Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Applicant's amendments to the claims filed 05 December 2025 have been entered. Applicant's remarks filed 05 December 2025 are acknowledged.
Claims 1 and 5 are in status “Currently amended.” Claims 2 – 4 and 6 – 14 are in status “Previously presented.” Claim 15 is in status “New.”
Response to Arguments
Applicant's arguments filed 05 December 2025 have been fully considered but they are not persuasive.
Applicant’s amendment to independent claim 1 specifying “the internal open space area is larger than a sum of the first bonding area and the second bonding area” is sufficient to overcome the rejection of record under 35 U.S.C. 102 as anticipated by Wan et al.
However, the rejections under 35 USC 103 as obvious over Wasamoto et al in view of Wan et al are maintained. The amended claim language is either taught by Wasamoto et al, is functional language describing the intended use of the device, or encompass product-by-process limitations.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1 – 15 are rejected under 35 U.S.C. 103 as being unpatentable over Wasamoto et al (WO 2018216673 A1, cited on the IDS provided 23 February 2023) in view of Wan et al (US 20170297019 A1).
With regards to claim 1, Wasamoto et al teaches;
The claimed “a first substrate” has been read on the taught (Figure 1, second microchip substrate 16; Page 3, paragraph 2, “The microchip 10 has a substantially flat plate shape in which a first microchip substrate 11 and a second microchip substrate 16 are joined…”);
The claimed “a second substrate that is partially bonded to the first substrate” has been read on the taught (Figure 1, first microchip substrate 11; Page 3, paragraph 2, “The microchip 10 has a substantially flat plate shape in which a first microchip substrate 11 and a second microchip substrate 16 are joined…”; Page 1, paragraph 2, “…a first microchip substrate and a second microchip substrate are bonded to each other…”);
The claimed “the second substrate having a first main surface, a second main surface, and an outer side face, the first main surface being located on one side of the first substrate, the second main surface being located on an opposite side of the first substrate” has been read on the taught (Page 3, paragraph 2, “The microchip 10 has a substantially flat plate shape in which a first microchip substrate 11 and a second microchip substrate 16 are joined in a stacked state in the thickness direction. One surface (the upper surface in FIG. 2) is the surface of the microchip 10. Inside the microchip 10, a micro flow path R is formed that includes a flow path groove 12 formed on the bonding surface (the lower surface in FIG. 2) of the first microchip substrate 11.”; The lower surface reads on a first main surface. The upper surface reads on a second main surface. The thickness direction reads on an outer side face.);
The claimed “at least a hollow channel that is located between the first substrate and the second substrate, the hollow channel extending in a direction along a predetermined portion of the first main surface of the second substrate without reaching the outer side face, the hollow channel having outer edges that define the extent of the hollow channel when viewed from a direction orthogonal to the first main surface” has been read on the taught (Figure 2, flow path groove 12; Page 3, paragraph 2, “Inside the microchip 10, a micro flow path R is formed that includes a flow path groove 12 formed on the bonding surface (the lower surface in FIG. 2) of the first microchip substrate 11.”);
The claimed “at least a liquid distribution port that is formed over the predetermined portion the hollow channel to penetrate the second substrate from the hollow channel toward the second main surface of the second substrate” has been read on the taught (Figure 2, inlet 13A; Page 3, paragraph 2, “The minute channel R communicates with an inlet 13A provided on one surface of the first microchip substrate 11 (the surface of the microchip 10) at one end...”);
The claimed “a first bonding section having a first bonding area with a bonding strength” and the first bonding section bonding “the first substrate to the second substrate completely surrounding the hollow channel along the outer edges of the hollow channel when viewed from a direction orthogonal to the first main surface” has been read on the taught (Page 3, paragraph 5, “The sealed space S is formed between the first microchip substrate 11 and the second microchip substrate 16, and has an annular inner joint portion 21 extending along the microchannel R.”; Page 12, paragraph 2, “…greater bonding strength can be obtained at the inner bonding portion 21 and the outer bonding portion 26.”; Inner joint portion 21 reads on the first bonding section. See also figures 1 and 2, reproduced on page 6 of this office action.);
The claimed first bonding section being “formed by a method of surface activation treatment under a predetermined heated condition including a step of irradiating with ultraviolet light and pressing with a predetermined pressing force” has been read on the taught (Page 2, paragraph 7, “…a method has been proposed in which the bonding surface of the microchip substrate is activated by irradiating the bonding surface of the microchip substrate with ultraviolet rays, and then bonded by bonding the microchip substrates.”).
Additionally, the above limitation is an example of a “Product-by-Process” limitation. According to MPEP 2113(I), “Product-by-process claims are not limited to the manipulations of the recited steps, only the structure implied by the steps.”—see In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).
The claimed “a second bonding section having a second bonding area with the bonding strength” and the second bonding section being “located completely outside of the first bonding section, the second bonding section being located at a position closer to the outer side face of the second substrate than the first bonding section for bonding the first substrate to the second substrate” has been read on the taught (Page 3, paragraph 5, “The outer bonding portion 26 is formed by bonding the outer peripheral edge portions of the bonding surfaces of the first microchip substrate 11 and the second and microchip substrates 16.”; Page 12, paragraph 2, “…greater bonding strength can be obtained at the inner bonding portion 21 and the outer bonding portion 26.”; Outer bonding portion 26 reads on the second bonding section. See also figures 1 and 2, reproduced on page 6 of this office action.);
The claimed second bonding section “with the bonding strength formed by the method of surface activation treatment” has been read on the taught (Page 2, paragraph 7, “…a method has been proposed in which the bonding surface of the microchip substrate is activated by irradiating the bonding surface of the microchip substrate with ultraviolet rays, and then bonded by bonding the microchip substrates.”).
Additionally, the above limitation is an example of a “Product-by-Process” limitation. According to MPEP 2113(I), “Product-by-process claims are not limited to the manipulations of the recited steps, only the structure implied by the steps.”—see In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).
The claimed “an internal open space having an internal open space area and devoid of any material and full of air provided in the second substrate, the first bonding section partially forming a first corner of the internal open space while the second bonding section partially forming a second corner opposite to the first corner of the internal open space,” has been read on the taught (Page 3, paragraph 5, “Further, in the microchip 10, an annular sealed space S is formed inside the microchip 10 so as to surround the minute flow path R.” Annular sealed space S reads on an internal open space. See also figures 1 and 2, reproduced on page 6 of this office action.).
Regarding the limitation “wherein the internal open space area is larger than a sum of the first bonding area and the second bonding area,” Wasamoto et al teaches that the volume of the internal open space depends on the materials of the microchip, but that the bonding area is preferentially a fraction of the total bonding surface, as read on the taught (Page 4, paragraph 2, “The volume of the sealed space S depends on the bonding area required in the microchip 10… These are determined appropriately in consideration of the constituent materials of the microchip substrate 11 and the second microchip substrate 16.”; Page 4, paragraph 3, “In the microchip 10, the bonding area is the area of the bonding surface (specifically, the area of the bonding surfaces of the first microchip substrate 11 and the second microchip substrate 16 from the viewpoint of bonding properties (bonding strength). ) Is preferably 10% or more, more preferably 10 to 40%.”)
Regarding the limitation wherein the internal open space is larger than a sum of the first bonding area and the second bonding area “for increasing the pressing force per unit area in both the first bonding area and the second bonding area,” this is functional language describing the intended purpose of the structural feature, and has been given the appropriate patentable weight. Wasamoto et al teaches that the size of the internal open space relates to the amount of deformation and handling a chip can accept during the bonding step, as read on the taught (Page 4, paragraph 6, “When the thickness of the inner barrier portion 22 is too small, fine processing in a mold for forming a microchip substrate is required, resulting in an increase in manufacturing cost. In addition, it is necessary to perform precise edge processing in the mold. If precise end processing is neglected, there arises a problem that a microchip substrate including a shape that becomes an obstructive factor for bonding, such as sink marks and burrs, is formed.”
Given these teachings, the limitation of “wherein the internal open space area is larger than a sum of the first bonding area and the second bonding area for increasing the pressing force per unit area in both the first bonding area and the second bonding area” would have been obvious to one of ordinary skill in the art as a results-effective variable subject to routine optimization, for the predictable result of managing the structural stability of the bonded chip.
However, Wasamoto et al does not explicitly disclose a gap devoid of any material and full of air and located on the second area for improving the bonding strength between the first substrate and the second substrate by accommodating thermal expansion effects by communicating the internal open space with outside.
In the analogous art of bonded microfluidic devices, Wan et al teaches;
A microfluidic device composed of two substrates, with a first and second bonding section, as read on the taught ([0078], “Each of the two pieces has one or more bonding areas where solvent will be applied to cause the two pieces to bond when they are pressed together.”; [0083], “The planar surface has a central portion 12 and a peripheral edge 13. A fluid retention groove 14 has been formed in the planar surface.”; Central portion 12 reads on a first bonding section. Peripheral edge 13 reads on a second bonding section. See also figures 5A-C, reproduced on page 8 of this office action.);
The claimed “a gap devoid of any material and full of air and located on the second area” has been read on the taught ([0083], “The first planar substrate 11 also includes a recess 20 formed in the groove 14 that joins the interior surface of the groove 14 to the peripheral edge 13 of the planar surface.”; Recess 20 reads on a gap.);
The claimed gap “communicating the internal open space with outside” has been read on the taught ([0094], “In some instances, a component planar substrate 11 has a recess 20 that joins the interior surface of the groove to the peripheral edge 13 of the planar surface. The recess 20 permits excess solvent to discharge from between the component planar substrates 11 of a device 10 during the bonding process.”; Recess 20 being capable of allowing excess solvent to discharge reads on the gap communicating internal open space with outside. See also figures 5A-C, reproduced on page 8 of this office action.);
Regarding the limitation of a gap “for improving the bonding strength between the first substrate and the second substrate by accommodating thermal expansion effects”, this limitation is functional language and has been given the appropriate patentable weight. Please see MPEP 2114(II), and Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990). As Wan et al teaches the structural limitation of the gap, this additional limitation does not define the instant application over the prior art.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the microchip as taught by Wasamoto et al with the internal space having a gap as taught by Wan et al. According to MPEP 2143(I)(C), use of a known technique to improve similar devices in the same way may be prima facie obvious. In the case of the instant invention, the prior art of Wasamoto et al contains a “base” device of a microchip with an internal space, upon which the microchip with the gap can be seen as an improvement. The prior art of Wan et al contains a comparable microchip with an internal space that has been improved with the inclusion of a gap. One of ordinary skill in the art could have applied the known improvement in the same way to the base device, for the predictable result of allowing temperature, pressure, or fluid materials to communicate between the internal and external spaces of the device.
With regards to claims 2-14, the microchip of claim 1 is obvious over Wasamoto et al in view of Wan et al.
The claim limitations of claims 2-14 all amount to variations on the shape, size, and orientation of the second bonding section. Per MPEP 2144.04(IV)(B), changes in shape are not sufficient to distinguish an instant invention over the prior art (See In reDailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) ). Likewise, MPEP 2144.02(IV)(A) recites that changes in size or proportion are not sufficient to distinguish over the prior art, provided that the instant invention does not perform differently than the prior art device (see Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
The instant specification does not disclose any unexpected results occurring from the shape, size, number, or orientation of the second bonding section. Accordingly, the limitations of claims 2-14 are not sufficient to define over the microchip as taught by Wasamoto et in view of Wan et al.
With regards to claim 15, Wasamoto et al teaches;
The claimed “a first substrate” has been read on the taught (Figure 1, second microchip substrate 16; Page 3, paragraph 2, “The microchip 10 has a substantially flat plate shape in which a first microchip substrate 11 and a second microchip substrate 16 are joined…”);
The claimed “a second substrate that is partially bonded to the first substrate” has been read on the taught (Figure 1, first microchip substrate 11; Page 3, paragraph 2, “The microchip 10 has a substantially flat plate shape in which a first microchip substrate 11 and a second microchip substrate 16 are joined…”; Page 1, paragraph 2, “…a first microchip substrate and a second microchip substrate are bonded to each other…”);
The claimed “the second substrate having a first main surface, a second main surface, and an outer side face, the first main surface being located on one side of the first substrate, the second main surface being located on an opposite side of the first substrate” has been read on the taught (Page 3, paragraph 2, “The microchip 10 has a substantially flat plate shape in which a first microchip substrate 11 and a second microchip substrate 16 are joined in a stacked state in the thickness direction. One surface (the upper surface in FIG. 2) is the surface of the microchip 10. Inside the microchip 10, a micro flow path R is formed that includes a flow path groove 12 formed on the bonding surface (the lower surface in FIG. 2) of the first microchip substrate 11.”; The lower surface reads on a first main surface. The upper surface reads on a second main surface. The thickness direction reads on an outer side face.);
The claimed “at least a hollow channel that is located between the first substrate and the second substrate, the hollow channel extending in a direction along a predetermined portion of the first main surface of the second substrate without reaching the outer side face, the hollow channel having outer edges that define the extent of the hollow channel when viewed from a direction orthogonal to the first main surface” has been read on the taught (Figure 2, flow path groove 12; Page 3, paragraph 2, “Inside the microchip 10, a micro flow path R is formed that includes a flow path groove 12 formed on the bonding surface (the lower surface in FIG. 2) of the first microchip substrate 11.”);
The claimed “at least a liquid distribution port that is formed over the predetermined portion the hollow channel to penetrate the second substrate from the hollow channel toward the second main surface of the second substrate” has been read on the taught (Figure 2, inlet 13A; Page 3, paragraph 2, “The minute channel R communicates with an inlet 13A provided on one surface of the first microchip substrate 11 (the surface of the microchip 10) at one end...”);
The claimed “a first bonding section having a first bonding area with a bonding strength” and the first bonding section bonding “the first substrate to the second substrate completely surrounding the hollow channel along the outer edges of the hollow channel when viewed from a direction orthogonal to the first main surface” has been read on the taught (Page 3, paragraph 5, “The sealed space S is formed between the first microchip substrate 11 and the second microchip substrate 16, and has an annular inner joint portion 21 extending along the microchannel R.”; Page 12, paragraph 2, “…greater bonding strength can be obtained at the inner bonding portion 21 and the outer bonding portion 26.”; Inner joint portion 21 reads on the first bonding section. See also figures 1 and 2, reproduced on page 6 of this office action.);
The claimed first bonding section being “formed by a method of surface activation treatment under a predetermined heated condition including a step of irradiating with ultraviolet light and pressing with a predetermined pressing force” has been read on the taught (Page 2, paragraph 7, “…a method has been proposed in which the bonding surface of the microchip substrate is activated by irradiating the bonding surface of the microchip substrate with ultraviolet rays, and then bonded by bonding the microchip substrates.”).
Additionally, the above limitation is an example of a “Product-by-Process” limitation. According to MPEP 2113(I), “Product-by-process claims are not limited to the manipulations of the recited steps, only the structure implied by the steps.”—see In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).
The claimed “a second bonding section having a plurality of second bonding areas with the bonding strength” and the second bonding section being “located completely outside of the first bonding section, the second bonding section being located at a position closer to the outer side face of the second substrate than the first bonding section for bonding the first substrate to the second substrate” has been read on the taught (Page 3, paragraph 5, “The outer bonding portion 26 is formed by bonding the outer peripheral edge portions of the bonding surfaces of the first microchip substrate 11 and the second and microchip substrates 16.”; Page 12, paragraph 2, “…greater bonding strength can be obtained at the inner bonding portion 21 and the outer bonding portion 26.”; Outer bonding portion 26 reads on the second bonding section. See also figures 1 and 2, reproduced on page 6 of this office action.);
Regarding the limitation of “a plurality of second bonding areas,” this is held to be mere duplication of parts. According to MPEP 2144.04(VI)(B), “mere duplication of parts has no patentable significance unless a new and unexpected result is produced.”—see In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Wasamoto et al with the plurality of second bonding areas, for the purpose of adding stability and structure to the device.
The claimed second bonding section “with the bonding strength formed by the method of surface activation treatment” has been read on the taught (Page 2, paragraph 7, “…a method has been proposed in which the bonding surface of the microchip substrate is activated by irradiating the bonding surface of the microchip substrate with ultraviolet rays, and then bonded by bonding the microchip substrates.”).
Additionally, the above limitation is an example of a “Product-by-Process” limitation. According to MPEP 2113(I), “Product-by-process claims are not limited to the manipulations of the recited steps, only the structure implied by the steps.”—see In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).
The claimed “an internal open space having an internal open space area and devoid of any material and full of air provided in the second substrate, the first bonding section partially forming a first corner of the internal open space while the second bonding section partially forming a second corner opposite to the first corner of the internal open space,” has been read on the taught (Page 3, paragraph 5, “Further, in the microchip 10, an annular sealed space S is formed inside the microchip 10 so as to surround the minute flow path R.” Annular sealed space S reads on an internal open space. See also figures 1 and 2, reproduced on page 6 of this office action.).
Regarding the limitation “the internal open space area being larger than a sum of the first bonding area and the plurality of the second bonding areas,” Wasamoto et al teaches that the volume of the internal open space depends on the materials of the microchip, but that the bonding area is preferentially a fraction of the total bonding surface, as read on the taught (Page 4, paragraph 2, “The volume of the sealed space S depends on the bonding area required in the microchip 10… These are determined appropriately in consideration of the constituent materials of the microchip substrate 11 and the second microchip substrate 16.”; Page 4, paragraph 3, “In the microchip 10, the bonding area is the area of the bonding surface (specifically, the area of the bonding surfaces of the first microchip substrate 11 and the second microchip substrate 16 from the viewpoint of bonding properties (bonding strength). ) Is preferably 10% or more, more preferably 10 to 40%.”)
Regarding the limitation wherein the internal open space is larger than a sum of the first bonding area and the second bonding area “for increasing the pressing force per unit area in both the first bonding area and the second bonding area,” this is functional language describing the intended purpose of the structural feature, and has been given the appropriate patentable weight. Wasamoto et al teaches that the size of the internal open space relates to the amount of deformation and handling a chip can accept during the bonding step, as read on the taught (Page 4, paragraph 6, “When the thickness of the inner barrier portion 22 is too small, fine processing in a mold for forming a microchip substrate is required, resulting in an increase in manufacturing cost. In addition, it is necessary to perform precise edge processing in the mold. If precise end processing is neglected, there arises a problem that a microchip substrate including a shape that becomes an obstructive factor for bonding, such as sink marks and burrs, is formed.”
Given these teachings, the limitation of “wherein the internal open space area is larger than a sum of the first bonding area and the second bonding area for increasing the pressing force per unit area in both the first bonding area and the second bonding area” would have been obvious to one of ordinary skill in the art as a results-effective variable subject to routine optimization, for the predictable result of managing the structural stability of the bonded chip.
However, Wasamoto et al does not explicitly disclose a gap devoid of any material and full of air and located on the second area for improving the bonding strength between the first substrate and the second substrate by accommodating thermal expansion effects by communicating the internal open space with outside.
In the analogous art of bonded microfluidic devices, Wan et al teaches;
A microfluidic device composed of two substrates, with a first and second bonding section, as read on the taught ([0078], “Each of the two pieces has one or more bonding areas where solvent will be applied to cause the two pieces to bond when they are pressed together.”; [0083], “The planar surface has a central portion 12 and a peripheral edge 13. A fluid retention groove 14 has been formed in the planar surface.”; Central portion 12 reads on a first bonding section. Peripheral edge 13 reads on a second bonding section. See also figures 5A-C, reproduced on page 8 of this office action.);
The claimed “a gap devoid of any material and full of air and located on the second area” has been read on the taught ([0083], “The first planar substrate 11 also includes a recess 20 formed in the groove 14 that joins the interior surface of the groove 14 to the peripheral edge 13 of the planar surface.”; Recess 20 reads on a gap.);
Regarding the limitation of “a plurality of gaps,” this is held to be mere duplication of parts. According to MPEP 2144.04(VI)(B), “mere duplication of parts has no patentable significance unless a new and unexpected result is produced.”—see In reHarza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Wasamoto et al in view of Wan et al with the plurality of gaps, for the purpose of optimizing communication between the internal open space with the outside.
The claimed gap “communicating the internal open space with outside” has been read on the taught ([0094], “In some instances, a component planar substrate 11 has a recess 20 that joins the interior surface of the groove to the peripheral edge 13 of the planar surface. The recess 20 permits excess solvent to discharge from between the component planar substrates 11 of a device 10 during the bonding process.”; Recess 20 being capable of allowing excess solvent to discharge reads on the gap communicating internal open space with outside. See also figures 5A-C, reproduced on page 8 of this office action.);
Regarding the limitation of a gap “for improving the bonding strength between the first substrate and the second substrate by accommodating thermal expansion effects”, this limitation is functional language and has been given the appropriate patentable weight. Please see MPEP 2114(II), and Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990). As Wan et al teaches the structural limitation of the gap, this additional limitation does not define the instant application over the prior art.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the microchip as taught by Wasamoto et al with the internal space having a gap as taught by Wan et al. According to MPEP 2143(I)(C), use of a known technique to improve similar devices in the same way may be prima facie obvious. In the case of the instant invention, the prior art of Wasamoto et al contains a “base” device of a microchip with an internal space, upon which the microchip with the gap can be seen as an improvement. The prior art of Wan et al contains a comparable microchip with an internal space that has been improved with the inclusion of a gap. One of ordinary skill in the art could have applied the known improvement in the same way to the base device, for the predictable result of allowing temperature, pressure, or fluid materials to communicate between the internal and external spaces of the device.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALISON CLAIRE GERHARD whose telephone number is (571)270-0945. The examiner can normally be reached M-F, 9:00 - 5:30pm EST.
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/ALISON CLAIRE GERHARD/ Examiner, Art Unit 1797 /LYLE ALEXANDER/ Supervisory Patent Examiner, Art Unit 1797