DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, 7 and 9-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xiong et al. (US 2021/0295795).
Regarding claim 1
Xiong et al. shows the array substrate (101, see para. 0031), comprising:
a plurality of gate on array (GOA) units (see for example Fig. 2, GOA1-GOA2n);
a plurality of clock signal lines (201) disposed on a side of the GOA units (GOA1-GOA2n) and arranged in sequence in a first direction (taken to be the direction shown in Fig. 2); and
a plurality of communication lines (202, see Fig. 202), wherein one of the communication lines is correspondingly connected to one of the clock signal lines and one of the GOA units (see connection lines connected to clock lines 201 and GOA units, see Fig. 2), and wherein
a winding area (taken to be area 400, see Fig. 2) is provided between the clock signal lines (201) and the GOA units (see Fig. 2), each communication line (2020 comprises a first part (taken to be the left side of area 400, see Fig. 2), a winding part (400) , and a second part connected in sequence (taken to be the right side of area 400, see Fig. 2), the first part is connected to one of the clock signal lines (201, see Fig. 2), the second part (right side of 400) is connected to one of the GOA units (see Fig. 2), and the winding part (400) is disposed in the winding area (taken to be area 400, see Fig. 2);
the winding part (400) comprises a plurality of first connection lines (taken to be a connection, connecting to the left side of the bent area 400, see Fig. 2) a plurality of second connection lines (taken to be the connections, connecting to the right side of the bent area 400, see Fig. 2), and a plurality of bent connection lines (taken to be bent sections shown in area 400, see Fig. 2), each bent connection line connects between one of the first connection lines (taken to be a connection, connecting to the left side of the bent area 400, see Fig. 2) and one of the second connection lines (taken to be a connection, connecting to the right side of the bent area 400, see Fig. 2), each first connection line (202) is disposed opposite to one of the clock signal lines (201, taken the connection shown in Fig. 2 , and each second connection line (right side of 400) is disposed opposite to one of the GOA units (take to be connection shown in Fig. 2); and
lateral capacitances (taken to be inherently included as described as capacitance in para 0036) formed by the plurality of first connection lines and the clock signal lines (see para. 0036) are equal (taken to be inherent as described in para. 0046 0044 and 0046, by having the clock signa branch lines 202 connected to GOA and the area of the capacitance compensation unit 300 on the clock signal branch lines 202 connected to the GOAn+1 are equal), and/or lateral capacitances formed by the plurality of second connection lines and the GOA units are equal (also taken to be inherent as described in para. 0046 0044 and 0046, by having the clock signa branch lines 202 connected to GOA and the area of the capacitance compensation unit 300 on the clock signal branch lines 202 connected to the GOAn+1 are equal).
Regarding claim 4
Xiong et al. further shows, wherein the plurality of communication lines have a same length (see para. 0044 that describes having distance between the capacitance compensation unit 300 and wire is equal to the preterminal distance to avoid mutual coupling between the capacitance compensation unit 300 and the wire).
Regarding claim 7
Xiong et al. further shows, wherein each communication line comprises one of the first connection lines (taken to be the connections, connecting to the left side of the bent area 400, see Fig. 2), one of the second connection lines (taken to be the connections, connecting to the right side of the bent area 400, see Fig. 2), and one of the bent connection lines (bent section shown in area 400).
Regarding claim 9
Xiong et al. further shows, wherein each bent connection line comprises a plurality of bent units connected in sequence (Figs. 2 and 3 show each of the bent areas includes a plurality of bent units), and the bent units are respectively connected to the first connection lines (taken to be the connections, connecting to the left side of the bent area 400, see Fig. 2) and the second connection lines by traces (taken to be the connections, connecting to the right side of the bent area 400, see Fig. 2).
Regarding claim 10
Xiong et al. further shows, wherein at least one parallel trace is further connected to the bent units (Figs. 2 and 3 show each of the bent areas includes a plurality of bent units that are parallel), and the parallel trace is disposed in parallel with each bent connection line (see Figs. 2 and 3, bent area 400).
Regarding claim 11
Xiong et al. further shows, wherein each clock signal line (201) is connected to the plurality of communication lines (202, see Figs. 2 and 3), and a set of the communication lines (202) comprising at least one communication line (202) are connected to the clock signal lines (201) in sequence in a direction in which the clock signal lines are arranged (see Figs. 2 and 3, that shows the clock signal line and communication lines connected in sequence in a direction of the clock signal lines).
Allowable Subject Matter
Claims 2, 3, 5, 6, 8, 12 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 14-20 are allowed over the prior art of record.
The following is an Examiner's Statement of Reasons for Allowance:
Regarding claim 2
The prior art of record, including Xiong et al. (US 2021/0295795), taken to be the closest prior art noted in the above rejection to the claims, taken alone or in combination does not teach, suggest or render obvious the array substrate, as recited in claim 1, having the combination of elements, along with having the further limitations which include:
wherein in a second direction that intersects with the first direction, the plurality of first connection lines have a same length, and/or the plurality of second connection lines have a same length, as recited in claim 2.
Further, even though Xiong et al. shows the invention substantially as claimed, as discussed in the above rejections, it does not specifically show or render obvious the limitations of claim 2, noted above.
Also, none of the prior art of record teaches having in a second direction that intersects with the first direction, the plurality of first connection lines have a same length, and/or the plurality of second connection lines have a same length, as recited in claim 2.
Therefore, it is believed that one of ordinary skilled in the art at the time the invention was filed, would not consider it obvious to modify Xiong et al., with any of the prior art of record, to include the limitations as recited in claim 2.
Regarding claim 3
The prior art of record, including Xiong et al. (US 2021/0295795), taken to be the closest prior art noted in the above rejection to the claims, taken alone or in combination does not teach, suggest or render obvious the array substrate, as recited in claim 1, having the combination of elements, along with having the further limitations which include:
wherein in the first direction, distances between the plurality of first connection lines and the clock signal lines are equal, and/or distances between the plurality of second connection lines and the GOA units are equal, as recited in claim 3.
Further, even though Xiong et al. shows the invention substantially as claimed, as discussed in the above rejections, it does not specifically show or render obvious the limitations of claim 3, noted above.
Also, none of the prior art of record teaches having in the first direction, distances between the plurality of first connection lines and the clock signal lines are equal, and/or distances between the plurality of second connection lines and the GOA units are equal, as recited in claim 3.
Therefore, it is believed that one of ordinary skilled in the art at the time the invention was filed, would not consider it obvious to modify Xiong et al., with any of the prior art of record, to include the limitations as recited in claim 3.
Regarding claim 5
The prior art of record, including Xiong et al. (US 2021/0295795), taken to be the closest prior art noted in the above rejection to the claims, taken alone or in combination does not teach, suggest or render obvious the array substrate, as recited in claim 1, having the combination of elements, along with having the further limitations which include:
wherein each first connection line comprises a first trace, a second trace, and a third trace, the first trace is disposed on a side away from the bent connection lines, the second trace is spaced apart from the first trace, the second trace is connected to the bent connection line, the third trace is connected between the first trace and the second trace, and the first trace and the second trace have a same length or different lengths, as recited in claim 5.
Further, even though Xiong et al. shows the invention substantially as claimed, as discussed in the above rejections, it does not specifically show or render obvious the limitations of claim 5, noted above.
Also, none of the prior art of record teaches having each first connection line comprises a first trace, a second trace, and a third trace, the first trace is disposed on a side away from the bent connection lines, the second trace is spaced apart from the first trace, the second trace is connected to the bent connection line, the third trace is connected between the first trace and the second trace, and the first trace and the second trace have a same length or different lengths, as recited in claim 5.
Therefore, it is believed that one of ordinary skilled in the art at the time the invention was filed, would not consider it obvious to modify Xiong et al., with any of the prior art of record, to include the limitations as recited in claim 5.
Regarding claim 6
The prior art of record, including Xiong et al. (US 2021/0295795), taken to be the closest prior art noted in the above rejection to the claims, taken alone or in combination does not teach, suggest or render obvious the array substrate, as recited in claim 1, having the combination of elements, along with having the further limitations which include:
wherein the each second connection line comprises a first wire, a second wire, and a third wire, the first wire is disposed on a side away from the each bent connection line, the second wire and the first wire are disposed in parallel and spaced apart by a spacing, the second wire is connected to the each bent connection line, the third wire is connected between the first wire and the second wire, and the first wire and the second wire have a same length or different lengths, as recited in claim 6.
Further, even though Xiong et al. shows the invention substantially as claimed, as discussed in the above rejections, it does not specifically show or render obvious the limitations of claim 6, noted above.
Also, none of the prior art of record teaches having the each second connection line comprises a first wire, a second wire, and a third wire, the first wire is disposed on a side away from the each bent connection line, the second wire and the first wire are disposed in parallel and spaced apart by a spacing, the second wire is connected to the each bent connection line, the third wire is connected between the first wire and the second wire, and the first wire and the second wire have a same length or different lengths, as recited in claim 6.
Therefore, it is believed that one of ordinary skilled in the art at the time the invention was filed, would not consider it obvious to modify Xiong et al., with any of the prior art of record, to include the limitations as recited in claim 6.
Regarding claim 8
The prior art of record, including Xiong et al. (US 2021/0295795), taken to be the closest prior art noted in the above rejection to the claims, taken alone or in combination does not teach, suggest or render obvious the array substrate, as recited in claim 1, having the combination of elements, along with having the further limitations which include:
wherein each communication line comprises at least two of the first connection lines, at least two of the second connection lines, and one of the bent connection lines, as recited in claim 8.
Further, even though Xiong et al. shows the invention substantially as claimed, as discussed in the above rejections, it does not specifically show or render obvious the limitations of claim 8, noted above.
Also, none of the prior art of record teaches having each communication line comprises at least two of the first connection lines, at least two of the second connection lines, and one of the bent connection lines, as recited in claim 8.
Therefore, it is believed that one of ordinary skilled in the art at the time the invention was filed, would not consider it obvious to modify Xiong et al., with any of the prior art of record, to include the limitations as recited in claim 8.
Regarding claim 12
The prior art of record, including Xiong et al. (US 2021/0295795), taken to be the closest prior art noted in the above rejection to the claims, taken alone or in combination does not teach, suggest or render obvious the array substrate, as recited in claim 11, having the combination of elements, along with having the further limitations which include:
wherein in each set of the communication lines, in a second direction that intersects the first direction, the first parts are increasingly enlarged and bending lengths of the bent connection lines are gradually shortened, as recited in claim 12.
Further, even though Xiong et al. shows the invention substantially as claimed, as discussed in the above rejections, it does not specifically show or render obvious the limitations of claim 12, noted above.
Also, none of the prior art of record teaches having in each set of the communication lines, in a second direction that intersects the first direction, the first parts are increasingly enlarged and bending lengths of the bent connection lines are gradually shortened, as recited in claim 12.
Therefore, it is believed that one of ordinary skilled in the art at the time the invention was filed, would not consider it obvious to modify Xiong et al., with any of the prior art of record, to include the limitations as recited in claim 12.
Regarding claim 13
The prior art of record, including Xiong et al. (US 2021/0295795), taken to be the closest prior art noted in the above rejection to the claims, taken alone or in combination does not teach, suggest or render obvious the array substrate, as recited in claim 11, having the combination of elements, along with having the further limitations which include:
wherein in each set of the communication lines, in a second direction that intersects the first direction, the first parts are increasingly enlarged and bending spacings between the bent connection lines are gradually shortened, as recited in claim 13.
Further, even though Xiong et al. shows the invention substantially as claimed, as discussed in the above rejections, it does not specifically show or render obvious the limitations of claim 13, noted above.
Also, none of the prior art of record teaches having in each set of the communication lines, in a second direction that intersects the first direction, the first parts are increasingly enlarged and bending spacings between the bent connection lines are gradually shortened, as recited in claim 13.
Therefore, it is believed that one of ordinary skilled in the art at the time the invention was filed, would not consider it obvious to modify Xiong et al., with any of the prior art of record, to include the limitations as recited in claim 13.
Regarding claims 14-20
The prior art of record, including Xiong et al. (US 2021/0295795), taken to be the closest prior art noted in the above rejection to the claims, taken alone or in combination does not teach, suggest or render obvious the display panel, as recited in claim 14, having the combination of elements, along with having the further limitations which include:
a counter substrate disposed opposite to the array substrate, wherein electrodes are disposed on the counter substrate corresponding to the communication lines and the clock signal lines, as recited in claims 14-20.
Further, even though Xiong et al. shows the invention substantially as claimed, as discussed in the above rejections, it does not specifically show or render obvious the limitations of claims 14-20, noted above.
Also, none of the prior art of record teaches
a counter substrate disposed opposite to the array substrate, wherein electrodes are disposed on the counter substrate corresponding to the communication lines and the clock signal lines, as recited in claim 14-20.
Therefore, it is believed that one of ordinary skilled in the art at the time the invention was filed, would not consider it obvious to modify Xiong et al., with any of the prior art of record, to include the limitations as recited in claim 14-20.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Gao et al. (US 2022/0114980), shows display device having an array substrate having clock signal lines (11), GOA units (64), connection lines (101 and 102) and bent connections (32-34) (see the abstract, Figs. 8-16, and para. 0060-0076).
Xiao et al. (US 2022/0122503), shows display device having an array substrate having clock signal lines (4) , GOA units (3), connection lines (60) and bent connections (60) (see also the abstract, Figs. 1-4, and para. 0055, 0060, 0063 and 0074).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUHAMMAD N EDUN whose telephone number is (571)272-7617. The examiner can normally be reached Mon-Fri 10:00-6:30.
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/MUHAMMAD N. EDUN/
Primary Patent Examiner
Art Unit 2629
/MUHAMMAD N EDUN/ Primary Examiner, Art Unit 2629
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