Response to Arguments
Applicant's arguments filed 07/23/2025 have been fully considered but they are not persuasive. The Applicant argues that Peng et al. (US 2021/0265439 A1; hereinafter “Peng”) in view of Qu (US 2021/0210528 A1) fails to teach the following limitations:
a first drain, disposed on an outer side of the interlayer insulating layer away from the first source
wherein the other part of the first active layer is on an outer surface of the interlayer insulating layer away from the first source.
The examiner respectfully disagrees with this argument. The Examiner notes that while the applicant has shown that Peng fails to teach the limitation, Applicant has not shown how Qu fails to disclose the limitations. The examiner asserts the limitations of Claim 1 and 11 are met by Peng in view of Qu as shown below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites the limitation " the surface of the interlayer insulating layer facing away from the first source" in line 4. There is insufficient antecedent basis for this limitation in the claim. The term “the surface” can be applied to multiple surfaces of the interlayer insulating layer, and therefore it is unclear which surface the Applicant is referencing in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5, 11-12 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Peng et al. (US 2021/0265439 A1; hereinafter “Peng”), and further in view of Qu (US 2021/0210528 A1).
In regard to claim 1, Peng teaches an array substrate (OLED array substrate) (Fig. 2 and paragraph 26), comprising a first thin film transistor (TFT) of a vertical structure (200) (Fig. 1 and paragraph 37), the first TFT comprising:
a first source (the first electrode 10A) (Fig. 1 and paragraph 35);
an interlayer insulating layer (the portion of the device containing the first and second interlayer dielectric layer 60B and 60A) (Fig. 1 and paragraph 46), covering the first source (the dielectric layer 60B is shown covering first electrode 10A in Fig. 1), wherein a hole penetrates the interlayer insulating layer to expose part of the first source (a hole penetrating the dielectric layer 60B and exposing first electrode 10A is shown in Fig. 1);
a first gate (a gate electrode 50A), fully embedded in the interlayer insulating layer and at a side of the hole (the gate electrode 50A is embedded between the first and second interlayer dielectric layer 60B and 60A and extends outward to the topside and to the left of the hole in the first interlayer dielectric layer 60B as shown in Fig. 1) (Fig. 1 and paragraph 46);
a first drain (a second electrode 20A) (Fig. 1 and paragraph 35), and
a first active layer (an active layer 30A) (Fig. 1 and paragraph 33), part of the first active layer being disposed in the hole and being electrically connected to the first source and the first drain (the active layer 30A is seen in the hole and connected to 10A and 20A in Fig. 1).
However, Peng doesn’t explicitly teach the first drain, disposed on an outer side of the interlayer insulating layer away from the first source;
the first drain covers another part of the first active layer, wherein the other part of the first active layer is on an outer surface of the interlayer insulating layer away from the first source.
Qu teaches an array substrate (100) (Fig. 19 and paragraph 39), a first drain (a second electrode 19 which functions as a drain) (Fig. 16 and paragraphs 109 and 111), disposed on an outer side of an interlayer insulating layer away from the first source (the second electrode 19 is shown disposed on an isolating layer 13 in Fig. 16 away from a first electrode 18 which functions as a source) (Fig. 16 and paragraphs 83, 109 and 111); wherein a first drain (the second electrode 19 which functions as a drain) covers another part of a first active layer (active layer 15) (Fig. 16 and paragraphs 109 and 111), wherein the other part of the first active layer is on an outer surface of the interlayer insulating layer away from the first source (the active layer 15 is shown on the exposed surface of the isolating layer 13 functions as an outer surface in Fig. 16).
It would have been obvious to one skilled in the art at the time to have the first drain, disposed on an outer side of the interlayer insulating layer away from the first source, the first drain cover another part of the first active layer, wherein the other part of the first active layer is on an outer surface of the interlayer insulating layer away from the first source. since this layout is well known to facilitate connections within the device while providing protections against unwanted shorts. Further the placement of components are merely a rearrangement of parts and limitations such as this are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical.
In regard to claim 2, Peng teaches wherein the first active layer is disposed on a side wall and a bottom of the hole and extends to the interlayer insulating layer away from the first source (the active layer 30A extending along the side wall and hole extending toward the second interlayer dielectric layer 60A which is in the topside direction is shown in Fig. 1).
In regard to claim 5, Peng teaches wherein a drain opening (opening in the second interlayer dielectric layer 60A that encompasses 20-50 A) corresponding to the hole is disposed on the first drain (opening in the second interlayer dielectric layer 60A that encompasses 20-50 A is corresponds to the hole in 60B due to being above it and is shown away from first electrode 10A as shown in Fig. 1) (Fig. 1 and paragraph 46).
In regard to claim 11, Peng teaches a display panel (OLED display device) comprising an array substrate (100) and an opposing substrate (400) disposed opposite the array substrate (Fig. 2 and paragraph 50), the array substrate comprising a first thin film transistor (TFT) (200) of a vertical structure (Fig. 2 and paragraph 37), the first TFT comprising:
a first source (the first electrode 10A) (Fig. 2 and paragraph 37);
an interlayer insulating layer (the portion of the device containing the first and second interlayer dielectric layer 60B and 60A) (Fig. 1 and paragraph 46), covering the first source (the first interlayer dielectric layer 60B is shown covering first electrode 10A in Fig. 2), wherein a hole penetrates the interlayer insulating layer to expose part of the first source (a hole penetrating the first interlayer dielectric layer 60B exposing first electrode 10A is shown in Fig. 2);
a first gate (a gate electrode 50A), fully embedded in the interlayer insulating layer and at a side of the hole (the gate electrode 50A is embedded in between the first and second interlayer dielectric layer 60B and 60A and extends outward to the topside and to the left of the hole in the first interlayer dielectric layer 60B as shown in Fig. 1) (Fig. 1 and paragraph 46);
a first drain (a second electrode 20A) (Fig. 1 and paragraph 35), and
a first active layer (an active layer 30A) (Fig .1 and paragraph 33), part of the first active layer being disposed in the hole and being electrically connected to the first source and the first drain (the active layer 30A is seen in the hole and connected to 10A and 20A in Fig. 1).
However, Peng doesn’t explicitly teach the first drain, disposed on an outer side of the interlayer insulating layer away from the first source;
the first drain covers another part of the first active layer, wherein the other part of the first active layer is on an outer surface of the interlayer insulating layer away from the first source.
Qu teaches an array substrate (100) (Fig. 19 and paragraph 39), a first drain (a second electrode 19 which functions as a drain) (Fig. 16 and paragraphs 109 and 111), disposed on an outer side of an interlayer insulating layer (an isolating layer 13 and a gate insulating layer 16 functions ) away from the first source (the second electrode 19 is shown disposed on an isolating layer 13 in Fig. 16 away from a first electrode 18 which functions as a source) (Fig. 16 and paragraphs 83, 109 and 111); wherein a first drain (the second electrode 19 which functions as a drain) covers another part of a first active layer (active layer 15) (Fig. 16 and paragraphs 109 and 111), wherein the other part of the first active layer is on an outer surface of the interlayer insulating layer away from the first source (the active layer 15 is shown on the exposed surface of the isolating layer 13 functions as an outer surface in Fig. 16).
It would have been obvious to one skilled in the art at the time to have the first drain, disposed on an outer side of the interlayer insulating layer away from the first source, the first drain cover another part of the first active layer, wherein the other part of the first active layer is on an outer surface of the interlayer insulating layer away from the first source. since this layout is well known to facilitate connections within the device while providing protections against unwanted shorts. Further the placement of components are merely a rearrangement of parts and limitations such as this are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical.
In regard to claim 12, Peng teaches wherein the first active layer is disposed on a side wall and a bottom of the hole and extends to the interlayer insulating layer away from the first source (the active layer 30A extending along the side wall and hole extending toward the second interlayer dielectric layer 60A which is in the topside direction is shown in Fig. 2).
In regard to claim 15, Peng teaches wherein a drain opening (opening in the second interlayer dielectric layer 60A that encompasses 20-50 A) corresponding to the hole is disposed on the first drain and covers part of the first active layer on the interlayer insulating layer away from the first source (opening in the second interlayer dielectric layer 60A that encompasses 20-50 A is corresponds to the hole in 60B due to being above it and is shown away from first electrode 10A as shown in Fig. 1) (Fig. 1 and paragraph 46).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Peng in view of Qu as applied to claim 1 or 11 above, and further in view of Ma (US 2014/0077298 A1).
In regard to claim 13, Peng in view of Qu doesn’t explicitly teach the display panel (OLED display device) wherein the first gate is disposed around the first active layer arranged on the side wall of the hole.
Ma teaches a display panel (display device) (paragraph 1), wherein a first gate (gate electrode 100 including gate electrode protrusions 101a and 101b) is disposed around the first active layer arranged on the side wall of a hole (hole created by the gate insulating layer 200 that exposes the source/drain layer 400) (Fig. 6 and paragraphs 28-29).
It would have been obvious to one of ordinary skill, in the art at the time, to modify Peng in view of Qu with the teachings of Ma to have the first gate is disposed around the first active layer arranged on the side wall of the hole since this layout allows for the gate electrode to influence the active layer from multiple direction which in turn can enhance ON current Ion of the TFT as taught by Ma (paragraph 29).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Peng in view of Qu and Ma as applied to 13 above, and further in view of Nan (US 10,985,187 B1).
In regard to claim 14, Peng in view of Qu and Ma teach wherein a gate opening is disposed on the first gate (gate electrode opening is between gates electrode protrusions 101A and 101b of gate electrode 100 as shown in Ma Fig. 6); the hole is embedded in the gate opening (the hole created by the gate insulating layer 200 that exposes the source/drain layer 400 in embedded between 101A and 101B as shown in Ma Fig. 6).
However, Peng in view of Qu and Ma doesn’t explicitly teach a projection of a gate opening perpendicular to a direction of an interlayer insulating layer being circular, and a projection of a hole perpendicular to a direction of the interlayer insulating layer being circular.
Nan teaches a display panel (100) ([Col.4, ln.26-29]), wherein a projection of a gate opening (opening created by gate electrode 210) perpendicular to a direction of an interlayer insulating layer (241) being circular (circular shape of opening created by gate electrode shown in Fig. 4) (Figs.1 and Fig.4 and [Col.5, ln.20-29]) , and a projection of a hole (2422) perpendicular to a direction of the interlayer insulating layer being circular (opening 2422 is circular due to shape of first end 230 having a circular shape as shown in Fig. 4) (Fig.1, Fig.4 and [Col. 5, ln.46-50]).
It would have been obvious to one of ordinary skill, in the art at the time, to modify Peng in view of Qu and Ma with the teachings of Nan to have a projection of the gate opening perpendicular to a direction of the interlayer insulating layer being circular, and a projection of the hole perpendicular to a direction of the interlayer insulating layer being circular since this layout allows for a device with a higher display resolution as taught by Nan ([Col.8, ln.57-67],[Col.9, ln.1-2]).
Claims 6 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Peng in view of Qu as applied to claim 1 or 11 above, and further in view of Shin et al. (US 2015/0378182 A1; hereinafter “Shin”).
In regard to claim 6, Peng doesn’t explicitly teach wherein the interlayer insulating layer comprises a silicon nitride layer and a silicon oxide layer; the silicon nitride layer and the silicon oxide layer are disposed on the interlayer insulating layer from bottom to top; the first gate is disposed on the silicon nitride layer; the silicon oxide layer covers the first gate.
Shin teaches an array substrate (310) (paragraph 45), wherein a interlayer insulating layer (125 and 135) comprises a silicon nitride (gate insulating layer 125 is formed of silicon nitride) layer and a silicon oxide layer (interdielectric insulating layer 135 is formed of a silicon oxide) (Fig. 1 and paragraphs 36-37); the silicon nitride layer and the silicon oxide layer are disposed on the interlayer insulating layer from bottom to top (gate insulating layer 125 is under interdielectric insulating layer 135 as shown in Fig. 1); a first gate (131) is disposed on the silicon nitride layer (gate electrode is over gate insulating layer 125 formed of silicon nitride as shown in Fig. 1); the silicon oxide layer covers the first gate (interdielectric insulating layer 135 formed of silicon oxide is over gate electrode 135 as shown in Fig. 1).
It would have been obvious to one of ordinary skill, in the art at the time, to modify Peng with the teachings of Shin to have the interlayer insulating layer comprises a silicon nitride layer and a silicon oxide layer; the silicon nitride layer and the silicon oxide layer are disposed on the interlayer insulating layer from bottom to top; the first gate is disposed on the silicon nitride layer; the silicon oxide layer covers the first gate since this layout along with the selected materials are well known to allows for increased insulation an short protection within the device.
Shin teaches an array substrate (310) (paragraph 45), wherein material of a first active layer (120) comprises a metal oxide (active layer 120 can be formed of gallium oxide or indium oxide) (Fig. 1 and paragraph 35).
It would have been obvious to one of ordinary skill, in the art at the time, to modify Peng in view of Qu with the teachings of Shin to have the active layer comprise a metal oxide since if the active layer is made of oxide, a high mobility can be obtained at a low temperature as taught by Shin (paragraph 8)
In regard to claim 16, Peng doesn’t explicitly teach wherein the interlayer insulating layer comprises a silicon nitride layer and a silicon oxide layer; the silicon nitride layer and the silicon oxide layer are disposed on the interlayer insulating layer from bottom to top; the first gate is disposed on the silicon nitride layer; the silicon oxide layer covers the first gate.
Shin teaches a display panel (display device) (paragraphs 5 and 12), wherein a interlayer insulating layer (125 and 135) comprises a silicon nitride (gate insulating layer 125 is formed of silicon nitride) layer and a silicon oxide layer (interdielectric insulating layer 135 is formed of a silicon oxide) (Fig. 1 and paragraphs 36-37); the silicon nitride layer and the silicon oxide layer are disposed on the interlayer insulating layer from bottom to top (gate insulating layer 125 is under interdielectric insulating layer 135 as shown in Fig. 1); a first gate (131) is disposed on the silicon nitride layer (gate electrode is over gate insulating layer 125 formed of silicon nitride as shown in Fig. 1); the silicon oxide layer covers the first gate (interdielectric insulating layer 135 formed of silicon oxide is over gate electrode 135 as shown in Fig. 1).
It would have been obvious to one of ordinary skill, in the art at the time, to modify Peng with the teachings of Shin to have the interlayer insulating layer comprises a silicon nitride layer and a silicon oxide layer; the silicon nitride layer and the silicon oxide layer are disposed on the interlayer insulating layer from bottom to top; the first gate is disposed on the silicon nitride layer; the silicon oxide layer covers the first gate since this layout is known to allows for increased insulation an short protection within the device.
In regard to claim 17, Peng does not explicitly teach wherein material of the first active layer comprises a metal oxide.
Shin teaches a display panel (display device) (paragraphs 5 and 12), wherein material of a first active layer (120) comprises a metal oxide (active layer 120 can be formed of gallium oxide or indium oxide) (Fig. 1 and paragraph 35).
It would have been obvious to one of ordinary skill, in the art at the time, to modify Peng with the teachings of Shin to have the active layer comprise a metal oxide since if the active layer is made of oxide, a high mobility can be obtained at a low temperature as taught by Shin (paragraph 8).
Claims 8-10 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Peng in view of Qu as applied to claim 1 or 11 above, and further in view of Shi (US 2018/0061994 A1).
In regard to claim 8, Peng teaches the array substrate wherein a second TFT (300) comprises a second active layer (30B) (Fig. 1 and paragraph 34), a second gate (50B) (Fig. 1 and paragraph 41), a second source (10B), and a second drain (20B) (Fig. 1 and paragraph 34); the second gate and the first source are disposed in the same layer (both first electrode 10A and gate electrode 50B are in the layer disposed on 40B as shown in Fig. 1);
the second source, the second drain, and the first drain are disposed in the same layer (second electrode 20A, first electrode 10B and a second electrode 20B all are disposed in the layer above 60B as shown in Fig. 1).
However, Peng in view of Qu doesn’t explicitly teach the array substrate, further comprising a display area and a non-display area; the first TFT is disposed on the display area; the array substrate further comprises a second TFT disposed on the non-display area.
Shi teaches an array substrate (paragraph 113), further comprising a display area (20) and a non-display area (10) (Fig. 10a and paragraph 113); the first TFT (200) is disposed on the display area (Fig. 10a and paragraph 114);
the array substrate further comprises a second TFT (100) disposed on the non-display area (Fig. 10a and paragraph 114).
It would have been obvious to one of ordinary skill, in the art at the time, to modify Peng with the teachings of Shi to have a display area and a non-display area where the first TFT is disposed on the display area and the second TFT disposed on the non-display area since this layout allows for a designated area for testing the TFT’s of the device which allows for increased device reliability as taught by Shi (paragraphs 4 and 39-40).
In regard to claim 9, Peng teaches wherein the second active layer and the second gate are correspondingly disposed (corresponding deposition of active layer 30B and gate electrode 50B shown in Peng Fig. 1); material of the second active layer comprises low-temperature polycrystalline silicon (LTPS) (the active layer 30B of the second TFT 300 is formed of a low temperature polysilicon material as taught in Peng, paragraph 40).
In regard to claim 10, Peng teaches the array substrate further comprising: a substrate (100), a buffer layer (600) disposed on the substrate (Peng Fig. 2 and paragraph 51), and a gate insulating layer (40B) disposed between the second active layer (30B) and the second gate (50B) (second gate insulating layer 40B shown is shown between the active layer 30B and gate electrode 50B in Peng Fig. 2) (Peng Fig. 2 and paragraph 48); the second active layer disposed on the buffer layer corresponds to the second gate (30B shown disposed on buffer layer 600 and corresponding to gate electrode 50B in Peng Fig. 2); the first source is disposed on the gate insulating layer (first electrode 10A is shown on gate insulating layer 40B in Peng Fig. 2).
In regard to claim 18, Peng teaches the display panel wherein a second TFT (300) comprises a second active layer (30B) (Fig. 1 and paragraph 34), a second gate (50B) (Fig. 1 and paragraph 41), a second source (10B), and a second drain (20B) (Fig. 1 and paragraph 34);
the second gate and the first source are disposed in the same layer (both first electrode 10A and gate electrode 50B are in the layer disposed on 40B as shown in Fig. 1); the second source, the second drain, and the first drain are disposed in the same layer (second electrode 20A, first electrode 10B and a second electrode 20B all are disposed in the layer above 60B as shown in Fig. 1).
However, Peng in view of Qu doesn’t explicitly teach the array substrate, further comprising a display area and a non-display area; the first TFT is disposed on the display area; the array substrate further comprises a second TFT disposed on the non-display area.
Shi teaches a display panel (120), further comprising a display area (20) and a non-display area (10) (Fig. 10a and paragraph 113); the first TFT (200) is disposed on the display area (Fig. 10a and paragraph 114);
the array substrate further comprises a second TFT (100) disposed on the non-display area (Fig. 10a and paragraph 114).
It would have been obvious to one of ordinary skill, in the art at the time, to modify Peng with the teachings of Shi to have a display area and a non-display area where the first TFT is disposed on the display area and the second TFT disposed on the non-display area since this layout allows for a designated area for testing the TFT’s of the device which allows for increased device reliability as taught by Shi (paragraphs 4 and 39-40).
In regard to claim 19, Peng teaches wherein the second active layer and the second gate are correspondingly disposed (corresponding deposition of active layer 30B and gate electrode 50B shown in Peng Fig. 1); material of the second active layer comprises low-temperature polycrystalline silicon (LTPS) (the active layer 30B of the second TFT 300 is formed of a low temperature polysilicon material as taught in Peng paragraph 40).
In regard to claim 20, Peng teaches the array substrate further comprising: a substrate (100), a buffer layer (600) disposed on the substrate (Peng Fig. 2 and paragraph 51), and a gate insulating layer (40B) disposed between the second active layer (30B) and the second gate (50B) (second gate insulating layer 40B shown is shown between the active layer 30B and gate electrode 50B in Peng Fig. 2) (Peng Fig. 2 and paragraph 48); the second active layer disposed on the buffer layer corresponds to the second gate (30B shown disposed on buffer layer 600 and corresponding to gate electrode 50B in Peng Fig. 2); the first source is disposed on the gate insulating layer (first electrode 10A is shown on gate insulating layer 40B in Peng Fig. 2).
Allowable Subject Matter
Claims 3-4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
In regard to claim 3, Peng is considered a close prior art of reference. However, Peng fails to teach wherein the other part of the first active layer that is covered by the first drain is not disposed in the hole. Peng does not teach the first active layer that is covered by the first drain is not disposed in the hole. Peng does not teach the first active layer is covered by the drain.
Qu is considered a close prior art of reference. However, Qu fails to teach wherein the other part of the first active layer that is covered by the first drain is not disposed in the hole. Qu teaches the first active layer is covered by the first drain in a hole.
Claim 4 is objected to as being dependent on claim 3.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEYON ALI-SIMAH PUNCHBEDDELL whose telephone number is (571)270-0078. The examiner can normally be reached Mon-Thur: 7:30AM-3:30 PM.
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/SEYON ALI-SIMAH PUNCHBEDDELL/ Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893