DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/26/2026 has been entered.
Accordingly, claims 1, 4-13, 16-19 and 32 are pending in this application. Claims 1, 4-6, 8-9, 17-18 and 32 are currently amended; claims 7, 10-13, 16 and 19 are previously presented; claims 2-3, 14-15, 20-31 and 33-59 are canceled.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). See the rejection under 35 U.S.C. 112 below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 4-13, 16-19 and 32 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “wherein the data type of the first data is converted, concatenated, and split” in line 22. A data is normally what is being concatenated and split rather than a data type of the data. Therefore, it is unclear how it is possible to concatenate and/or split a data type. For purposes of examination, this is interpreted as wherein the first type data is converted, concatenated, and split. Claim 32 recites a similar limitation and is rejected for the same reason. Claims 4-13, 16-19 inherit the same deficiency as claim 1 by reason of dependence.
Furthermore, this limitation causes confusion as to how these three specific steps are performed. It is unclear whether the first type is data is first converted then concatenated then split or whether the first type is data is first concatenated then split then converted and so on and how these steps interrelate with the other steps/functional limitations of the claims. Further clarification is required. Claims 4-13, 16-19 inherit the same deficiency as claim 1 by reason of dependence.
Claim 1 recites “wherein the intermediate result is related to all types of the second type of data” in lines 34-35. There is insufficient antecedent basis for the underlined limitation in the claim. For purposes of examination, this is interpreted as the second data type. Claims 4-13, 16-19 inherit the same deficiency as claim 1 by reason of dependence.
Furthermore, the second data type in line 28 is recited in singular form. Therefore, it is unclear what the term all types are supposed to be referring to since the claim only recites one type of second data type. Therefore, there is also insufficient antecedent basis for this limitation in the claim. Further clarification is required. Claims 4-13, 16-19 inherit the same deficiency as claim 1 by reason of dependence.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 4-13, 16-19 and 32 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites “wherein the data type of the first data is converted, concatenated, and split” in line 22. This limitation lacks written description support because the specification fails to disclose converting, concatenating and splitting the data type of the first data, i.e., the claim is inconsistent with the specification. Paragraph [0035] discloses that “the first type data … may be first type data that is converted, concatenated, and split”, however, the first type data is not the same as the data type of first type data. Claim 32 recites a similar limitation and is rejected for the same reason. Claims 4-13, 16-19 inherit the same deficiency as claim 1 by reason of dependence.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 4-13, 16-19 and 32 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Under Step 1, claims 1, 4-13 and 16-19 recite a converter and, therefore, is a machine. Claim 32 recite a series of steps and, therefore, is a process.
Under Step 2A prong 1, claim 1 recites
A processor-implemented converter, of an artificial intelligence (AI) chip, for data type conversion, comprising processing circuitry, the processor-implemented converter comprising:
a first conversion stage (L1) comprising first circuitry configured to:
receive first type data and descriptive information about each of the first type data and second type data;
generate a transition sign bit (Tsign), a transition data bit (Tdata), and a transition exponent bit (Tshift) according to the first type data and the descriptive information; and
calculate an intermediate data bit (ABS) according to the transition data bit (Tdata);
calculate an intermediate exponent bit (EXP) according to the transition exponent bit (Tshift);
calculate an intermediate sign bit (SIGN) according to the transition sign bit (Tsign)
generate an intermediate result according to the transition sign bit (Tsign), the transition data bit (Tdata), and the transition exponent bit (Tshift),
wherein the intermediate result comprises the intermediate sign bit (SIGN), the intermediate exponent bit (EXP), and the intermediate data bit (ABS), and
wherein the descriptive information comprises:
first descriptive information configured to describe a data type of the first type data and a first exponent bit of the first type data, wherein the data type of the first data is converted, concatenated, and split;
second descriptive information configured to describe a data type of the second type data and a second exponent bit of the second type data, wherein the transition exponent bit (Tshift) is equal to a difference between the first exponent bit and the second exponent bit;
a first data type of the first type data;
a second data type of the second type data; and
a difference exponent bit configured to indicate the difference between the first exponent bit of the first type data and the second exponent bit of the second type data,
wherein the transition exponent bit (Tshift) is equal to the difference exponent bit; and
a second conversion stage (L2) comprising second circuitry configured to convert the intermediate result into the second type data, wherein the intermediate result is related to all types of the second type of data.
The above underlined limitations of converting a first data type format to an intermediate format, then converting the intermediate format to a second data type format using descriptive information specifying the data type and the exponent bits of the first and second data type amounts to processing mathematical relationships/calculations and falls within the “Mathematical Concepts” and “Mental Processes” grouping of abstract ideas. The steps of “generate”, “calculate”, “calculate”, “calculate”, “generate”, and “convert” is a process that under its broadest reasonable interpretation, covers performance of the limitation in the mind. That is, other than reciting “first circuitry” and “second circuitry”, nothing in the claim element precludes the steps from practically being performed in the human mind. For example, but for the “first circuitry” and “second circuitry” language, the claim encompasses manually converting a 32-bit floating point (FP) number into an intermediate format by extracting various bits of the different data field of the 32-bit floating point number and using the various bits of the different data field (sign, exponent, and mantissa) to generate/calculate an intermediate result that is also in a FP format which includes a sign, exponent, and mantissa, and converting the intermediate result to an 8-bit FP number using pen and paper. Accordingly, the claim is directed to recite an abstract idea.
Under step 2A prong 2, the claim recites the following additional elements: processing circuitry, first circuitry, receive first type data and descriptive information about each of the first type data and second type data, and second circuitry. However, the additional elements of “processing circuitry”, “first circuitry” and “second circuitry” are recited at a high-level of generality (i.e., as a generic circuitry for performing a series of mathematical operations) such that they amount to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or merely as instructions using a generic computer component or merely as tools to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f) for more information. The additional element of “receive first type data and descriptive information about each of the first type data and second type data” is merely an adding insignificant extra-solution activity, i.e. mere data gathering. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under step 2B, claim 1 does not include additional elements that, individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “processing circuitry”, “first circuitry” and “second circuitry” are recited at a high-level of generality (i.e., as a generic circuitry for performing a series of mathematical operations) such that they amount to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or merely as instructions using a generic computer component or merely as tools to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f) for more information. The additional element of “receive first type data and descriptive information about each of the first type data and second type data” is merely an adding insignificant extra-solution activity, i.e. mere data gathering. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Receiving or transmitting data over a network” and “Storing and retrieving information in memory” as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under step 2A prong 1, claims 4-13 and 16-19 recite the same abstract idea as claim 1 by reason of dependence. Further, claim 4 recites further details of the intermediate result and further abstract idea of “wherein the intermediate result further comprises an intermediate rounding bit (STK) and to calculate the intermediate rounding bit (STK) according to the intermediate data bit (ABS) and the intermediate sign bit (SIGN)”; claim 5 recites further details of the intermediate result and further abstract idea of “wherein the intermediate result further comprises an intermediate rounding bit (STK), and calculate the intermediate rounding bit (STK) according to the intermediate data bit (ABS), the intermediate exponent bit (EXP), and the intermediate sign bit (SIGN)”; claim 6 recites further abstract idea of “judge whether the transition data bit (Tdata) is less than 0, and calculate a complement of the transition data bit (Tdata) and take the complement of the transition data bit (Tdata) as the intermediate data bit (ABS) if the transition data bit (Tdata) is less than 0, otherwise, take the transition data bit (Tdata) as the intermediate data bit (ABS)”; claim 7 recites further abstract idea of “judge whether a data type of the transition data bit (Tdata) is a first type or a second type, select or processing, if the data type of the transition data bit (Tdata) is the first type, select for processing, if the data type of the transition data bit (Tdata) is the second type, and normalize the transition data bit (Tdata) and take the normalized transition data bit as the intermediate data bit (ABS) if the data type of the transition data bit (Tdata) is the second type”; claim 8 recites further abstract idea of “wherein the intermediate exponent bit (EXP) is equal to the transition exponent bit (Tshift)”; claim 9 recites further abstract idea of “wherein the intermediate sign bit (SIGN) is calculated”; claim 10 recites further abstract idea of “determine a number of the first type data received and concatenate the first type data to form first concatenation data, and convert the first concatenation data into the intermediate result according to the descriptive information”; claim 11 recites further details of determining the number of first type data received “wherein the number of the first type data received is determined by: a preset first fixed value, or a specific value that is obtained by dividing: a number of bits of data with a highest number of bits in the first type data and the second type data by a number of processing bits”; claim 12 recites further abstract idea of “determine a number of to-be-split first type data received and split the first type data into split data with a number same as the determined number of the to-be-split first type data received, and convert the split data into the intermediate result according to the descriptive information”; claim 13 recites further details of determining the number of to-be-split first type data received “wherein the number of the to-be-split first type data received is determined by: a preset second fixed value, or specific value that is obtained by dividing: a number of processing bits of the converter by a number of bits of data with a highest number of bits in the first type data and the second type data; claim 16 recites further details of the descriptive information “herein the descriptive information further comprises a rounding type, wherein the rounding type comprises at least one of: a TOZERO, an OFFZERO, an UP, a DOWN, a ROUNDINGOFFZERO, a ROUNDINGTOEVEN, and a random rounding”; claim 17 recites further abstract idea of “calculate an intermediate rounding bit (STK) according to the intermediate data bit (ABS) and the intermediate sign bit (SIGN)”; claim 18 recites further abstract idea of “calculate an intermediate rounding bit (STK) according to the intermediate data bit (ABS), the intermediate exponent bit (EXP), and the intermediate sign bit (SIGN)”; and claim 19 recites further abstract idea of “generate the second type data according to the intermediate data bit (ABS), the intermediate sign bit (SIGN), the intermediate exponent bit (EXP), and the intermediate rounding bit (STK), and wherein the intermediate rounding bit (STK) is calculated” and falls within the “Mathematical Concepts” and/or “Mental Processes” grouping of abstract ideas. In particular claims 4-5, 8, 10-13 and 16-18 do not include additional elements that would require further analysis under step 2A prong 2 and step 2B. Accordingly, the claims are directed to recite an abstract idea.
Under step 2A prong 2, claim 6 recites the following additional elements: a second selector and a first complement calculator. Claim 7 recites the following additional elements: a first selector and a first normalizer. Claim 9 recites the following additional elements: a straight connection line. Claim 19 recites the following additional elements: an AND-OR logic. However, the additional elements of “a second selector” and “a first complement calculator” in claim 6; “a first selector” and “a first normalizer” in claim 7; “straight connection line” in claim 9; and “an AND-OR logic” in claim 19 are recited at a high-level of generality (i.e., as a generic selector for selecting where to route data; as a generic complementor for complementing; as a generic normalizer for normalizing; as a generic data wire for routing data; and as a generic AND-OR logic without reciting any specific structural configuration to achieve the claimed functions) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea or merely reciting the words “apply it” (or an equivalent) with the judicial exception. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under step 2B, claims 6-7, 9 and 19 do not include additional elements that, individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a second selector” and “a first complement calculator” in claim 6; “a first selector” and “a first normalizer” in claim 7; “straight connection line” in claim 9; and “an AND-OR logic” in claim 19 are recited at a high-level of generality (i.e., as a generic selector for selecting where to route data; as a generic complementor for complementing; as a generic normalizer for normalizing; as a generic data wire for routing data; and as a generic AND-OR logic without reciting any specific structural configuration to achieve the claimed functions) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea or merely reciting the words “apply it” (or an equivalent) with the judicial exception. The claims do not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claims do not amount to significantly more than the abstract idea.
Regarding claim 32, it is directed to a method practiced by the converter of claim 1. All steps performed by the method of claim 32 would be practiced by the converter of claim 1. Claim 1 analysis applies equally to claim 32. In addition, the additional limitations included in claim 32 will be discussed below.
Under step 2A prong 2, claim 32 recites the following additional elements: a processor-implemented converter of an artificial intelligence (AI) chip. However, the additional elements of “a processor-implemented converter of an artificial intelligence (AI) chip” are recited at a high-level of generality (i.e., as a generic converter in a generic AI chip for performing a series of mathematical operations without reciting any specific configuration with circuit structure of the converter) such that they amount to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or merely as instructions using a generic computer component or merely as tools to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f) for more information. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under step 2B, claim 32 does not include additional elements that, individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of the additional elements of “a processor-implemented converter of an artificial intelligence (AI) chip” are recited at a high-level of generality (i.e., as a generic converter in a generic AI chip for performing a series of mathematical operations without reciting any specific configuration with circuit structure of the converter) such that they amount to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or merely as instructions using a generic computer component or merely as tools to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f) for more information. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Allowable Subject Matter
Claims 1, 4-13, 16-19 and 32 would be allowable if rewritten to overcome the 35 U.S.C. 101 rejection discussed above.
The following is a statement of reasons for the indication of allowable subject matter:
The reasons for indication of allowable subject matter are the same reasons provided for the indication of allowable subject matter in the non-final office action submitted on 05/07/2025.
Response to Arguments
Applicant's arguments filed on 04/28/2026, see remarks page 10-22, with respect to the 35 U.S.C. 101 rejection of claims 1, 4-13, 16-19 and 32 have been fully considered but they are not persuasive.
Applicant argues the following:
1.) under step 2A prong One, the claims do not recite a mathematical concept because the claims do not recite any mathematical formulas, equations, or abstract mathematical relationships. Further, the claims do not recite any equation, summation, squaring, reciprocal operation, or mathematical formula. Further, the claims do not recite a mental process because the human mind is not equipped to “calculate an intermediate data bit (ABS) according to the transition data bit (Tdata); calculate an intermediate exponent bit (EXP) according to the transition exponent bit (Tshift); calculate an intermediate sign bit (SIGN) according to the transition sign bit (Tsign); generate an intermediate result according to the transition sign bit (Tsign), the transition data bit (Tdata), and the transition exponent bit (Tshift), wherein the intermediate result comprises at least an the intermediate sign bit (SIGN), the intermediate exponent bit (EXP), and the intermediate data bit (ABS), and wherein the descriptive information comprises: first descriptive information configured to describe a data type of the first type data and a first exponent bit of the first type data, wherein the data type of the first data is converted, concatenated, and split” as recited in claim 1.
Response: Examiner respectfully disagrees. The claims recite mathematical relationships expressed in words and mathematical calculations. Accordingly, the claims recite mathematical concepts. Furthermore, the claims also recite mental steps that can practically be performed in the human mind.
2.) under step 2A prong 2, the claims provide an improvement by reducing repeated calculation logic and reducing memory access delay and overheads during operation of artificial intelligence chip as disclosed in paragraphs [0003-0007, 0014, 0036- 0037, 0046, 0056 and 0196-0198] by having two conversion stages and using an intermediate result that has a common structure to convert the input data to other types of data. As long as an intermediate result that may represent any data type is obtained, flexible processing may be performed on the intermediate result, and it is not necessarily required to employ specific circuits and structures described in the present disclosure. Further, the concatenation and splitting operation enables parallel processing and improved resource utilization which increases throughput and efficiency.
Response: Examiner respectfully disagrees. The alleged improvements being argued by Applicant is a direct result of the math as admitted by Applicant, i.e., by first converting the first type data into the intermediate result which produces the technical effect of reducing repeated calculation logic and reducing memory access delay and overheads and portability and then converting the intermediate result into the second type data and not by any additional elements or combination of additional elements. Applicant’s admission that “As long as an intermediate result that may represent any data type is obtained, flexible processing may be performed on the intermediate result, and it is not necessarily required to employ specific circuits and structures described in the present disclosure” further provides evidence that the abstract idea itself provides the alleged improvements. See also paragraphs [0036-0037] which discloses in part “when the type of data is converted, the data may be converted into the intermediate result … The beneficial effects brought by converting the first type data into the intermediate result and then converting the intermediate result into the second type data …”. See MPEP 2106.05(a): “It is important to note, the judicial exception alone cannot provide the improvement.” See also MPEP 2106.05 I: “An inventive concept "cannot be furnished by the unpatentable law of nature (or natural phenomenon or abstract idea) itself.” Furthermore, the features of “wherein the data type of the first data is converted, concatenated, and split” is also part of the abstract idea. There is no requirement that the concatenated and split data are being processed in parallel.
3.) under step 2B, the features of “a second conversion stage (L2) comprising second circuitry configured to convert the intermediate result into the second type data, wherein the intermediate result is related to all types of the second type of data” improves the efficiency of a conventional artificial intelligence chip by reducing stacking of conversion number instructions which further reduces a large amount of logic redundancy in a conversion number unit.
Response: As discussed above, the features of “wherein the intermediate result is related to all types of the second type of data” is part of the abstract idea, i.e., there is a mathematical relationship between the intermediate result and the second type data to make it possible to convert the intermediate result into the second type data. The feature of “second circuitry” is recited at a high-level of generality (i.e., as a generic circuitry for converting the intermediate result into the second type data without reciting any specific structural configuration of the second circuitry to achieve the claimed function) such that it amounts to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or merely as tools to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f) for more information.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlo Waje whose telephone number is (571)272-5767. The examiner can normally be reached 9:00-6:00 M-F.
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/Carlo Waje/Examiner, Art Unit 2182 (571)272-5767
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