DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Accordingly, claims 1, 3-13, 16-19 and 32 are pending in this application. Claims 1, 3, 6, 10-13, 16-19 and 32 are currently amended; claims 4-5 and 7-9 are previously presented; claims 2, 14-15, 20-31 and 33-59 are canceled.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 3-13, 16-19 and 32 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Under Step 1, claims 1, 3-13 and 16-19 recite a converter and, therefore, is a machine. Claim 32 recite a series of steps and, therefore, is a process.
Under Step 2A prong 1, claim 1 recites
A processor-implemented converter, of an artificial intelligence (AI) chip, for data type conversion, comprising processing circuitry, the processor-implemented converter comprising:
a first conversion stage (L1) comprising first circuitry configured to:
receive first type data and descriptive information about each of the first type data and second type data;
generate a transition sign bit (Tsign), a transition data bit (Tdata), and a transition exponent bit (Tshift) according to the first type data and the descriptive information; and
generate an intermediate result according to the transition sign bit (Tsign), the transition data bit (Tdata), and the transition exponent bit (Tshift),
wherein the intermediate result comprises at least an intermediate sign bit (SIGN), an intermediate exponent bit (EXP), and an intermediate data bit (ABS), and
wherein the descriptive information comprises:
first descriptive information configured to describe a data type of the first type data and a first exponent bit of the first type data;
second descriptive information configured to describe a data type of the second type data and a second exponent bit of the second type data, wherein the transition exponent bit (Tshift) is equal to a difference between the first exponent bit and the second exponent bit;
a first data type of the first type data;
a second data type of the second type data; and
a difference exponent bit configured to indicate the difference between the first exponent bit of the first type data and the second exponent bit of the second type data,
wherein the transition exponent bit (Tshift) is equal to the difference exponent bit; and
a second conversion stage (L2) comprising second circuitry configured to convert the intermediate result into the second type data.
The above underlined limitations of converting a first data type format to an intermediate format, then converting the intermediate format to a second data type format using descriptive information specifying the data type and the exponent bits of the first and second data type amounts to processing mathematical relationships/calculations and falls within the “Mathematical Concepts” and “Mental Processes” grouping of abstract ideas. The steps of “generate”, “generate” , and “convert” is a process that under its broadest reasonable interpretation, covers performance of the limitation in the mind. That is, other than reciting “first circuitry” and “second circuitry”, nothing in the claim element precludes the steps from practically being performed in the human mind. For example, but for the “first circuitry” and “second circuitry” language, the claim encompasses manually converting a 32-bit floating point (FP) number into an intermediate format by extracting various bits of the different data field of the 32-bit floating point number and using the various bits of the different data field (sign, exponent, and mantissa) to generate an intermediate result that is also in a FP format which includes a sign, exponent, and mantissa, and converting the intermediate result to an 8-bit FP number using pen and paper. Accordingly, the claim is directed to recite an abstract idea.
Under step 2A prong 2, the claim recites the following additional elements: processing circuitry, first circuitry, receive first type data and descriptive information about each of the first type data and second type data, and second circuitry. However, the additional elements of “processing circuitry”, “first circuitry” and “second circuitry” are recited at a high-level of generality (i.e., as a generic circuitry for performing a series of mathematical operations) such that they amount to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or merely as instructions using a generic computer component or merely as tools to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f) for more information. The additional element of “receive first type data and descriptive information about each of the first type data and second type data” is merely an adding insignificant extra-solution activity, i.e. mere data gathering. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under step 2B, claim 1 does not include additional elements that, individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “processing circuitry”, “first circuitry” and “second circuitry” are recited at a high-level of generality (i.e., as a generic circuitry for performing a series of mathematical operations) such that they amount to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or merely as instructions using a generic computer component or merely as tools to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f) for more information. The additional element of “receive first type data and descriptive information about each of the first type data and second type data” is merely an adding insignificant extra-solution activity, i.e. mere data gathering. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Receiving or transmitting data over a network” and “Storing and retrieving information in memory” as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under step 2A prong 1, claims 3-13 and 16-19 recite the same abstract idea as claim 1 by reason of dependence. Further, claim 3 recites further details of the intermediate result and further abstract idea of “calculate the intermediate data bit (ABS) according to the transition data bit (Tdata), calculate the intermediate exponent bit (EXP) according to the transition exponent bit (Tshift), and calculate the intermediate sign bit (SIGN) according to the transition sign bit (Tsign)”; claim 4 recites further details of the intermediate result and further abstract idea of “wherein the intermediate result further comprises an intermediate rounding bit (STK) and to calculate the intermediate rounding bit (STK) according to the intermediate data bit (ABS) and the intermediate sign bit (SIGN)”; claim 5 recites further details of the intermediate result and further abstract idea of “wherein the intermediate result further comprises an intermediate rounding bit (STK), and calculate the intermediate rounding bit (STK) according to the intermediate data bit (ABS), the intermediate exponent bit (EXP), and the intermediate sign bit (SIGN)”; claim 6 recites further abstract idea of “judge whether the transition data bit (Tdata) is less than 0, and calculate a complement of the transition data bit (Tdata) and take the complement of the transition data bit (Tdata) as the intermediate data bit (ABS) if the transition data bit (Tdata) is less than 0, otherwise, take the transition data bit (Tdata) as the intermediate data bit (ABS)”; claim 7 recites further abstract idea of “judge whether a data type of the transition data bit (Tdata) is a first type or a second type, select or processing, if the data type of the transition data bit (Tdata) is the first type, select for processing, if the data type of the transition data bit (Tdata) is the second type, and normalize the transition data bit (Tdata) and take the normalized transition data bit as the intermediate data bit (ABS) if the data type of the transition data bit (Tdata) is the second type”; claim 8 recites further abstract idea of “wherein the intermediate exponent bit (EXP) is equal to the transition exponent bit (Tshift)”; claim 9 recites further abstract idea of “wherein the intermediate sign bit (SIGN) is calculated”; claim 10 recites further abstract idea of “determine a number of the first type data received and concatenate the first type data to form first concatenation data, and convert the first concatenation data into the intermediate result according to the descriptive information”; claim 11 recites further details of determining the number of first type data received “wherein the number of the first type data received is determined by: a preset first fixed value, or a specific value that is obtained by dividing: a number of bits of data with a highest number of bits in the first type data and the second type data by a number of processing bits”; claim 12 recites further abstract idea of “determine a number of to-be-split first type data received and split the first type data into split data with a number same as the determined number of the to-be-split first type data received, and convert the split data into the intermediate result according to the descriptive information”; claim 13 recites further details of determining the number of to-be-split first type data received “wherein the number of the to-be-split first type data received is determined by: a preset second fixed value, or specific value that is obtained by dividing: a number of processing bits of the converter by a number of bits of data with a highest number of bits in the first type data and the second type data; claim 16 recites further details of the descriptive information “herein the descriptive information further comprises a rounding type, wherein the rounding type comprises at least one of: a TOZERO, an OFFZERO, an UP, a DOWN, a ROUNDINGOFFZERO, a ROUNDINGTOEVEN, and a random rounding”; claim 17 recites further abstract idea of “calculate an intermediate rounding bit (STK) according to the intermediate data bit (ABS) and the intermediate sign bit (SIGN)”; claim 18 recites further abstract idea of “calculate an intermediate rounding bit (STK) according to the intermediate data bit (ABS), the intermediate exponent bit (EXP), and the intermediate sign bit (SIGN)”; and claim 19 recites further abstract idea of “generate the second type data according to the intermediate data bit (ABS), the intermediate sign bit (SIGN), the intermediate exponent bit (EXP), and the intermediate rounding bit (STK), and wherein the intermediate rounding bit (STK) is calculated” and falls within the “Mathematical Concepts” and/or “Mental Processes” grouping of abstract ideas. In particular claims 3-5, 8, 10-13 and 16-18 do not include additional elements that would require further analysis under step 2A prong 2 and step 2B. Accordingly, the claims are directed to recite an abstract idea.
Under step 2A prong 2, claim 6 recites the following additional elements: a second selector and a first complement calculator. Claim 7 recites the following additional elements: a first selector and a first normalizer. Claim 9 recites the following additional elements: a straight connection line. Claim 19 recites the following additional elements: an AND-OR logic. However, the additional elements of “a second selector” and “a first complement calculator” in claim 6; “a first selector” and “a first normalizer” in claim 7; “straight connection line” in claim 9; and “an AND-OR logic” in claim 19 are recited at a high-level of generality (i.e., as a generic selector for selecting where to route data; as a generic complementor for complementing; as a generic normalizer for normalizing; as a generic data wire for routing data; and as a generic AND-OR logic without reciting any specific structural configuration to achieve the claimed functions) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea or merely reciting the words “apply it” (or an equivalent) with the judicial exception. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under step 2B, claims 6-7, 9 and 19 do not include additional elements that, individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a second selector” and “a first complement calculator” in claim 6; “a first selector” and “a first normalizer” in claim 7; “straight connection line” in claim 9; and “an AND-OR logic” in claim 19 are recited at a high-level of generality (i.e., as a generic selector for selecting where to route data; as a generic complementor for complementing; as a generic normalizer for normalizing; as a generic data wire for routing data; and as a generic AND-OR logic without reciting any specific structural configuration to achieve the claimed functions) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea or merely reciting the words “apply it” (or an equivalent) with the judicial exception. The claims do not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claims do not amount to significantly more than the abstract idea.
Regarding claim 32, it is directed to a method practiced by the converter of claim 1. All steps performed by the method of claim 32 would be practiced by the converter of claim 1. Claim 1 analysis applies equally to claim 32. In addition, the additional limitations included in claim 32 will be discussed below.
Under step 2A prong 2, claim 32 recites the following additional elements: a processor-implemented converter of an artificial intelligence (AI) chip. However, the additional elements of “a processor-implemented converter of an artificial intelligence (AI) chip” are recited at a high-level of generality (i.e., as a generic converter in a generic AI chip for performing a series of mathematical operations without reciting any specific configuration with circuit structure of the converter) such that they amount to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or merely as instructions using a generic computer component or merely as tools to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f) for more information. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under step 2B, claim 32 does not include additional elements that, individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of the additional elements of “a processor-implemented converter of an artificial intelligence (AI) chip” are recited at a high-level of generality (i.e., as a generic converter in a generic AI chip for performing a series of mathematical operations without reciting any specific configuration with circuit structure of the converter) such that they amount to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or merely as instructions using a generic computer component or merely as tools to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f) for more information. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Allowable Subject Matter
Claims 1, 3-13, 16-19 and 32 would be allowable if rewritten to overcome the 35 U.S.C. 101 rejection discussed above.
The following is a statement of reasons for the indication of allowable subject matter:
The reasons for indication of allowable subject matter are the same reasons provided for the indication of allowable subject matter in the non-final office action submitted on 05/07/2025.
Response to Arguments
In view of amendments made, the objection to claims has been withdrawn.
In view of amendments made, the 35 U.S.C. 112(b) rejection of the claims has been withdrawn.
In view of amendments made, the 35 U.S.C. 101 rejection of claims 1, 10-13 and 16 with respect to being directed to a non-statutory subject matter has been withdrawn.
Applicant's arguments filed on 01/06/2026, see remarks page 11-20, with respect to the 35 U.S.C. 101 rejection of claims 1, 3-13, 16-19 and 32 have been fully considered but they are not persuasive.
Applicant argues the following:
1.) under step 2A prong One, the claims do not recite a mental process because the converter is “processor-implemented” as recited in amended claim 1. The conversion of electronic data into an intermediate result and then converting the intermediate result is beyond the purview of human mind. The claimed conversion operations are constrained upon the descriptive information about each of the first type data and second type data. Further, amended claim 1 recites staged operations and “processing circuitry” and “first circuitry” to perform the signal generation and conversion operations which cannot practically or conceptually be performed in the human mind.
Response: Examiner respectfully disagrees. See MPEP 2106.04(a)(2) III.C: “Claims can recite a mental process even if they are claimed as being performed on a computer. The Supreme Court recognized this in Benson, determining that a mathematical algorithm for converting binary coded decimal to pure binary within a computer’s shift register was an abstract idea.” Furthermore, the “processor-implemented” is recited in the preamble, and the preamble is not given patentable weight because it does not limit the scope of the claim. Further, the two stages are not recited as circuit stages can be reasonably interpreted as conversion steps that can be performed manually using pen and paper. The mere nominal recitation of “processing circuitry”, “first circuitry” and “second circuitry” does not take the claims from the mental processes grouping of abstract idea.
2.) under step 2A prong One, amended independent claim 1 does not recite a mathematical concept. While the claim involves calculations such as determining a difference between exponent bits, this determination is not claimed as a mathematical result, but as a hardware control parameter (the transition exponent bit) used by circuitry to align, normalize, and convert data representations directed to a practical technological solution for processor-based data type conversion.
Response: Examiner respectfully disagrees. Converting from one data type to another data type recites a mathematical concept. See MPEP 2106.04(a)(2) I.A where “ii. a conversion between binary coded decimal and pure binary” is considered to recite a mathematical concept. Further, Applicant is arguing unclaimed features. The claims do not recite how the transition exponent bit is used to control specific sub-components of the first circuitry to control alignment, normalization, and conversion of the input data. The claim merely recites generating output signals using input signals with no recitation of specific circuit structure and configuration of the first circuitry to generate the intermediate result.
3.) under step 2A prong 2, amended claim 1 provides an improvement to overcome the limitations disclosed in paragraphs [0003-0005, 0037 and 0196-0198] by having two conversion stages which reduces chip area, power consumption, and design complexity compared with traditional MxN conversion circuits. The main purpose of the intermediate result of the present disclosure is to reduce repeated calculation logic and compared with the software implementations, reduce memory access delay and overheads, and simultaneously have better scalability and portability.
Response: Examiner respectfully disagrees. The alleged improvements being argued by Applicant is a direct result of the math as admitted by Applicant, i.e., by converting the first type data into the intermediate result which produces the technical effect of reducing repeated calculation logic, reducing memory access delay and overheads, and simultaneously improving scalability and portability and then converting the intermediate result into the second type data and not by any additional elements or combination of additional elements. See also paragraphs [0036-0037] which discloses in part “when the type of data is converted, the data may be converted into the intermediate result … The beneficial effects brought by converting the first type data into the intermediate result and then converting the intermediate result into the second type data …”. See MPEP 2106.05(a): “It is important to note, the judicial exception alone cannot provide the improvement.” See also MPEP 2106.05 I: “An inventive concept "cannot be furnished by the unpatentable law of nature (or natural phenomenon or abstract idea) itself.”
4.) under step 2B, generating transition bits using circuitry, producing a structured intermediate representation, and performing staged conversion using processing circuitry, constitutes an inventive concept that is neither routine nor conventional.
Response: As discussed above, the features of generating transition bits, producing an intermediate representation, and performing staged conversion are part of the abstract idea. The features of “processing circuitry”, “first circuitry” and “second circuitry” are recited at a high-level of generality (i.e., as a generic circuitry for performing a series of mathematical operations without reciting any specific structural circuit configuration of the first and second circuitry) such that they amount to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or merely as tools to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f) for more information.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlo Waje whose telephone number is (571)272-5767. The examiner can normally be reached 9:00-6:00 M-F.
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/Carlo Waje/Examiner, Art Unit 2182 (571)272-5767