DETAILED ACTION 1. Claims 1-8, 10-12, 16-17, 24, 25, 28-30, and 33 are pending in the application. Notice of Pre-AIA or AIA Status 2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. 4. Claim(s) 1, 10, 16-17, 24, 25, 28-30, and 33 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Danysh et al (hereafter Danysh )( US Pub. 2019 / 0196785 ) Danysh was cited in the IDS filed 02/20/2022 5. As to claims 1 and 33, Danysh discloses a method for performing a floating-point number multiplication computation by using a multiplier (abstract) , wherein a mantissa processing unit of the multiplier is used to obtain a mantissa after the multiplication computation according to a mantissa of a floating-point number [0040] generating mantissa) , and the mantissa processing unit includes a control circuit, which is configured to call the mantissa processing unit multiple times when a mantissa bit width of at least one of two floating- point numbers is larger than a data bit width that is processable at one time by the mantissa processing unit ([0015]-[0019], larger bit width) . 6. As to claim 10, Danysh discloses wherein the multiplier also includes an exponent processing unit, which is configured to obtain an exponent after the multiplication computation according to exponents of the two floating-point numbers , wherein the exponent processing unit includes a second control circuit, which is configured to determine calling the exponent processing unit multiple times to obtain the exponent after the multiplication computation according to an exponent bit width of one of the two floating-point numbers and one of two bit widths supported by the exponent processing unit, or according to exponent bit widths of the two floating-point numbers and the two bit widths supported by the exponent processing unit ([0015]-[0020] and [0054]). 7. As to claim 16, Danysh discloses wherein the mantissa processing unit includes a partial product computation unit and a partial product summation unit, wherein the partial product computation unit is configured to obtain an intermediate result according to mantissas of the two floating-point numbers, and the partial product summation unit is configured to perform a summation computation on intermediate results to obtain a summation result and take the summation result as the mantissa after the multiplication computation ([0039] intermediate result including sums partial products). 8. As to claim 17, Danysh discloses wherein the partial product computation unit includes a Booth encoding circuit, which is configured to perform Booth encoding processing on the mantissa of the first floating-point number or the mantissa of the second floating-point number to obtain the intermediate result ([0003]). 9. As to claim 24, Danysh discloses wherein the multiplier further includes: a normalization processing unit configured to perform normalization processing on at least one of the two floating-point numbers to obtain a corresponding exponent and a corresponding mantissa when at least one of the two floating-point numbers is a non-normalized and non-zero floating-point number ([0053] determining whether first operand is denormal). 10. As to claim 25, Danysh discloses wherein the multiplier is configured to perform a multiplication computation of the two floating-point numbers according to a computation mode, wherein the computation mode indicates data formats of the two floating-point numbers; the mantissa processing unit is configured to obtain the mantissa after the multiplication computation according to the computation mode and the mantissas of the two floating-point numbers; and the exponent processing unit is configured to obtain the exponent after the multiplication computation according to the computation mode and the exponents of the two floating-point numbers ([0015]-[0020]). 11. As to claim 28, Danysh discloses wherein the mantissa processing unit includes a bit number extending circuit, which is configured to extend a mantissa bit number of at least one of the first floating-point number and the second floating-point number ([0040]). 12. As to claim 29, Danysh discloses wherein the floating-point number further includes a sign, and the multiplier further includes: a sign processing unit configured to obtain a sign after the multiplication computation according to signs of the two floating-point numbers ([0040]-[0041]). 13. As to claim 30, Danysh discloses wherein the sign processing unit includes an exclusive-OR logical circuit, which is configured to perform an exclusive-OR computation according to the signs of the two floating-point numbers to obtain the sign after the multiplication computation ([0040]-[0041]). Allowable Subject Matter 14. Claims 2-8, 11, and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 15. The following is a statement of reasons for the indication of allowable subject matter: The claims recite at least wherein the two floating-point numbers include a first floating-point number and a second floating-point number, and the mantissa processing unit supports a first bit width and a second bit width, wherein a mantissa of the first floating-point number is set as a first input corresponding to the first bit width, a mantissa of the second floating- point number is set as a second input corresponding to the second bit width, a bit width of the first input is less than or equal to the first bit width, and the control circuit is configured to call the mantissa processing unit multiple times to obtain the mantissa after the multiplication computation when a bit width of the second input is larger than the second bit width ; and wherein the two floating-point numbers include a first floating-point number and a second floating-point number; the exponent processing unit supports a third bit width and a fourth bit width, wherein an exponent of the first floating-point number is set as a third input corresponding to the third bit width, an exponent of the second floating-point number is set as a fourth input corresponding to the fourth bit width, and a bit width of the third input is less than or equal to the third bit width; and the second control circuit is configured to call the exponent processing unit multiple times to obtain the exponent after the multiplication computation when a bit width of the fourth input is larger than the fourth bit width. The closest prior art of record US Pub. 2019 / 0196785 teaches a multiplier configured to perform a multiplication computation of a floating- point number, as in claims 1 and 33, however; the prior art of record does not teach or suggest at least wherein the two floating-point numbers include a first floating-point number and a second floating-point number, and the mantissa processing unit supports a first bit width and a second bit width, wherein a mantissa of the first floating-point number is set as a first input corresponding to the first bit width, a mantissa of the second floating- point number is set as a second input corresponding to the second bit width, a bit width of the first input is less than or equal to the first bit width, and the control circuit is configured to call the mantissa processing unit multiple times to obtain the mantissa after the multiplication computation when a bit width of the second input is larger than the second bit width ; and wherein the two floating-point numbers include a first floating-point number and a second floating-point number; the exponent processing unit supports a third bit width and a fourth bit width, wherein an exponent of the first floating-point number is set as a third input corresponding to the third bit width, an exponent of the second floating-point number is set as a fourth input corresponding to the fourth bit width, and a bit width of the third input is less than or equal to the third bit width; and the second control circuit is configured to call the exponent processing unit multiple times to obtain the exponent after the multiplication computation when a bit width of the fourth input is larger than the fourth bit width. Conclusion 16. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pat. 6 , 115 , 729 – related to a data processing system incorporating a floating point unit that provides a multiply-accumulate operation with a reduced circuit size. US Pub. 2007 / 0061391 – related to data processing systems and specifically to floating point units. US Pub. 2013 / 0282783 – related to s ystems and methods for digital computation, and more particularly to systems and methods for constructing a floating-point multiply-add unit in a system such as a digital signal processor or a hardware accelerator. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT MICHAEL D YAARY whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-1249 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Mon-Fri 9-5:30 . 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Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL D. YAARY/ Primary Examiner, Art Unit 2151