DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority The present application, 17620601 filed 09/30/2022 is a National Stage entry of PCT/CN2020/120717, international filing date: 10/13/2020; claims foreign priority to CN202011075144.5, filed 10/09/2020; claims foreign priority to CN201910970802.8, filed 10/14/2019. Information Disclosure Statement The information disclosure statement (IDS) submitted on 10/11/2023 , 12/12/2024 and 04/17/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner except for the reference that is lined-through because Applicant has not provided a legible copy of the foreign document i.e., an English translation was submitted but the actual foreign document was not submitted. Drawings The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters " 202 " and " 204 " have both been used to designate the “Mantissa processing unit” in Fig. 3. Examiner suggest amending the drawing s to relabel 202 as “ exponent processing unit” instead. The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 1000 . Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification Applicant is reminded of the proper content of an abstract of the disclosure. A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art. If the patent is of a basic nature, the entire technical disclosure may be new in the art, and the abstract should be directed to the entire disclosure. If the patent is in the nature of an improvement in an old apparatus, process, product, or composition, the abstract should include the technical disclosure of the improvement. The abstract should also mention by way of example any preferred modifications or alternatives. Where applicable, the abstract should include the following: (1) if a machine or apparatus, its organization and operation ; (2) if an article, its method of making; (3) if a chemical compound, its identity and use; (4) if a mixture, its ingredients; (5) if a process, the steps . Extensive mechanical and design details of an apparatus should not be included in the abstract. The abstract should be in narrative form and generally limited to a single paragraph within the range of 50 to 150 words in length. See MPEP § 608.01(b) for guidelines for the preparation of patent abstracts. The abstract of the disclosure is objected to because the invention is directed to a multiplier and a multiplication method, however, the abstract does not include the organization and operation of the multiplier or the steps of the multiplication method. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b). The abstract of the disclosure is objected to because it is also missing a period at the end. The specification is objected to under 37 C.F.R. 1.74, which requires the detailed description to refer to the different parts of the figures by use of reference letters or reference numerals. Implicit in this rule is that the detailed description correctly reference the figures. In this application the figures and detailed description are inconsistent as explained below. A. In paragraph [32] line 3 mentions a “the exponent processing unit 202”, however, 202 is labeled as “Mantissa processing unit” in Fig. 3. Examiner suggest amending the drawings to relabel 202 as “ exponent processing unit” instead. The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). See the rejection under 35 U.S.C. 112 below. Claim Objections Claim s 17 and 20 are objected to under 37 C.F.R. 1.71(a) which requires “full, clear, concise, and exact terms” as to enable any person skilled in the art or science to which the invention or discovery appertains, or with which it is most nearly connected, to make and use the same. The following should be corrected. A. In claim 17 line 5, “as as the mantissa” should read “as the mantissa” instead for better clarity. B. In claim 20 line 3, “ a multiplication computation” should read “the multiplication computation” instead because a multiplication computation is already introduced in line 1. Claim Interpretation The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph: (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: exponent processing unit first recited in claim 1 mantissa processing unit first recited in claim 1 a sign processing unit first recited in claim 4 a normalization processing unit first recited in claim 6 partial product computation unit first recited in claim 7 partial product summation unit first recited in claim 7 normalization unit first recited in claim 17 mode selection unit first recited in claim 19 Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. A. exponent processing unit (first recited in claim 1): See paragraphs [0033 and 0091] the exponent processing unit includes an adder and a subtracter circuit B . mantissa processing unit (first recited in claim 1): See Fig. 3 reference numeral 204 and paragraphs [0034] the mantissa processing unit includes a partial product computation unit and a partial product summation unit C. a sign processing unit ( first recited in claim 4 ):See Fig. 3 reference numeral 206 and paragraph [0039] the sign processing unit includes an exclusive-OR logical circuit. D. partial product computation unit ( first recited in claim 7 ): See Fig 4. reference numeral 312 and paragraph [0043] partial product computation unit includes a Booth encoding circuit and a partial product generation circuit. E. partial product summation unit ( first recited in claim 7 ): See Fig. 4 reference numeral 314 and paragraph s [0036 , 0037, 0052-0053 partial product computation unit includes an adder, a shifter and a Wallace tree compressor. If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim s 3, 9-17 and 19 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 3 recites “the data format” in line 1. It is unclear whether this is supposed to refer to the data format of the first floating-point number or the data format of the second floating-point number or to both. For purposes of examination, this is interpreted to refer to both. Claim 9 recites “wherein the partial product summation unit may include an adder” in lines 1-2. It is unclear whether the adder is optional or required because of the use of the word may. For purposes of examination, this is interpreted as wherein the partial product summation unit includes an adder. Claim 11 inherit the same deficiency as claim 9 by reason of dependence. Claim 10 recites “the adder” in line 2. There is insufficient antecedent basis for this limitation in the claim. The adder is introduced in claim 9, however, claim 10 does not depend on claim 9. For purposes of examination, this is interpreted as an adder. Claims 12-17 inherit the same deficiency as claim 10 by reason of dependence. Claim 11 recites “wherein the adder includes at least one of adders including a full adder, a serial adder and a carry lookahead adder.” This limitation is unclear because it recites a group of alternatives, however, it is not a closed group of alternatives which creates confusion as to what other alternatives are intended to be encompassed by the claim. For purposes of examination, this is interpreted as wherein the adder is a full adder, a serial adder or a carry lookahead adder. See MPEP 2173.05(h) ( I ) for more information. Claim 12 recites “the number” in line 2. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this is interpreted to refer to “the count” instead. Claims 13-14 inherit the same deficiency as claim 12 by reason of dependence. Claim 13 recites “each Wallace tree” in line 1 and “the Wallace trees” in line 2. There is insufficient antecedent basis for these limitations in the claim. The term each is normally used to every one of two or more things (plural form), however, the Wallace tree recited in claim 10 is in singular form which creates confusion as to which other Wallace tree s are being referred to. For purposes of examination, this is interpreted to refer to the Wallace tree. Claim 14 inherit the same deficiency as claim 13 by reason of dependence. Claim 16 recites “the result” in line 4. It is unclear whether this is supposed to refer to the intermediate result, the summation result or the existing summation result . For purposes of examination, this is interpreted to refer to the existing summation result. Claim 17 inherit the same deficiency as claim 16 by reason of dependence. Claim limitation s “ normalization processing unit configured to normalize the first floating-point number or the second floating-point number according to the computation mode to obtain a corresponding exponent and a corresponding mantissa when the first floating-point number or the second floating-point number is a non-normalized and non-zero floating-point number” in claim 6; “normalization unit configured to: execute floating-point number normalization processing to the mantissa and the exponent after the multiplication computation to obtain a normalized exponent result and a normalized mantissa result, take the normalized exponent result as the exponent after the multiplication computation, and take the normalized mantissa result as the mantissa after the multiplication computation” in claim 17 and “a mode selection unit configured to select the computation mode configured to indicate the data format of the first floating-point number and the data format of the second floating-point number from various computation modes supported by the multiplier” in claim 19 invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The specification is devoid of adequate structure to perform the claimed functions. There is no disclosure of any particular structure, either explicitly or inherently, to perform the normalizing of the first floating-point number or the second floating-point number; executing floating-point number normalization processing to the mantissa and the exponent after the multiplication computation; and selecting the computation mode. The specification merely describes the normalization processing unit , the normalization unit and the mode selection unit by the functions they perform without disclosing specific structure(s) to perform the se functions. Therefore, claims 7, 17 and 19 are indefinite and are rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph. Applicant may: (a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph; (b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or (c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)). If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either: (a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or (b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181. The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claim s 6, 17 and 19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. As described above, the disclosure does not provide adequate structure to perform the claimed functions of “normalize the first floating-point number or the second floating-point number according to the computation mode to obtain a corresponding exponent and a corresponding mantissa when the first floating-point number or the second floating-point number is a non-normalized and non-zero floating-point number” in claim 6; “execute floating-point number normalization processing to the mantissa and the exponent after the multiplication computation to obtain a normalized exponent result and a normalized mantissa result, take the normalized exponent result as the exponent after the multiplication computation, and take the normalized mantissa result as the mantissa after the multiplication computation” in claim 17 and “select the computation mode configured to indicate the data format of the first floating-point number and the data format of the second floating-point number from various computation modes supported by the multiplier” in claim 19. The specification does not demonstrate that applicant has made an invention that achieves the claimed function because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention. The following is a quotation of 35 U.S.C. 112(d): (d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph: Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. Claim s 5 and 9 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 5 does not further limit claim 4 upon which it depends because the limitations of claim 5 are already incorporated into claim 4, i.e. , the corresponding structure described in the specification as performing the claimed function of the sign processing unit. See 35 U.S.C. 112(f) claim interpretation section above. Claim 9 does not further limit claim s 7/8 upon which it depends because the limitations of claim 9 are already incorporated into claim 7, i.e. , the corresponding structure described in the specification as performing the claimed function of the partial product summation unit. See 35 U.S.C. 112(f) claim interpretation section above. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim s 1 -5, 7-11 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Langhammer et al. (US 20190155574 A1), hereinafter Langhammer , in view of Lee et al. (US 8301681 B1), hereinafter Lee. Regarding claim 1, Langhammer teaches a multiplier configured to execute a multiplication computation of a floating- point number according to a computation mode, wherein the floating-point number at least comprises an exponent and a mantissa, and the multiplier comprises (Langhammer Figs. 7-9 and paragraphs [0073, 0076] “DSP block 120 may be operable in at least two different floating-point multiplier modes (see, e.g., FIG. 7). As shown in FIG. 7, DSP block 120 is operable in a first floating-point mode 700 and a second floating-point mode 702. During first floating-point mode 700, DSP block 120 may be configured to receive FP16 inputs. As described above, an FP16 number has one sign bit, five exponent bits, and 10 mantissa bits, which can be represented using the following notation: { 1, 5, 10} … Still referring to FIG. 7, DSP block 120 is also operable in second floating-point mode 702. During second floating-point mode 702, DSP block 120 may be configured to receive "BFLOAT16" inputs. A BFLOAT16 floating-point number may be defined as a number that has one sign bit, eight exponent bits, and 7 mantissa bits, which can be represented using the following notation: {1, 8, 7}”; multiplier – at least the multiplier datapath 150 and exponent handling circuitry 900; floating- point number – floating-point inputs; computation mode – mode 700 or 702) : an exponent processing unit configured to obtain an exponent after the multiplication computation according to the computation mode, an exponent of a first floating-point number and an exponent of a second floating-point number (Langhammer Fig. 9 and paragraphs [0086-0088]; exponent processing unit - exponent handling circuitry 900; exponent of a first floating-point number – ExpA; exponent of a second floating-point number – ExpB) ; and a mantissa processing unit configured to obtain a mantissa after the multiplication computation according to the computation mode, a mantissa of the first floating-point number and a mantissa of the second floating-point number (Langhammer Figs. 8A-8B and paragraphs [0078, 0081] “CPA 314 may output the mantissa of a first floating-point product, whereas CPA 315 may output the mantissa of a second floating-point product”; mantissa processing unit - multiplier datapath 150/circuits 310-315 and 320; paragraph [0084] “the same input bits to DSP block 120 for both FP16 and BFLOAT16 can be reused. For instance, four pairs of 16 input terminals can be reused. In this arrangement, an input switch such as input multiplexer 802 (see, e.g., FIGS. 8A and 8B) can be used to extract the desired bits in either of modes 700 or 702”) , wherein the computation mode is configured to indicate a data format of the first floating- point number and a data format of the second floating-point number (Langhammer Figs. 8A-8B and paragraphs [0073 and 0076] “During first floating-point mode 700, DSP block 120 may be configured to receive FP16 inputs. As described above, an FP16 number has one sign bit, five exponent bits, and 10 mantissa bits, which can be represented using the following notation: { 1, 5, 10} … Still referring to FIG. 7, DSP block 120 is also operable in second floating-point mode 702. During second floating-point mode 702, DSP block 120 may be configured to receive "BFLOAT16" inputs. A BFLOAT16 floating-point number may be defined as a number that has one sign bit, eight exponent bits, and 7 mantissa bits, which can be represented using the following notation: {1, 8, 7}”). Langhammer does not explicitly teach an exponent processing unit configured to obtain an exponent after the multiplication computation . However, on the same field of endeavor, Lee discloses an exponent processing unit configured to obtain an exponent after the multiplication computation (Lee Fig. 6 and col 11 lines 60-65; exponent – output of multiplexer 652; exponent processing unit – logic 65 and 650-652). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Langhammer using Lee and configure the exponent handling circuitry to include a multiplexer for selecting the output of circuit 906 or an output+1 in order to account for the rounding and the normalization operation after the mantissa multiplication (Lee Fig. 6 and col 11 lines 60-65). As disclosed by Lee, the final exponent depends on the normalization and rounding of the mantissa multiplication, therefore, the exponent is obtained after the mantissa multiplication operation. Therefore, the combination of Langhammer as modified in view of Lee teaches an exponent processing unit configured to obtain an exponent after the multiplication computation according to the computation mode, an exponent of a first floating-point number and an exponent of a second floating-point number. Regarding claim 2, Langhammer as modified in view of Lee teaches all the limitation of claim 1 as stated above. Further, Langhammer as modified in view of Lee teaches wherein the computation mode is further configured to indicate a data format after the multiplication computation (Langhammer paragraph [0078] “the width and rounding mode of CPA 314 and 315 can be independently determined or may be dependent on the input representation”; paragraph [0081] “the width and rounding mode of CPA 314 and 315 can be independently determined or may be dependent on the input representation”). Regarding claim 3, Langhammer as modified in view of Lee teaches all the limitation of claim 1 as stated above. Further, Langhammer as modified in view of Lee teaches wherein the data format includes at least one of numbers including a half-precision floating-point number, a single precision floating- point number, a brain floating-point number, a double precision floating-point number and a self definition floating-point number (Langhammer Figs. 8A-8B and paragraphs [0073, 0076 and 0085]). Regarding claim 4, Langhammer as modified in view of Lee teaches all the limitation of claim 1 as stated above. Further, Langhammer as modified in view of Lee teaches wherein the floating-point number further includes a sign, and the multiplier further includes (Langhammer Figs. 7-8B and paragraphs [0073, 0076]) : a sign processing unit configured to obtain a sign after the multiplication computation according to a sign of the first floating-point number and a sign of the second floating-point number (Langhammer Figs. 8A-8B and paragraphs [0079, 0082] sign – sign of the intermediate format IF (output of the CPA)). Langhammer does not explicitly teach a sign processing unit configured to obtain a sign after the multiplication computation according to a sign of the first floating-point number and a sign of the second floating-point number . However, on the same field of endeavor, Lee discloses a sign processing unit configured to obtain a sign of a multiplication result according to a sign of the first floating-point number and a sign of the second floating-point number (Lee Fig. 6; col 11 line 13 and col 11 lines 46-47 “The two sign bits 611, 621 preferably are input to XOR 63 to compute the output sign”; col 11 lines 65-67 “All of the values are then input to output multiplexer 67 to provide the final output to output register 68”; sign processing unit – XOR gate and part of the output multiplexer 67 processing the sign bit to the output register 68). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Langhammer using Lee and configure the multiplier circuitry to include sign processing circuitry (XOR logic) for calculating the sign of the product of the multiplication result (Lee col 11 lines 46-47) which is a common implementation to compute the sign of a multiplication result . Therefore, the combination of Langhammer as modified in view of Lee teaches a sign processing unit configured to obtain a sign after the multiplication computation according to a sign of the first floating-point number and a sign of the second floating-point number. Regarding claim 5, Langhammer as modified in view of Lee teaches all the limitation of claim 4 as stated above. Further, Langhammer as modified in view of Lee teaches wherein the sign processing unit includes an exclusive-OR logical circuit , which is configured to execute an exclusive-OR computation according to the sign of the first floating-point number and the sign of the second floating-point number to obtain the sign after the multiplication computation (Lee Fig. 6 and col 11 line 13 “(b) Sign_X=Sign_A (XOR) Sign_B”; col 11 lines 46-47 “The two sign bits 611, 621 preferably are input to XOR 63 to compute the output sign”; exclusive-OR logical circuit - XOR 63). Regarding claim 7, Langhammer as modified in view of Lee teaches all the limitation of claim 1 as stated above. Further, Langhammer as modified in view of Lee teaches wherein the mantissa processing unit includes a partial product computation unit and a partial product summation unit, wherein the partial product computation unit is configured to obtain an intermediate result according to the mantissa of the first floating-point number and the mantissa of the second floating-point number, and the partial product summation unit is configured to sum intermediate results to obtain a summation result and take the summation result as the mantissa after the multiplication computation (Langhammer Figs. 3-4, 8A-8B and paragraphs [0041-0042] “The first part of the multiplication is the generation of the partial products, which can be computed using partial product generation circuit 210. The partial products output from circuit 210 may then be summed (after appropriate shifting) to generate the final product. In ASIC (Application Specific Integrated Circuit) technology, the summation may be split into two different operations: (1) compression and (2) carry propagate addition. First, the partial products are compressed using compression circuit 212, which may be implemented as Wallace trees, Dadda trees, or other suitable parallel counters. The output of compressor 212 is two redundant form vectors such as a sum vector and a carry vector. These vectors are then added together using a carry propagate adder (CPA) 214. Carry propagate adder 214 may be implemented as a ripple carry adder, a carry look-ahead adder, or a carry prefix adder such as the Kogge-Stone network, Brent-Kung network, and others. The product or result of the multiplication (i.e., A *B, which generated at the output of CPA 214) is then provided as an output to multiplier data path 150”; partial product computation unit - partial product generation circuit; partial product summation unit – compressors and carry propagate adders (CPAs) ) . Regarding claim 8, Langhammer as modified in view of Lee teaches all the limitation of claim 7 as stated above. Langhammer does not explicitly teach wherein the partial product computation unit includes a Booth encoding circuit, which is configured to add zeros and execute a Booth encoding processing to a high bit and a low bit of the mantissa of the first floating-point number or the second floating-point number to obtain the intermediate result . However, on the same field of endeavor, Lee discloses a partial product generator configured to execute a Booth encoding processing to a high bit and a low bit of the mantissa of a first floating-point number or a second floating-point number to obtain an intermediate result (Lee col 8 lines 43-54 “Each partial product generator 31 preferably creates nine 20-bit signed Booth-encoded vectors (Booth-encoding is a known technique that can reduce the number of partial products), as well as a 17-bit unsigned carry vector (negative partial products are in ones-complement format, with the associated carry-in bit in the carry vector)”). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Langhammer using Lee and configure the partial product generation circuit to include a Booth encoding circuit, which is configured to add zeros and execute a Booth encoding processing to a high bit and a low bit of the mantissa of the first floating-point number or the second floating-point number to obtain the intermediate result because Booth-encoding is a known technique to reduce the number of partial products (Lee col 8 lines 43-54). Therefore, the combination of Langhammer as modified in view of Lee teaches wherein the partial product computation unit includes a Booth encoding circuit, which is configured to add zeros and execute a Booth encoding processing to a high bit and a low bit of the mantissa of the first floating-point number or the second floating-point number to obtain the intermediate result. Regarding claim 9, Langhammer as modified in view of Lee teaches all the limitation of claim 8 as stated above. Further, Langhammer as modified in view of Lee teaches wherein the partial product summation unit may include an adder, which is configured to sum the intermediate results to obtain the summation result (Langhammer Figs. 3-4 and 8A-8B and paragraph [0042] “The product or result of the multiplication (i.e., A *B, which generated at the output of CPA 214)”; paragraphs [0078, 0081] “CPA 314 may output the mantissa of a first floating-point product, whereas CPA 315 may output the mantissa of a second floating-point product”; adder – CPA). Regarding claim 10, Langhammer as modified in view of Lee teaches all the limitation of claim 8 as stated above. Further, Langhammer as modified in view of Lee teaches wherein the partial product summation unit includes a Wallace tree and the adder, wherein the Wallace tree is configured to sum the intermediate results to obtain a second intermediate result, and the adder is configured to sum second intermediate results to obtain the summation result (Langhammer Figs. 3-4 and 8A-8B and paragraph [004 2 ] “the summation may be split into two different operations: (1) compression and (2) carry propagate addition. First, the partial products are compressed using compression circuit 212, which may be implemented as Wallace trees … The output of compressor 212 is two redundant form vectors such as a sum vector and a carry vector. These vectors are then added together using a carry propagate adder (CPA) 214. Carry propagate adder 214 may be implemented as a ripple carry adder, a carry look-ahead adder, or a carry prefix adder such as the Kogge-Stone network, Brent-Kung network, and others”; Wallace tree - compression circuit implemented as Wallace trees; adder – CPA). Regarding claim 11, Langhammer as modified in view of Lee teaches all the limitation of claim 9 as stated above. Further, Langhammer as modified in view of Lee teaches wherein the adder includes at least one of adders including a full adder, a serial adder and a carry lookahead adder (Langhammer paragraph [0042] “Carry propagate adder 214 may be implemented as … a carry look-ahead adder”). Regarding claim 20, it is directed to a method practiced by the multiplier of claim 1. All steps performed by the method of claim 20 would be practiced by the multiplier of claims. Claim 1 analysis applies equally to claim 20. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Langhammer in view of Lee as applied to claim 1 above, and further in view of Lutz et al. (US 20150254066 A1), hereinafter Lutz. Regarding claim 6, Langhammer as modified in view of Lee teaches all the limitation of claim 1 as stated above. Langhammer does not explicitly teach the multiplier further includes: a normalization processing unit configured to normalize the first floating-point number or the second floating-point number according to the computation mode to obtain a corresponding exponent and a corresponding mantissa when the first floating-point number or the second floating-point number is a non-normalized and non-zero floating-point number . However, on the same field of endeavor, Lutz discloses a normalization circuitry configured to normalize a first floating-point number or a second floating-point number to obtain a corresponding exponent and a corresponding mantissa when the first floating-point number or the second floating-point number is a non-normalized and non-zero floating-point number (Lutz Figs. 2 and 8; paragraph [0013] “normalization circuitry configured to be responsive to one of said first and second input floating point operands being a subnormal operand, to form the corresponding normalized floating point operand to have a significand formed by shifting the significand of the subnormal operand in said first direction by a normalising amount and to have an exponent formed by adjusting the exponent of the subnormal operand dependent on said normalising amount”; paragraphs [0041, 0063]). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Langhammer in view of Lee using Lutz and configure the multiplier circuitry to include normalization circuitry for normalizing subnormal input prior to the multiplication operation (Lutz paragraph [0013]). Further, Langhammer discloses that the FP mode 700 may be provided with subnormal support, therefore, it would be obvious to include normalization circuitry in order to normalize subnormal numbers and support subnormal numbers (Langhammer Fig. 7 and paragraphs [0075, 0105]). Therefore, the combination of Langhammer as modified in view of Lee and Lutz teaches the multiplier further includes: a normalization processing unit configured to normalize the first floating-point number or the second floating-point number according to the computation mode to obtain a corresponding exponent and a corresponding mantissa when the first floating-point number or the second floating-point number is a non-normalized and non-zero floating-point number. Claim s 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Langhammer in view of Lee as applied to claim 10 above, and further in view of Rarick et al. (US 20100057824 A1), hereinafter Rarick. Regarding claim 12, Langhammer as modified in view of Lee teaches all the limitation of claim 10 as stated above. Langhammer does not explicitly teach wherein when a count of the intermediate results is less than M, zero values are added as the intermediate results to make the number of the intermediate results equal to M, wherein M is a presupposed positive integer . However, on the same field of endeavor, Rarick discloses wherein when a count of intermediate results is less than M, zero values are added as the intermediate results to make the number of the intermediate results equal to M, wherein M is a predetermined positive integer (Rarick Fig. 3 and paragraph [0033] “In this case, using Booth Encoding (110), such a multiplication results in 27 partial products. However, because the hardware is large enough to accommodate 33 partial products, the hardware creates 33 partial products for the floating point operation, where the additional partial products are all zeros (i.e., only 27 of the partial products include data)”; M – 33 which is the number of input ports of the compressor circuit). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Langhammer in view of Lee using Rarick and configure the partial product generation circuit to generate additional all zero partial products when a count of the partial products is less than M to make the number of the intermediate results equal to M in order to match the number of partial products with number of input ports of the compressor such that multiplier can support different precisions of floating-point multiply operations (Rarick paragraphs [0003, 0033]). Therefore, the combination of Langhammer as modified in view of Lee and Rarick teaches wherein when a count of the intermediate results is less than M, zero values are added as the intermediate results to make the number of the intermediate results equal to M, wherein M is a presupposed positive integer. Regarding claim 13, Langhammer as modified in view of Lee and Rarick teaches all the limitation of claim 12 as stated above. Further, Langhammer as modified in view of Lee and Rarick teaches wherein each Wallace tree has M inputs and N outputs, and a count of the Wallace trees is no less than K, wherein N is a presupposed positive integer less than M, and K is a positive integer that is no less than a largest bit width of the intermediate results (Langhammer Figs. 8A-8B and paragraph [0042] “First, the partial products are compressed using compression circuit 212, which may be implemented as Wallace trees … The output of compressor 212 is two redundant form vectors such as a sum vector and a carry vector ”; see a lso claim 12 analysis and Rarick Fig. 3; the number of partial products equals the number of input ports of the Wallace tree compression circuit; N -2; K - 1 or number of 4:2 compressors in the Wallace tree). Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Langhammer in view of Lee and Rarick as applied to claim 13 above, and further in view of Kurd (US 7840628 B2). Regarding claim 14, Langhammer as modified in view of Lee and Rarick teaches all the limitation of claim 13 as stated above. Further, Langhammer as modified in view of Lee and Rarick teaches wherein the partial product summation unit is configured to select one group or a plurality of groups of Wallace trees to sum the intermediate results (Langhammer paragraph [0047] “DSP block 120 may include at least two partial product generating circuits 310 and 311, two compression circuits 312 and 313, and two carry propagate adders (CPA) 314 and 315. All of these decomposed component pairs can be combined into a single respective structure when not being used to support machine learning applications”; the compressors and CPAs are selected to be combined or operate independently to sum the partial products based on the computation mode). Langhammer does not explicitly teach wherein each group of Wallace tree has X Wallace trees, and X is a bit number of the intermediate result, wherein Wallace trees in each group have successive carry relationships, but there is no carry relationship between Wallace trees from different groups . However, on the same field of endeavor, Kurd discloses wherein a group of Wallace tree has X Wallace trees, and X is a bit number of the intermediate result, wherein Wallace trees in the group have successive carry relationships, but there is no carry relationship between Wallace trees from different groups (Kurd Figs. 2-3 and col 4 lines 19-28 and 41-62; col 5 line 43 to col 4 line 14; although a single compression circuit is shown, there would be mx2 compression circuit since each compression circuit only adds bits with a same bit weighting). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Langhammer in view of Lee and Rarick using Kurd and configure each compressor (group of Wallace tree s ) to include mx2 Wallace trees each for adding together partial product bits having the same weight ( i.e., column wise addition similar to how partial products are normally added manually ) with carry relationships in each group and no carry relationship between different groups in order to generate the sum vector an carry vector provided to the CPAs for final addition to generate the product. As discussed, Langhammer discloses using Wallace trees to implement the compressors in paragraph [0042] while Kurd discloses how Wallace trees are configured to perform partial product compression which is well-known in the art (Kurd col 4 line 38-40]). Therefore, the combination of Langhammer as modified in view of Lee, Rarick and Kurd teaches wherein each group of Wallace tree has X Wallace trees, and X is a bit number of the intermediate result, wherein Wallace trees in each group have successive carry relationships, but there is no carry relationship between Wallace trees from different groups. Claims 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Langhammer in view of Lee and Rarick as applied to claim 12 above, and further in view of Bosshart (US 4754421 A). Regarding claim 15, Langhammer as modified in view of Lee and Rarick teaches all th