DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 22, 2026 has been entered.
Status of Claims
Claims 1, 3-5, 7-8, and 10-21 are pending, with claim 1 currently amended, claims 2, 6, and 9 cancelled, and claims 14-20 withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites the limitation "the metal wiring" in line 2. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, “the metal wiring” is interpreted as “a metal wiring.” Claim 11 depends upon claim 10.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 3-5, 7-8, 10-13, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Kamada et al. (US PG-Pub No.: 2021/0005669 A1, hereinafter, “Kamada”), prior art of record, in view of Park et al. (US PG-Pub No.: 2021/0296609 A1, hereinafter, “Park”), prior art of record, and Joo et al. (US PG-Pub No.: 2021/0318770 A1, hereinafter, “Joo”), prior art of record.
Regarding claim 1, Kamada discloses a display panel (see Kamada, FIG. 16), comprising:
a thin-film transistor (208, FIG. 16) comprising a source (222a, ¶ [0262]), a drain (222b, ¶ [0262]), and a gate (223, ¶ [0262]), wherein the thin-film transistor (208) serves as a driving switch for pixels of the display panel to emit light (FIG. 16);
an anode (191R, ¶ [0192]) electrically connected to the thin-film transistor (208), wherein a material of the anode (191R) comprises silver-palladium-copper alloy (Table 1);
a bonding pad (166, FIG. 16) electrically connected to the thin-film transistor (208, FIGs. 13 and 16; FIG. 13 shows that FPC 172 is the external circuit for the display panel sending and receiving electrical signals, and ¶ [0242] discloses that 172 is electrically connected with both 162 and 164 to supply a signal and power; therefore, although not shown in FIG. 16, 166 is electrically connected with the driving transistor 208), wherein a material of the bonding pad (166) is same as the material of the anode (191R, ¶¶ [0109] and [0272]),
a passivation layer (214a, FIG. 17; FIG. 16 labelled wrongly since FIG. 16 labelled 214a and 214b as the same layer), wherein the passivation layer (214a) is disposed on the thin-film transistor (208) and covers the thin-film transistor (208), and the passivation layer (214a) comprises a first through hole (hole for part of 169R, FIG. 16) defined on the thin-film transistor (208), and
a planarization layer (214b, FIG. 16), wherein the planarization layer (214b) is disposed on the passivation layer (214a), and the planarization layer (214b) comprises a second through hole (hole for 191R and part of 169R, FIG. 16) defined corresponding to a position of the first through hole (hole for 169R).
Kamada is silent regarding that the anode further comprises a transparent conductive oxide disposed on two opposite surfaces of the silver-palladium-copper alloy; and a hole position of the first through hole overlaps with and corresponds to a hole position of the second through hole, and the second through hole is provided with a bottom opening on a surface of the passivation layer away from the thin-film transistor, the first through hole is provided with a top opening on the surface of the passivation layer away from the thin-film transistor, wherein a projection area of the bottom opening on a surface of the passivation layer close to the thin film transistor covers and is larger than a projection area of the top opening on the surface of the passivation layer close to the thin film transistor.
Park, however, discloses a display panel (see Park, FIG. 5), wherein an anode comprises a transparent conductive oxide disposed on two opposite surfaces of the silver-palladium-copper alloy (ITO/APC/ITO, ¶ [0109]). Park also discloses that the source and the drain (S1 and D1, FIG. 5) comprising copper or copper alloy (¶ [0099]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to form Kamada’s anode comprising a transparent conductive oxide disposed on two opposite surfaces of the silver-palladium-copper alloy, as taught by Park, in order to improve light efficiency (¶ [0109]); and to form Kamada’s metal wiring, the source, and the drain with copper or copper alloy, as taught by Park, since copper has low resistance and it is a great material to form electrodes.
Kamada in view of Park is silent regarding that a hole position of the first through hole overlaps with and corresponds to a hole position of the second through hole, and the second through hole is provided with a bottom opening on a surface of the passivation layer away from the thin-film transistor, the first through hole is provided with a top opening on the surface of the passivation layer away from the thin-film transistor, wherein a projection area of the bottom opening on a surface of the passivation layer close to the thin film transistor covers and is larger than a projection area of the top opening on the surface of the passivation layer close to the thin film transistor.
Joo, however, discloses a display panel (see Joo, FIG. 8), wherein a second through hole (hole for part of 171 and part of ANDE1 in 160, FIG. 8) is provided with a bottom opening on a surface of a passivation layer (150, FIG. 8) away from a thin-film transistor (ST, FIG. 8), a first through hole (hole for part of ANDE1 in 150) is provided with a top opening on the surface of the passivation layer (150) away from the thin-film transistor (ST), wherein a projection area of the bottom opening on a surface of the passivation layer (150) close to the thin film transistor (ST) covers and is larger than a projection area of the top opening on the surface of the passivation layer (150) close to the thin film transistor (ST, FIG. 8).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to form the second through hole of Kamada in view of Park provided with a bottom opening on a surface of the passivation layer away from the thin-film transistor, the first through hole is provided with a top opening on the surface of the passivation layer away from the thin-film transistor, wherein a projection area of the bottom opening on a surface of the passivation layer close to the thin film transistor covers and is larger than a projection area of the top opening on the surface of the passivation layer close to the thin film transistor, as taught by Joo, since it is an alternative design.
Regarding claim 3, Kamada in view of Park and Joo discloses the display panel according to claim 1, wherein the transparent conductive oxide comprises indium oxide (Park, ¶ [0109]), antimony oxide, or cadmium oxide.
Regarding claim 4, Kamada in view of Park and Joo discloses the display panel according to claim 1, wherein the bonding pad (166) further comprises a transparent conductive oxide disposed on two opposite surfaces of the silver-palladium-copper alloy (see statement above regarding claim 1).
Regarding claim 5, Kamada in view of Park and Joo discloses the display panel according to claim 4, wherein the transparent conductive oxide comprises indium oxide (Park, ¶ [0109]), antimony oxide, or cadmium oxide.
Regarding claim 7, Kamada in view of Park and Joo discloses the display panel according to claim 1, wherein the anode (181) is electrically connected to the thin-film transistor (203) through the first through hole and the second through hole (Park, FIG. 16).
Regarding claim 8, Kamada in view of Park and Joo discloses the display panel according to claim 7, wherein the first through hole and the second through hole are respectively defined through two manufacturing processes (claim 8 is a device claim, even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. See MPEP § 2113(I)).
Regarding claim 10, Kamada in view of Park and Joo discloses the display panel according to claim 1, wherein the passivation layer (214a) further comprises a third through hole defined above a metal wiring (165; Kamada, FIG. 16), and the bonding pad (166) is electrically connected to the metal wiring (165) through the third through hole (FIG. 16).
Note: for the purpose of examination, “the metal wiring” is interpreted as “a metal wiring.” Claim 11 depends upon claim 10.
Regarding claim 11, Kamada in view of Park and Joo discloses the display panel according to claim 10, wherein the first through hole and the third through hole are defined through a same manufacturing process (claim 11 is a device claim, even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. See MPEP § 2113(I)).
Regarding claim 12, Kamada in view of Park and Joo discloses the display panel according to claim 1.
Kamada is silent regarding that the thin-film transistor comprises a top-gate thin-film transistor.
Park, however, discloses a display panel (see Park, FIG. 5), comprising a top gate thin-film transistor (T1, FIG. 5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to form Kamada’s thin-film transistor a top-gate thin-film transistor, as taught by Park, since it is an alternative design (Park, ¶ [0094]).
Regarding claim 13, Kamada in view of Park and Joo discloses the display panel according to claim 1, wherein the display panel is an organic light-emitting diode display panel (Kamada, ¶ [0065]), and the anode (181) is an anode of an organic light-emitting diode (FIG. 16).
Regarding claim 21, Kamada in view of Park and Joo discloses the display panel according to claim 1, wherein the display panel further comprises a metal wiring (165; Kamada, ¶ [0240]), the metal wiring (165), and the source (222a) and the drain (222b) of the thin-film transistor (208) are disposed in a same layer (FIG. 16), and the bonding pad (166) is electrically connected to the thin-film transistor (208, since 172 is electrically connected with both 162 and 164 to supply a signal and power) serving as a driving switch for pixels of the display panel (FIG. 16) to emit light through the metal wiring (165).
Kamala is silent regarding that the metal wiring adopting copper or copper alloy.
Park, however, discloses that source and drain (S1 and D1, FIG. 5) comprising copper or copper alloy (¶ [0099]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to form Kamada’s metal wiring, the source, and the drain with copper or copper alloy, as taught by Park, since copper has low resistance and it is a great material to form electrodes.
Response to Arguments
Applicant's arguments filed on Jan 22, 2026 have been fully considered but they are not persuasive. Applicant alleged that Joo fails to disclose a projection area of the bottom opening on a surface of the passivation layer close to the thin film transistor covers and is larger than a projection area of the top opening on the surface of the passivation layer close to the thin film transistor (Remarks, pages 7-10). Examiner respectfully disagrees. Joo’s first through hole is a hole in 150 filled by part of ANDE1 and Joo’s second through hole is a hole in 160 filled by part of 171 and part of ANDE1. The first and second though holes are holes going through 150 and 160 separately, which meet the claim limitations as stated in rejection for claim 1 above.
Conclusion
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/XIA L CROSS/Primary Examiner, Art Unit 2892