Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
2. This Final Office Action is responsive to Applicants’ amendments and arguments, as received 9/8/25. Claims 1 and 5-15 are pending, of which claim 1 is independent.
Claim Rejections - 35 USC § 102
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office Action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 1 and 13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by U.S. Patent Application Publication No. 2020/0394502 (“Chen”).
Regarding claim 1, CHEN teaches A three-dimensional (Chen’s FIGs. 1 and 4-7 show three dimensions in terms of D1-D3) neuromorphic device (Chen’s [0004]-[0006] framing its teachings as relating to “a neuromorphic computing device”) having multiple synapses per neuron (the aforementioned device per Chen has “a plurality of synapses”, which are used to connect different “neural regions” and “neural circuits” per Chen’s [0018] for example, where a neural region or a neural circuit can be understood to be equivalent to Applicants’ recitation of a “neuron” for which there are “multiple synapses”), comprising:
a common gate (Chen’s [0045] discussing “a common gate” in relation to transistors, where transistors are understood by the Examiner for use to implement synapses per [0045]-[0046]) configured to implement a single axon (based on the prior mapping, if a gate services different transistors to connect different neural regions/circuits, then the gate is akin/analogous to a biological axon relative to biological neurons); and
a plurality of data storage elements configured to implement each of a plurality of synapses (transistors per Chen’s [0044]-[0046]),
wherein the plurality of data storage elements have different physical structures providing different weights (transistors are associated with synapse weights per Chen’s [0044]-[0046]),
wherein the plurality of data storage elements having different weights will store and process data to which a plurality of weights are assigned in parallel, in response to a signal flowing through the common gate (transistors are each associated with synapse weights per Chen’s [0044]-[0046], and may share a same source and drain per [0045] (i.e., are “parallel”), and a “common gate” also per [0045]), and
wherein the different physical structures are formed of different thicknesses or of different composition materials to provide the different weights (Chen’s [0043]-[0044] discussing differences in various physical attributes of the resistive material layers, including size, thickness, materials, and structures (all of which read on the recitation for “different structure”), with the differentiation being said to be explicitly varied to realize the synapse weights as needed, and see also the discussion of different transistor arrangements per [0046] to realize different synapse weights (where a different arrangement is understood to read on the recitation for a “different structure”), where the synapse weights per synapse/transistor are understood to be differentiable in accordance with Chen’s [0019]-[0021]).
Regarding claim 13, Chen teaches the three-dimensional neuromorphic device of claim 1, wherein the three-dimensional neuromorphic device is used as a pre-neuron and a post-neuron connected through at least one synapse of the pre-neuron and the plurality of synapses (as discussed per claim 1, Chen teaches “a plurality of synapses”, which are used to connect different “neural regions” and “neural circuits” per Chen’s [0018] for example, such that the region/circuit on either side of the synapse connection can be understood to each be one of a respective pre and post neuron construct as recited).
Claim Rejections - 35 USC § 103
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office Action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
9. Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of U.S. Patent No. 11672133 (“Lilak”).
Regarding claim 5, Chen teaches the three-dimensional neuromorphic device of claim 1, as discussed above. Chen teaches that neuromorphic computing devices, such as the one taught therein, are implemented using memory arrays, per [0002]. Moreover, Chen’s neuromorphic computing device is implemented using a stacking of layers to realize its synapse weighting, per [0037]-[0043]. Chen provides examples therein of what materials may be used to implement these layers but does not specifically teach the further limitation wherein each of the plurality of data storage elements is a nitride layer of ONO (Oxide layer-Nitride layer-Oxide layer) in a flash memory. Rather, the Examiner relies upon LILAK to teach what Chen otherwise lacks, see e.g., Lilak’s column 10 lines 31-47 discussing implementation of a flash memory with different layers as stacked (e.g., tunnel oxide, silicon nitride, blocking oxide) in a configuration reading on this present recitation.
Both Chen and Lilak relate to the implementation of a working/operable transistor-based memory based on the layering of known materials having known resistance/conductance/capacitance properties. Hence, they are similarly directed and therefore analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the particular materials considered by Lilak to implement Chen’s framework, with a reasonable expectation of success, such that the ONO layering is known and practiced in the state of the art to provide the same function needed per Chen to implement its neuromorphic architecture.
Regarding claim 6, Chen in view of Lilak teach the three-dimensional neuromorphic device of claim 5, as discussed above. The aforementioned references teach the additional limitations wherein the plurality of nitride layers have different amounts of charge depending on having different capacitance values through different physical structures (see Chen’s discussion per [0037]-[0043] discussing how the layering and composition of different materials with differing conductance and resistance properties results in the realization of the synapse weighting for its neuromorphic architecture, with Lilak as discussed per claim 5 providing a specific version of that layering that is using the ONO configuration). The motivation for combining the references is as discussed above in relation to claim 5.
10. Claims 7-8, 11-12, and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Non-Patent Literature “Mott Memory and Neuromorphic Devices” (“Zhou”) {previously cited and relied upon in the prior Office Action}.
Regarding claim 7, Chen teaches the three-dimensional neuromorphic device of claim 1, as discussed above. Chen teaches that neuromorphic computing devices, such as the one taught therein, are implemented using memory arrays, per [0002]. Moreover, Chen’s neuromorphic computing device is implemented using a stacking of layers to realize its synapse weighting, per [0037]-[0043]. Chen provides examples therein of what materials may be used to implement these layers but does not specifically teach the further limitation wherein each of the plurality of data storage elements is a Mott insulator layer of OMO (Oxide layer-Mott insulator layer-Oxide layer) in a Mott memory. Rather, the Examiner relies upon ZHOU to teach what Chen otherwise lacks, see e.g., Zhou’s section III discussing implementations using Mott transitions for memory and neuromorphic devices, as mentioned in the final paragraph of Zhou’s section I, and per section III (B) it is discussed that “A layer of Mott insulator is sandwiched between two gate oxide layers, which forms the gate oxide stack of a metal–oxide–semiconductor field-effect transistor (MOSFET).”
Both Chen and Zhou relate to the implementation of a working/operable transistor-based memory based on the layering of known materials having known resistance/conductance/capacitance properties. Hence, they are similarly directed and therefore analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the particular materials considered by Zhou to implement Chen’s framework, with a reasonable expectation of success, such that the OMO layering is known and practiced in the state of the art to provide the same function needed per Chen to implement its neuromorphic architecture.
Regarding claim 8, Chen in view of Zhou teach the three-dimensional neuromorphic device of claim 7, as discussed above. The aforementioned references teach the additional limitations wherein the plurality of Mott insulator layers have different conductivities or different resistance values, depending on having different phase transition characteristics (Insulator-to-Metal Phase Transition: Mott Transition) through different physical structures (see Chen’s discussion per [0037]-[0043] discussing how the layering and composition of different materials with differing conductance and resistance properties results in the realization of the synapse weighting for its neuromorphic architecture, with Zhou as discussed per claim 7 providing a specific version of that layering that is using the OMO configuration). The motivation for combining the references is as discussed above in relation to claim 7.
Regarding claim 11, Chen teaches the three-dimensional neuromorphic device of claim 1, as discussed above. Chen does not teach the further limitation wherein each of the plurality of data storage elements is an oxide layer in a resistance change memory. Rather, the Examiner relies upon ZHOU to teach what Chen otherwise lacks, see e.g., Zhou’s section II(F), second to last paragraph, discussing “multistate nonvolatile resistance change.”
Both Chen and Zhou relate to the implementation of a working/operable transistor-based memory based on the layering of known materials having known resistance/conductance/capacitance properties. Hence, they are similarly directed and therefore analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the particular materials considered by Zhou to implement Chen’s framework, with a reasonable expectation of success, such that Zhou’s layering is known and practiced in the state of the art to provide the same function needed per Chen to implement its neuromorphic architecture.
Regarding claim 12, Chen in view of Zhou teach the three-dimensional neuromorphic device of claim 11, as discussed above. The aforementioned references teach the additional limitations wherein the plurality of oxide layers have different resistance values or different conductance values depending on having different resistances or different conductance change characteristics through different physical structures (see Chen’s discussion per [0037]-[0043] discussing how the layering and composition of different materials with differing conductance and resistance properties results in the realization of the synapse weighting for its neuromorphic architecture, with Zhou as discussed per claim 11 providing a specific version of that layering). The motivation for combining the references is as discussed above in relation to claim 11.
Regarding claim 14, Chen teaches the three-dimensional neuromorphic device of claim 13, as discussed above. While Chen teaches pre- and post-neuron constructs, as the Examiner has discussed per claim 13, it does not teach the further limitation wherein the three-dimensional neuromorphic device used as the pre-neuron, when it is necessary to store the same data as previously stored data in the plurality of data storage elements included in the three-dimensional neuromorphic device used as the pre-neuron, performs only an output function in response to the three-dimensional neuromorphic device used as the post-neuron connected through the plurality of data storage elements being switched off. Rather, the Examiner relies upon ZHOU to teach what Chen otherwise lacks, see e.g., Zhou’s section III(D) discussing that a neuron implementation can have presynaptic and postsynaptic aspects, and to the extent that this implemented using Mott insulators featuring Mott transitions, the Examiner then notes Zhou’s section I, third full paragraph, discussing state switching between 0 and 1 as a function of stimulus being applied/removed in a manner that facilitates read/write as shown in FIG. 1, which the Examiner equates with the switching on/off of data storage elements as recited here.
Both Chen and Zhou relate to the implementation of a working/operable transistor-based memory based on the layering of known materials having known resistance/conductance/capacitance properties. Hence, they are similarly directed and therefore analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the particular materials considered by Zhou, e.g. Mott insulators, to implement Chen’s framework, with a reasonable expectation of success, such that Zhou’s layering is known and practiced in the state of the art to provide the same function needed per Chen to implement its neuromorphic architecture.
Regarding claim 15, Chen teaches the three-dimensional neuromorphic device of claim 13, as discussed above. While Chen teaches pre- and post-neuron constructs, as the Examiner has discussed per claim 13, it does not teach the further limitation wherein the three-dimensional neuromorphic device used as the pre-neuron, when it is necessary to delete weighted data stored in the plurality of data storage elements included in the three-dimensional neuromorphic device used as the pre-neuron, deletes the weighted data stored in the plurality of data storage elements, in response to a backward pulse as the three-dimensional neuromorphic device used as the post-neuron connected through the plurality of data storage elements is switched on. Rather, the Examiner relies upon ZHOU to teach what Chen otherwise lacks, see e.g., Zhou’s section III(D) discussing that a neuron implementation can have presynaptic and postsynaptic aspects, and to the extent that this implemented using Mott insulators featuring Mott transitions, the Examiner then notes Zhou’s section I, third full paragraph, discussing state switching between 0 and 1 as a function of stimulus being applied/removed in a manner that facilitates read/write as shown in FIG. 1, which the Examiner equates with the switching on/off of data storage elements as recited here.
Both Chen and Zhou relate to the implementation of a working/operable transistor-based memory based on the layering of known materials having known resistance/conductance/capacitance properties. Hence, they are similarly directed and therefore analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the particular materials considered by Zhou, e.g. Mott insulators, to implement Chen’s framework, with a reasonable expectation of success, such that Zhou’s layering is known and practiced in the state of the art to provide the same function needed per Chen to implement its neuromorphic architecture.
11. Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of U.S. Patent Application Publication No. 2015/0039547 (“Kang”).
Regarding claim 9, Chen teaches the three-dimensional neuromorphic device of claim 1, as discussed above. Chen does not teach the further limitation wherein each of the plurality of data storage elements is a phase change material (PCM) layer in a phase change memory. Rather, the Examiner relies upon KANG to teach what Chen otherwise lacks, see e.g., Kang’s comparable neuromorphic architecture ([0006]) where memory cell resistance is implemented using phase change material, per [0052].
Like Chen, Kang contemplates a neuromorphic architecture. Hence, they are similarly directed and therefore analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement synapses as involved in Chen’s framework with the implementation contemplated by Kang, with a reasonable expectation of success, such that power consumption concerns can be better mitigated as discussed per Kang’s [0010] and [0082].
Regarding claim 10, Chen in view of Kang teaches the three-dimensional neuromorphic device of claim 9, as discussed above. The aforementioned references further teach the additional limitation wherein the plurality of PCM layers have different resistance values depending on having different phase change characteristics through different physical structures (see Chen’s discussion per [0037]-[0043] discussing how the layering and composition of different materials with differing conductance and resistance properties results in the realization of the synapse weighting for its neuromorphic architecture, with Kang as discussed per claim 9 providing a specific version of that layering). The motivation for combining the references is as discussed above in relation to claim 9.
Response to Arguments
12. Applicants’ arguments received 9/8/25 have been carefully considered but are respectfully not persuasive. The Examiner will provide feedback here:
As a first matter, in arguing that the cited prior art Chen does not teach the limitations for having “data storage structures, where each of the data storage structures have different physical structures formed from different thicknesses or different composition materials to provide the different weights for each of the data storage structures” (see first full paragraph on Applicants’ Reply, page 6), Applicants appear to disregard the entirety of the portion cited and rather appear to focus on an embodiment that corresponds to FIG. 9 and [0045]-[0046] only.
Applicants do not appear to address at all the portions actually cited to, e.g. Chen’s [0043]-[0044] as addressed in the prior Office Action on page 4 per the claim’s final limitation, and as reiterated here in the Final Office Action. For the benefit of the record, the Examiner will reproduce [0043] below:
“In embodiments, arrangements of the resistive material layers, the conductor elements, the contact vias and the conductor layer may be properly varied according to actual demands for obtaining synapse weights having expected weight values. For example, resistances of the unit resistors of different layers may be the same or different flexibly varied by controlling factors influencing effective resistance such as a shape, a gap distance, a contact area with the resistive material layer, or contact location with the resistive material layer of the corresponding pair of the conductor elements, and/or a size, a material, or a shape of the resistive material layers, or other factors. For example, the resistive material layers may have the same or different thickness. The resistive material layers may have the same or different material characteristic. The resistive material layer may comprise a semiconductor material such as a silicon material such as poly-silicon, or a carbon based material, or a metal nitride such as TiN, TaN, etc., or other suitable resistor materials. The resistive material layer may comprise a N-type semiconductor material or a P-type semiconductor material. For example, the resistive material layers may have the same or different doped characteristic. For example, the resistive material layers may have the same or different dopant impurity, and/or have the same or different dopant concentration. The dopant impurity may comprise an element of P, B, In, C, N and so on.”
In the Examiner’s view, [0044] following [0043] as reproduced above has the effect of teaching that the invention is not limited to [0043]’s embodiment, and that [0045]-[0046] discussing FIG. 9 for example is yet a different such embodiment. But even [0046] discusses that “synapse weights have different transistor arrangements so as to have different weight values.”
The Examiner does not read the discussion provided per [0045]-[0046] as argued by Applicants’ to break the reasoning provided by the Examiner per [0043]-[0044]. However, if Applicants are willing to specifically address why [0043]-[0044] do not map to the limitations for which they are asserted, then the Examiner is willing to reconsider.
These paragraphs, taken in full, appear to repeatedly teach that the elements, whether transistive or resistive, have variations to them, in terms of material, composition, and so forth, which result in their weighted variance.
Conclusion
13. The prior art made of record and not relied upon is considered pertinent to Applicants’ disclosure:
Non-Patent Literature “On-chip photonic synapse”
Non-Patent Literature “Nanoelectronic Programmable Synapses Based on Phase Change Materials for Brain-Inspired Computing”
14. THIS ACTION IS MADE FINAL. Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
15. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHOURJO DASGUPTA whose telephone number is (571)272-7207. The examiner can normally be reached M-F 8am-5pm CST.
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/SHOURJO DASGUPTA/Primary Examiner, Art Unit 2144