Prosecution Insights
Last updated: May 29, 2026
Application No. 17/623,501

FLEXIBLE DISPLAY PANEL AND FLEXIBLE ARRAY SUBSTRATE

Final Rejection §102
Filed
Jun 15, 2023
Priority
Dec 08, 2021 — CN 202111488237.5 +1 more
Examiner
SENGDARA, VONGSAVANH
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co. Ltd.
OA Round
2 (Final)
72%
Grant Probability
Favorable
3-4
OA Rounds
3m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
658 granted / 920 resolved
+3.5% vs TC avg
Strong +19% interview lift
Without
With
+18.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
44 currently pending
Career history
998
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
84.1%
+44.1% vs TC avg
§102
11.7%
-28.3% vs TC avg
§112
2.1%
-37.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 920 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant's arguments filed on 03/27/2026 have been fully considered but they are not persuasive. Cai discloses a barrier layer 81 (par [0004] - SiNx or SiOx – material as listed in applicant specification par [0079]) for water and oxygen protection, disposed between the thin film transistor layer and the flexible substrate. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-2 and 11-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CAI 20170069701. PNG media_image1.png 562 578 media_image1.png Greyscale Regarding claims 1 and 11, fig. 2 of Cai discloses a flexible display panel/array substrate, having a display area (light-emitting unit 7 area) and comprising: a flexible substrate 1; a thin film transistor layer (all elements in layer 82-84) disposed on the flexible substrate and in the display area and comprising a plurality of insulating layers (82-84) disposed in a stack, wherein first through-holes 91s penetrating at least one of the insulating layers are formed at a surface of the thin film transistor layer away from the flexible substrate; an organic planarization layer 5 (par [0050] - planarization layer 5 may be formed by the flexible organic material) covering one side of the thin film transistor layer away from the flexible substrate and filled in the first through-holes, and a barrier layer 81 (par [0004] - SiNx or SiOx – material as listed in applicant specification par [0079]) for water and oxygen protection, disposed between the thin film transistor layer and the flexible substrate; wherein the insulating layers comprise a gate insulating layer 82, an interlayer insulating layer 83, a source and drain electrode layer 33, and a passivation layer 84, the thin film transistor layer further comprises a semiconductor layer (necessary the case for TFT) and a gate electrode layer 31, the semiconductor layer is disposed on the flexible substrate, the gate electrode layer is disposed on one side of the semiconductor layer away or adjacent to the flexible substrate, the gate insulating layer is disposed between the gate electrode layer and the semiconductor layer, the source and drain electrode layer is disposed on one side of the gate electrode layer and the semiconductor layer away from the flexible substrate, the interlayer insulating layer is disposed between the source and drain electrode layer and the semiconductor layer, the passivation layer is disposed on one side of the source and drain electrode layer away from the flexible substrate, and the first through-holes penetrate at least a part of the passivation layer (see fig. 2). Regarding claims 2 and 12, par [0004] of Cai discloses wherein the thin film transistor layer comprises thin film transistors, and the first through-holes are defined adjacent to the thin film transistors (this is necessary the case as fig. 2 shows first through-holes and there are TFTs). Allowable Subject Matter Claims 5-10 and 15-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VONGSAVANH SENGDARA whose telephone number is (571)270-5770. The examiner can normally be reached 9AM-6PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, PURVIS A. Sue can be reached on (571 )272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VONGSAVANH SENGDARA/ Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Jun 15, 2023
Application Filed
Dec 29, 2025
Non-Final Rejection mailed — §102
Mar 27, 2026
Response Filed
Apr 22, 2026
Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12641879
ORGANIC LIGHT EMITTING DIODE DISPLAY
2y 6m to grant Granted May 26, 2026
Patent 12635586
SEMICONDUCTOR PACKAGE
2y 7m to grant Granted May 19, 2026
Patent 12615948
DISPLAY PANEL AND DISPLAY APPARATUS
2y 10m to grant Granted Apr 28, 2026
Patent 12615921
DISPLAY PANEL AND DISPLAY APPARATUS
2y 6m to grant Granted Apr 28, 2026
Patent 12607596
Nanostructure platform for cellular interfacing and corresponding manufacturing method
2y 10m to grant Granted Apr 21, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
72%
Grant Probability
90%
With Interview (+18.8%)
3y 3m (~3m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 920 resolved cases by this examiner. Grant probability derived from career allowance rate.

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