DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species III, which includes amended claims 1-2, 5-12, and 15-19, in the reply filed on 10/31/2025 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 11-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CAI 20170069701.
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Regarding claims 1 and 11, fig. 2 of Cai discloses a flexible display panel/array substrate, having a display area (light-emitting unit 7 area) and comprising:
a flexible substrate 1;
a thin film transistor layer (all elements in layer 8) disposed on the flexible substrate and in the display area and comprising a plurality of insulating layers 8 disposed in a stack,
wherein a surface of the thin film transistor layer away from the flexible substrate is provided with first through-holes (91s) penetrating at least one of the insulating layers; and
an organic planarization layer 5 (par [0050] - planarization layer 5 may be formed by the flexible organic material) covering one side of the thin film transistor layer away from the flexible substrate and filled in the first through-holes,
wherein the insulating layers comprise a gate insulating layer 82, an interlayer insulating layer 83, a source and drain electrode layer 33, and a passivation layer 84, the thin film transistor layer further comprises a semiconductor layer (necessary the case for TFT) and a gate electrode layer 31, the semiconductor layer is disposed on the flexible substrate, the gate electrode layer is disposed on one side of the semiconductor layer away or adjacent to the flexible substrate, the gate insulating layer is disposed between the gate electrode layer and the semiconductor layer, the source and drain electrode layer is disposed on one side of the gate electrode layer and the semiconductor layer away from the flexible substrate, the interlayer insulating layer is disposed between the source and drain electrode layer and the semiconductor layer, the passivation layer is disposed on one side of the source and drain electrode layer away from the flexible substrate, and the first through-holes penetrate at least a part of the passivation layer (see fig. 2).
Regarding claims 2 and 12, par [0004] of Cai discloses wherein the thin film transistor layer comprises thin film transistors, and the first through-holes are defined adjacent to the thin film transistors (this is necessary the case as fig. 2 shows first through-holes and there are TFTs).
Allowable Subject Matter
Claims 5-10 and 15-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/VONGSAVANH SENGDARA/ Primary Examiner, Art Unit 2893