Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the response to this Office action, the Office respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Office in prosecuting this application.
The Office has cited particular figures, elements, paragraphs and/or columns and line numbers in the references as applied to the claims for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, in preparing the responses, to fully consider each of the cited references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage disclosed by the Office.
Status of Claims
- Applicant' s Amendment filed December 10, 2025 is acknowledged.
- Claim(s) 1, 3, 6, 11, 13, 16 is/are amended
- Claim(s) 4-5, 14-15 is/are canceled
- Claim(s) 23, 24 is/are new
- Claim(s) 1-3, 6-13, 15-24 is/are pending in the application.
This action is FINAL
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 11-13, 21-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al, Chinese Patent Publication CN111724745A in view of Lee et al, U.S. Patent Publication No. 20100164847.
Consider claim 1, Wang teaches a display panel comprising a plurality of sub-pixels (see Wang paragraph 0066-0068 where display area of the organic light emitting diode display panel is provided with a plurality of pixel circuits, each pixel circuit is used for driving a sub-pixel to emit light), wherein each sub-pixel comprises a driving circuit, and wherein the driving circuit comprises:
a light-emitting device and a driving transistor, wherein the light-emitting device and the driving transistor are connected in series between a first power supply voltage and a second power supply voltage (see Wang figure 6, element T1, OLED, ELVDD, ELVSS);
a first transistor, wherein a gate electrode of the first transistor receives a first control signal, a drain electrode of the first transistor is electrically connected to a gate electrode of the driving transistor, and wherein the first transistor is an oxide film transistor (see Wang figure 6, element T8, Nscan, Q, T1 and paragraph 0095 where transistor T8 comprises an active layer with an oxide semiconductor);
a first capacitor, wherein one terminal of the first capacitor is electrically connected to the gate electrode of the driving transistor, and another terminal of the first capacitor is connected to the first power supply voltage (see Wang figure 6, element C, Q, T1, ELVDD);
a second transistor, wherein a gate electrode of the second transistor receives a second control signal, a source electrode of the second transistor is electrically connected to a source electrode of the first transistor, a drain electrode of the second transistor is connected to a drain electrode of the driving transistor (see Wang figure 6, element T3, Scan(n), T1, T8);
a third transistor, wherein a gate electrode of the third transistor receives a third control signal, a source electrode of the third transistor receives a first reset signal, and a drain electrode of the third transistor is electrically connected to the source electrode of the first transistor (see Wang figure 6, element T4, Vint, Scan(n-1), T1 and paragraph 0091 where initialization transistor T4 is used for transmitting the initialization signal to the first node Q through the conductive leakage-proof transistor T8 according to the first scanning signal, so as to initialize the potential of the first node Q); and
Wang is silent regarding a second capacitor, one terminal of the second capacitor is electrically connected to the gate electrode of the driving transistor, and another terminal of the second capacitor receives the second control signal, wherein the second capacitor is configured to reverse-couple an electrical potential of the drain electrode of the first transistor, so that the electrical potential of the drain electrode of the first transistor is consistent with an electrical potential of the gate electrode of the driving transistor.
In the same field of endeavor, Lee teaches a driving circuit further comprises a second capacitor (see Lee figure 2, element Ckb), one terminal of the second capacitor is electrically connected to the gate electrode of a driving transistor (see Lee figure 2, Qd), and another terminal of the second capacitor receives the second control signal (see Lee figure 2, element Scan) so as to reduce the dependence of current on Vth to make the circuit more tolerant to Vth variations and facilitate current through a light emitting element to become more stable (see Lee paragraph 0107).
One of ordinary skill in the art would have been motivated to have modified Wang with the teachings of Lee to have a second capacitor as recited so as to reduce the dependence of current on Vth to make the circuit more tolerant to Vth variations and facilitate current through a light emitting element to become more stable using known techniques with predictable results.
Incorporation of a second capacitor with Wang’s figure 6 would have resulted in the following circuit:
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Wang/Lee is silent regarding reverse-couple an electrical potential of the drain electrode of the first transistor, so that the electrical potential of the drain electrode of the first transistor is consistent with an electrical potential of the gate electrode of the driving transistor.
However as can be seen from Applicant’s figure 5, modification of Wang to incorporate a second capacitor as disclosed by Lee results in substantially the same circuit as Applicant’s figure 5
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Further paragraph 0112 of Wang discloses that Nscan would be as illustrated with respect to figure 3 of Wang
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The signals (Nscan, Scan(n), Scan(n-1)) provided to the transistors (T2, T8, T4, T3, T7) of Wang correspond to the signals (S1(n), S2(n), S1(n-1) ) provided to the transistors (T4, T1, T3, T2, T7) of Applicant’s figure 5 as illustrated in Applicant’s figure 6
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Both Wang as modified by Lee circuit and Applicant’s figure 5 circuit have same types of transistor, same circuit arrangement and same signals provided to the transistors. Therefore, one of ordinary skill would readily recognize that a same circuit receiving same signals to same types of elements will necessarily function the same. The fact that Applicant has recognized a benefit that was not explicitly recognize by the prior art does not render the disclosed structure of the prior art newly patentable based on the newly recognized benefit.
Consider claim 2, Wang as modified by Lee teaches all the limitations of claim 1 and further teaches wherein the driving circuit further comprises a fourth transistor, and wherein a gate electrode of the fourth transistor receives the second control signal, a source electrode of the fourth transistor receives a data signal, and a drain electrode of the fourth transistor is electrically connected to a source electrode of the driving transistor (see Wang figure 6, element T2, Scan(n), T1, Data).
Consider claim 3, Wang as modified by Lee teaches all the limitations of claim 2 and further teaches wherein the driving circuit further comprises a fifth transistor and a sixth transistor, and wherein a gate electrode of the fifth transistor and a gate electrode of the sixth transistor both receive a light-emitting control signal (see Wang figure 6, element T5, T6, EM), and wherein a source electrode of the fifth transistor receives the first power supply voltage, a drain electrode of the fifth transistor is electrically connected to the source electrode of the driving transistor (see Wang figure 6, element T5, ELVDD, T1), and wherein a drain electrode of the sixth transistor is electrically connected to an anode of the light-emitting device, and a source electrode of the sixth transistor is electrically connected to the drain electrode of the driving transistor (see Wang figure 6, element T6, OLED, T1).
Consider claim 11, Wang teaches a display panel comprising a plurality of sub-pixels (see Wang paragraph 0066-0068 where display area of the organic light emitting diode display panel is provided with a plurality of pixel circuits, each pixel circuit is used for driving a sub-pixel to emit light), wherein each sub-pixel comprises a driving circuit, and wherein the driving circuit comprises:
a light-emitting device and a driving transistor, wherein the light-emitting device and the driving transistor are connected in series between a first power supply voltage and a second power supply voltage (see Wang figure 6, element T1, OLED, ELVDD, ELVSS);
a first transistor, wherein a gate electrode of the first transistor receives a first control signal, a drain electrode of the first transistor is electrically connected to a gate electrode of the driving transistor, and wherein the first transistor is an oxide film transistor (see Wang figure 6, element T8, Nscan, Q, T1 and paragraph 0095 where transistor T8 comprises an active layer with an oxide semiconductor);
a first capacitor, wherein one terminal of the first capacitor is electrically connected to the gate electrode of the driving transistor, and another terminal of the first capacitor is connected to the first power supply voltage (see Wang figure 6, element C, Q, T1, ELVDD);
a second transistor, wherein a gate electrode of the second transistor receives a second control signal, a source electrode of the second transistor is electrically connected to a source electrode of the first transistor, a drain electrode of the second transistor is connected to a drain electrode of the driving transistor (see Wang figure 6, element T3, Scan(n), T1, T8);
a third transistor, wherein a gate electrode of the third transistor receives a third control signal, a source electrode of the third transistor receives a first reset signal, and a drain electrode of the third transistor is electrically connected to the source electrode of the first transistor (see Wang figure 6, element T4, Vint, Scan(n-1)), T1 and paragraph 0091 where initialization transistor T4 is used for transmitting the initialization signal to the first node Q through the conductive leakage-proof transistor T8 according to the first scanning signal, so as to initialize the potential of the first node Q); and
wherein the driving transistor, the second transistor, and the third transistor are low temperature polysilicon thin film transistors (see Wang paragraph 0069 where the driving transistor, the switch transistor, the compensation transistor, the initializing transistor, the first light emitting control transistor, the second light emitting control transistor and the reset transistor are P-type transistors with low-temperature polysilicon active layer).
Wang is silent regarding a second capacitor, one terminal of the second capacitor is electrically connected to the gate electrode of the driving transistor, and another terminal of the second capacitor receives the second control signal, wherein the second capacitor is configured to reverse-couple an electrical potential of the drain electrode of the first transistor, so that the electrical potential of the drain electrode of the first transistor is consistent with an electrical potential of the gate electrode of the driving transistor.
In the same field of endeavor, Lee teaches a driving circuit further comprises a second capacitor (see Lee figure 2, element Ckb), one terminal of the second capacitor is electrically connected to the gate electrode of a driving transistor (see Lee figure 2, Qd), and another terminal of the second capacitor receives the second control signal (see Lee figure 2, element Scan) so as to reduce the dependence of current on Vth to make the circuit more tolerant to Vth variations and facilitate current through a light emitting element to become more stable (see Lee paragraph 0107).
One of ordinary skill in the art would have been motivated to have modified Wang with the teachings of Lee to have a second capacitor as recited so as to reduce the dependence of current on Vth to make the circuit more tolerant to Vth variations and facilitate current through a light emitting element to become more stable using known techniques with predictable results.
Incorporation of a second capacitor with Wang’s figure 6 would have resulted in the following circuit:
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Wang/Lee is silent regarding reverse-couple an electrical potential of the drain electrode of the first transistor, so that the electrical potential of the drain electrode of the first transistor is consistent with an electrical potential of the gate electrode of the driving transistor.
However as can be seen from Applicant’s figure 5, modification of Wang to incorporate a second capacitor as disclosed by Lee results in substantially the same circuit as Applicant’s figure 5
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Further paragraph 0112 of Wang discloses that Nscan would be as illustrated with respect to figure 3 of Wang
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The signals (Nscan, Scan(n), Scan(n-1)) provided to the transistors (T2, T8, T4, T3, T7) of Wang correspond to the signals (S1(n), S2(n), S1(n-1) ) provided to the transistors (T4, T1, T3, T2, T7) of Applicant’s figure 5 as illustrated in Applicant’s figure 6
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Both Wang as modified by Lee circuit and Applicant’s figure 5 circuit have same types of transistor, same circuit arrangement and same signals provided to the transistors. Therefore, one of ordinary skill would readily recognize that a same circuit receiving same signals to same types of elements will necessarily function the same. The fact that Applicant has recognized a benefit that was not explicitly recognize by the prior art does not render the disclosed structure of the prior art newly patentable based on the newly recognized benefit.
Consider claim 21, Wang as modified by Lee teaches all the limitations of claim 3 and further teaches wherein the first control signal is set as the light-emitting control signal (see Wang figure 2, element T8, EM and paragraphs 0085, 0110 where figure 6 is substantially similar to the pixel circuit of the first embodiment.)
Claims 12-13, 22 recite similar claim limitations as claims 2-3, 21, and thus are rejected under similar rational as claims 2-3, 21 detail above.
Claim(s) 6-10, 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al, Chinese Patent Publication CN111724745A and Lee et al, U.S. Patent Publication No. 20100164847 in view of Dong, U.S. Patent Publication No. 20210376046.
Consider claim 6, Wang as modified by Lee teaches all the limitations of claim 1. Wang is silent regarding wherein driving circuits of the plurality of sub-pixels are arranged in an array, and wherein driving circuits of two adjacent columns of sub-pixels are arranged in a mirror-symmetrical structure.
In the same field of endeavor, Dong teaches wherein driving circuits of the plurality of sub-pixels are arranged in an array (see Dong figure 1, element P where a plurality of sub-pixels P are arranged in an array), and wherein driving circuits of two adjacent columns of sub-pixels are arranged in a mirror-symmetrical structure (see Dong figure 5 and paragraph 0147) so as to arrange rows and columns of sub-pixels with respect to plural data lines.
One of ordinary skill in the art would have been motivated to have modified Wang with the teaching of Dong to have the recited features so as to arrange rows and columns of sub-pixels with respect to plural data lines using known techniques with predictable results.
Consider claim 7, Wang as modified by Lee and Dong teaches all the limitations of claim 6. Wang is silent regarding wherein the display panel further comprises: a first conductive channel layer comprising a polysilicon active layer and a first electrode plate of the first capacitor; a first metal layer comprising a gate electrode of a polysilicon thin film transistor and a second electrode plate of the first capacitor; a second metal layer comprising a gate electrode of an oxide thin film transistor; a second conductive channel layer comprising an oxide semiconductor active layer; and a third metal layer comprising a source electrode of the polysilicon thin film transistor, a drain electrode of the polysilicon thin film transistor, a source electrode of the oxide thin film transistor, and a drain electrode of the oxide thin film transistor.
Wang does disclose both oxide thin film transistor and polysilicon thin film transistors (see Wang paragraph 0069 where second light emitting control transistor and the reset transistor are P-type transistors with low-temperature polysilicon active layer. The anti-leakage transistor is N-type transistor with oxide semiconductor active layer)
Dong teaches a first conductive channel layer comprising a polysilicon active layer and a first electrode plate of the first capacitor (see Dong figure 2, element 20, 30 and paragraph 0120 where semiconductor layer 20 may include active regions of the plurality of transistors. The first metal layer 30 may include the gate line G, the light emission control line EM, the reset signal line Reset, a first electrode C1 of the storage capacitor and gate electrodes of the plurality of transistors. And paragraph 0127 here semiconductor layer may be oxide or polysilicon); a first metal layer comprising a gate electrode of a polysilicon thin film transistor and a second electrode plate of the first capacitor (see Dong figure 2-3 and paragraphs 0120, 0127); a second metal layer comprising a gate electrode of an oxide thin film transistor (see Dong figure 2-3 and paragraphs 0120, 0127); a second conductive channel layer comprising an oxide semiconductor active layer (see Dong figure 2, element 20, 30 and paragraph 0120 where semiconductor layer 20 may include active regions of the plurality of transistors. The first metal layer 30 may include the gate line G, the light emission control line EM, the reset signal line Reset, a first electrode C1 of the storage capacitor and gate electrodes of the plurality of transistors. And paragraph 0127 here semiconductor layer may be oxide or polysilicon); and a third metal layer comprising a source electrode of the polysilicon thin film transistor, a drain electrode of the polysilicon thin film transistor, a source electrode of the oxide thin film transistor, and a drain electrode of the oxide thin film transistor (see Dong figure 2, element 20, 30 and paragraph 0120 where semiconductor layer 20 may include active regions of the plurality of transistors. The first metal layer 30 may include the gate line G, the light emission control line EM, the reset signal line Reset, a first electrode C1 of the storage capacitor and gate electrodes of the plurality of transistors. And paragraph 0127 here semiconductor layer may be oxide or polysilicon) so as to form the components of a pixel circuit such as transistors, data lines, gate lines and capacitors.
One of ordinary skill in the art would have been motivated to have modified Wang with the teachings of Dong to have various layers of metal and semiconductor layers so as to form the components of Wang’s pixel circuit including transistors, data lines, gate lines and capacitors using known techniques with predictable results.
Consider claim 8, Wang as modified by Lee and Dong teaches all the limitations of claim 7 and further teaches wherein the sub-pixels positioned in a same row are sequentially divided into a plurality of pairs of sub-pixels in a sequence, and wherein each pair of sub-pixels has a common boundary (see Dong figure 5 and paragraph 0147);
wherein in the second conductive channel layer, the active layers of the first transistors in each pair of sub-pixels are arranged opposite to and close to the common boundary of each pair of sub-pixels (see Dong figure 3), and
wherein the active layers of the first transistors of each pair of sub-pixels are parallel to the common boundary of each pair of sub-pixels (see Dong figure 5 where in view of arrangements illustrated in figure 3, mirroring the circuits results in the recited features).
Consider claim 9, Wang as modified by Lee and Dong teaches all the limitations of claim 7 and further teaches wherein the first metal layer further comprises a first electrode plate of the second capacitor, and wherein the second conductive channel layer further comprises a second electrode plate of the second capacitor (see Dong figure 2, element 20, 30 and paragraph 0120 where semiconductor layer 20 may include active regions of the plurality of transistors. The first metal layer 30 may include the gate line G, the light emission control line EM, the reset signal line Reset, a first electrode C1 of the storage capacitor and gate electrodes of the plurality of transistors. And paragraph 0127 here semiconductor layer may be oxide or polysilicon and Lee figure 2, element Ckb). Lee is silent regarding layers for forming pixel circuits. Examiner notes that one of ordinary skill would have found the teachings of Dong to have various layers forming a pixel circuit components to fairly teach or suggested having additional layers to form a second capacitor incorporated with the teachings of Wang so as to form various pixel circuit components using known techniques with predictable results.
Consider claim 10, Wang as modified by Lee and Dong teaches all the limitations of claim 9 and further teaches wherein the sub-pixels positioned in a same row are sequentially divided into a plurality of pairs of sub-pixels in a sequence, and wherein each pair of sub-pixels has a common boundary (see Dong figure 5 and paragraph 0147);
wherein in the second conductive channel layer, the second electrode plate of the second capacitor and the active layer of the first transistor are positioned in a same axial direction, and wherein the second capacitors in each pair of sub-pixels are oppositely and close to the common boundary of each pair of sub-pixels (see Dong figure 5 where in view of arrangements illustrated in figure 3, mirroring the circuits results in the recited features).
Claims 16-20 recite similar claim limitations as claims 6-10, and thus are rejected under similar rational as claims 6-10 detail above.
Claim(s) 23-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al, Chinese Patent Publication CN111724745A and Lee et al, U.S. Patent Publication No. 20100164847 in view of Kawachi, U.S. Patent Publication No. 20210383754.
Consider claim 23, Wang as modified by Lee teaches all the limitations of claim 1 and further teaches wherein the driving circuit further comprises a seventh transistor, and wherein a gate electrode of the seventh transistor receives the second control signal, a source electrode of the seventh transistor receives a
Wang is silent regarding a second reset signal. In a related field of endeavor, Kawachi teaches a potential for an OLED anode reset can be different from a potential to reset a gate of a driving transistor (see Kawachi paragraph 0044 notice that Kawachi pixel in figures 5, 10 illustrate M7, M5 as being connected to a same reset line VRST).
One of ordinary skill would have been motivated to have modified Kawachi to have different reset potential from a reset potential for resetting a gate of a driving transistor so as to reset an anode of an OLED as disclosed by Kawachi using known techniques with predictable results.
Claim 24 recite similar claim limitations as claim 23, and thus are rejected under similar rational as claim 23 detail above.
Response to Arguments
Applicant's arguments filed December 10, 2025 have been fully considered but they are not persuasive.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “internal control signal”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Examiner further notes that Applicant’s original specification does not appear to discuss “internal control signal”. It is unclear how to interpret the metes and bounds of Applicant’s argued “internal control signal” because Applicant’s specification does not define “internal control signal”.
Regarding Applicant’s assertion that Lee does not include an oxide film transistor at all, Examiner respectfully directs Applicant’s attention to paragraph 0086 where “the driving transistor Qd are p-channel electric field effect transistors (PMOS). These may for example be thin film transistors (TFT), and they may include polysilicon or amorphous silicon”; paragraph 0110 where “sixth switching transistor Qs6 is an n-channel electric field effect transistor (NMOS) rather than a PMOS transistor” and paragraph 0118 where “driving transistor Qd are p-channel electric field effect transistors (PMOS), and the sixth switching transistor Qs6 is an n-channel electric field effect transistor (NMOS). The electric field effect transistors can be, for example, thin film transistors (TFT), and may include polysilicon or amorphous silicon”. It is well known that PMOS and NMOS are the two types of metal-oxide-semiconductor field-effect transistors (MOSFETs). Therefore, Lee clearly teaches an oxide film transistor. Examiner further notes that Wang clearly teaches an oxide semiconductor transistor (see Wang figure 6, element T8, Nscan, Q, T1 and paragraph 0095 where transistor T8 comprises an active layer with an oxide semiconductor).
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
In response to applicant's argument that capacitor Ckb of Lee is used for forward coupling, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
As discussed in the rejection above, incorporation of Lee’s teaching of “a second capacitor, one terminal of the second capacitor is electrically connected to the gate electrode of the driving transistor, and another terminal of the second capacitor receives the second control signal” with Wang’s figure 6 would have resulted in the following circuit:
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Wang/Lee is silent regarding reverse-couple an electrical potential of the drain electrode of the first transistor, so that the electrical potential of the drain electrode of the first transistor is consistent with an electrical potential of the gate electrode of the driving transistor.
However as can be seen from Applicant’s figure 5, modification of Wang to incorporate a second capacitor as disclosed by Lee results in substantially the same circuit as Applicant’s figure 5
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Further paragraph 0112 of Wang discloses that Nscan would be as illustrated with respect to figure 3 of Wang
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The signals (Nscan, Scan(n), Scan(n-1)) provided to the transistors (T2, T8, T4, T3, T7) of Wang correspond to the signals (S1(n), S2(n), S1(n-1) ) provided to the transistors (T4, T1, T3, T2, T7) of Applicant’s figure 5 as illustrated in Applicant’s figure 6
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Both Wang as modified by Lee circuit and Applicant’s figure 5 circuit have same types of transistor, same circuit arrangement and same signals provided to the transistors. Therefore, one of ordinary skill would readily recognize that a same circuit receiving same signals to same types of elements will necessarily function the same. The fact that Applicant has recognized a benefit that was not explicitly recognize by the prior art does not render the disclosed structure of the prior art newly patentable based on the newly recognized benefit.
Examiner is unpersuaded by Applicant’s arguments.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Zhou et al, U.S. Patent Publication No. 20220302238 (figure 4, paragraph 0125), You, U.S. Patent Publication No. 20220328592 (figure 2, paragraph 0014).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dorothy H Harris whose telephone number is (571)270-7539. The examiner can normally be reached Monday - Friday 8am - 4pm.
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/Dorothy Harris/Primary Examiner, Art Unit 2625