DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (U.S. PG Pub 2012/0038683) in view of Kim et al. (U.S. PG Pub 2018/0293939).
Regarding Claim 16, Park et al. teach a pixel circuit (Figure 2, Element 140. Paragraph 50), comprising: a driving circuit (Figure 2, Element M1. Paragraph 53), a data writing circuit (Figure 2, Element M2. Paragraph 55), a first thin film transistor (Figure 2, Element M5. Paragraph 58), a second thin film transistor (Figure 2, Element M4. Paragraph 57), and a blocking circuit (Figure 2, Element M3. Paragraph 56);
wherein a first terminal of the driving circuit (Figure 2, Element M1. Paragraph 53) is connected to a first terminal of the data writing circuit (Figure 2, Element M2. Paragraph 55), a second terminal of the driving circuit (Figure 2, Element M1. Paragraph 53) is respectively connected to a first terminal of the blocking circuit (Figure 2, Element M3. Paragraph 56) and a light-emitting device (Figure 2, Element OLED. Paragraphs 50 - 52), and a third terminal (Figure 2, Element N1. Paragraph 53) of the driving circuit (Figure 2, Element M1. Paragraph 53) is connected to a drain of the first thin film transistor (Figure 2, Element M5. Paragraph 58);
wherein a second terminal of the data writing circuit (Figure 2, Element M2. Paragraph 55) is connected to a first scan line of a current row (Figure 2, Element Sn. Paragraph 55), and a third terminal of the data writing circuit (Figure 2, Element M2. Paragraph 55) is connected to a data line (Figure 2, Element Dm. Paragraph 55);
wherein a gate of the first thin film transistor (Figure 2, Element M5. Paragraph 58) is connected to a second scan line of a current row (Figure 5, Element /En. Paragraph 58), and a source of the first thin film transistor (Figure 2, Element M5. Paragraph 58) is respectively connected to a drain of the second thin film transistor (Figure 2, Element M4. Paragraph 57) and a second terminal of the blocking circuit (Figure 2, Element M3. Paragraph 56);
wherein a gate of the second thin film transistor (Figure 2, Element M4. Paragraph 57) is connected to the first scan line of a previous row (Figure 5, Element Sn-1. Paragraph 57), and a source of the second thin film transistor (Figure 2, Element M4. Paragraph 57) is connected to receive a second initial voltage signal (Figure 5, Element Vint. Paragraph 57);
wherein a third terminal of the blocking circuit (Figure 2, Element M3. Paragraph 56) is connected to the first scan line of the current row (Figure 2, Element Sn. Paragraph 55); and
wherein in a stage of resetting a potential of the third terminal (Figure 2, Element N1. Paragraph 53) of the driving circuit (Figure 2, Element M1. Paragraph 53), the first scan line of the previous row (Figure 5, Element Sn-1. Paragraph 57) is configured to turn on (Paragraph 63) the second thin film transistor (Figure 2, Element M4. Paragraph 57), the second scan line of the current row (Figure 5, Element /En. Paragraph 58) is configured to turn on (Paragraph 64) the first thin film transistor (Figure 2, Element M5. Paragraph 58), and the first scan line of the current row (Figure 2, Element Sn. Paragraph 55) is configured to turn off (Paragraphs 65 – 66) the blocking circuit (Figure 2, Element M3. Paragraph 56) such that the potential of the third terminal (Figure 2, Element N1. Paragraph 53) of the driving circuit (Figure 2, Element M1. Paragraph 53) is reset to (Paragraph 64) the second initial voltage signal (Figure 5, Element Vint. Paragraph 57) derived from the source of the second thin film transistor (Figure 2, Element M4. Paragraph 57).
Park et al. is silent with regards to wherein the first scan line of the current row and the first scan line of the previous row are configured to transmit a first scan signal, the second scan line of the current row is configured to transmit a second scan signal, and the first scan signal has a higher signal frequency than the second scan signal.
Kim et al. teach wherein the first scan line of the current row (Figure 13, Element S1i. Paragraph 154) and the first scan line of the previous row (Figure 13, Element S1i. Paragraph 154) are configured to transmit a first scan signal (Figure 13, Element S1i. Paragraph 154), the second scan line of the current row (Figure 13, Element S2i. Paragraph 161) is configured to transmit a second scan signal (Figure 13, Element S2i. Paragraph 161), and the first scan signal (Figure 13, Element S1i. Paragraph 154) has a higher signal frequency (Figures 6 and 13. Paragraphs 114 and 166) than the second scan signal (Figure 13, Element S2i. Paragraph 161).
It would have been obvious to a person of ordinary skill in the art to modify the teachings of the pixel circuit of Cho with the driving frequencies of Kim et al. The motivation to modify the teachings of Cho with the teachings of Kim et al. is to improve image quality, as taught by Kim et al. (Paragraph 6).
Claims 1 and 3 – 12 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (U.S. PG Pub 2012/0038683) in view of Tseng et al. (U.S. PG Pub 2018/0151115) in view of Kim et al. (U.S. PG Pub 2018/0293939).
Regarding Claim 1, Park et al. teach a pixel circuit (Figure 2, Element 140. Paragraph 50), comprising: a driving circuit (Figure 2, Element M1. Paragraph 53), a first light-emitting control circuit (Figure 2, Element M7. Paragraph 60), a second light-emitting control circuit (Figure 2, Element M6. Paragraph 59), a data writing circuit (Figure 2, Element M2. Paragraph 55), a reset circuit (Figure 5, Element M8. Paragraphs 76 - 79), a storage circuit (Figure 2, Element Cst. Paragraph 61), a first thin film transistor (Figure 2, Element M5. Paragraph 58), and a second thin film transistor (Figure 2, Element M4. Paragraph 57);
wherein a first terminal of the driving circuit (Figure 2, Element M1. Paragraph 53) is respectively connected to a first terminal of the first light-emitting control circuit (Figure 2, Element M7. Paragraph 60) and the first terminal of the data writing circuit (Figure 2, Element M2. Paragraph 55), a second terminal of the driving circuit (Figure 2, Element M1. Paragraph 53) is respectively connected to a source (Figure 2. Park et al. shows the connection through transistor M3) of the first thin film transistor (Figure 2, Element M5. Paragraph 58), a drain (Figure 2. Park et al. shows the connection through transistor M3) of the second thin film transistor (Figure 2, Element M4. Paragraph 57) and a first terminal of the second light-emitting control circuit (Figure 2, Element M6. Paragraph 59), and a third terminal (Figure 2, Element N1. Paragraph 53) of the driving circuit (Figure 2, Element M1. Paragraph 53) is respectively connected to a drain of the first thin film transistor (Figure 2, Element M5. Paragraph 58) and a first terminal of the storage circuit (Figure 2, Element Cst. Paragraph 61);
wherein a second terminal of the first light-emitting control circuit (Figure 2, Element M7. Paragraph 60) is respectively connected to a second terminal of the storage circuit (Figure 2, Element Cst. Paragraph 61) and a voltage source (Figure 2, Element ELVDD. Paragraph 60), a third terminal of the first light-emitting control circuit (Figure 2, Element M7. Paragraph 60) is connected to receive a light-emitting signal (Figure 2, Element En. Paragraph 60), a second terminal of the second light-emitting control circuit (Figure 2, Element M6. Paragraph 59) is connected to receive the light-emitting signal (Figure 2, Element En. Paragraph 60), and a third terminal of the second light-emitting control circuit (Figure 2, Element M6. Paragraph 59) is connected to a first terminal (Figure 5. Park et al. shows the connection through transistors M6 and M3) of the reset circuit (Figure 5, Element M8. Paragraphs 76 - 79) and is configured to connect to a light-emitting device (Figure 2, Element OLED. Paragraphs 50 - 52);
wherein a second terminal of the data writing circuit (Figure 2, Element M2. Paragraph 55) is connected to a first scan line of a current row (Figure 2, Element Sn. Paragraph 55), a third terminal of the data writing circuit (Figure 2, Element M2. Paragraph 55) is connected to a data line (Figure 2, Element Dm. Paragraph 55), and a third terminal of the reset circuit (Figure 5, Element M8. Paragraphs 76 - 79) is connected to receive a first initial voltage signal (Figure 5, Element Vref. Paragraph 79); and
wherein a gate of the first thin film transistor (Figure 2, Element M5. Paragraph 58) is connected to a second scan line of a current row (Figure 5, Element /En. Paragraph 58), a gate of the second thin film transistor (Figure 2, Element M4. Paragraph 57) is connected to the first scan line of a previous row (Figure 5, Element Sn-1. Paragraph 57), and a source of the second thin film transistor (Figure 2, Element M4. Paragraph 57) is connected to receive a second initial voltage signal (Figure 5, Element Vint. Paragraph 57);
wherein the pixel circuit (Figure 2, Element 140. Paragraph 50) further comprises a blocking circuit (Figure 2, Element M3. Paragraph 56);
wherein a first terminal of the blocking circuit (Figure 2, Element M3. Paragraph 56) is connected to the second terminal of the driving circuit (Figure 2, Element M1. Paragraph 53) and the first terminal of the second light-emitting control circuit (Figure 2, Element M6. Paragraph 59), a second terminal of the blocking circuit (Figure 2, Element M3. Paragraph 56) is connected to the source of the first thin film transistor (Figure 2, Element M5. Paragraph 58) and the drain of the second thin film transistor (Figure 2, Element M4. Paragraph 57), and a third terminal of the blocking circuit (Figure 2, Element M3. Paragraph 56) is connected to the first scan line of a current row (Figure 2, Element Sn. Paragraph 55);
wherein in a stage of (Figure 3, Element not labeled, but is the timing when the Signal Line Sn – 1 is low. Paragraph 64)
resetting a potential of the third terminal (Figure 2, Element N1. Paragraph 53) of the driving circuit (Figure 2, Element M1. Paragraph 53), the first scan line of the previous row (Figure 5, Element Sn-1. Paragraph 57) and the second scan line of the current row (Figure 5, Element /En. Paragraph 58) are configured to transmit low-level signals (Paragraphs 63 – 64), and the first scan line of the current row (Figure 2, Element Sn. Paragraph 55) is configured to transmit a high-level signal such that the first thin film transistor (Figure 2, Element M5. Paragraph 58) and the second thin film transistor (Figure 2, Element M4. Paragraph 57) are simultaneously turned on (Paragraphs 63 – 64), the blocking circuit (Figure 2, Element M3. Paragraph 56) is turned off (Paragraphs 65 – 66), and the potential of the third terminal (Figure 2, Element N1. Paragraph 53) of the driving circuit (Figure 2, Element M1. Paragraph 53) is reset to the second initial voltage signal (Figure 5, Element Vint. Paragraph 57).
Park et al. is silent with regards to a second terminal of the reset circuit is connected to the first scan line of a current row, and wherein the first scan line of the current row and the first scan line of the previous row are configured to transmit a first scan signal, the second scan line of the current row is configured to transmit a second scan signal, and the first scan signal has a higher signal frequency than the second scan signal.
Tseng et al. teach a second terminal of the reset circuit (Figure 3, Element M8. Paragraph 55) is connected to the first scan line of a current row (Figure 3, Element S1. Paragraph 55).
It would have been obvious to a person of ordinary skill in the art to modify the pixel circuit of Park et al. with the reset circuit connections of Tseng et al. The motivation to modify the teachings of Cho with the teachings of Tseng et al. is to reduce the number of signal ports and wiring space, as taught by Tseng et al. (Paragraph 55).
Kim et al. teach wherein the first scan line of the current row (Figure 13, Element S1i. Paragraph 154) and the first scan line of the previous row (Figure 13, Element S1i. Paragraph 154) are configured to transmit a first scan signal (Figure 13, Element S1i. Paragraph 154), the second scan line of the current row (Figure 13, Element S2i. Paragraph 161) is configured to transmit a second scan signal (Figure 13, Element S2i. Paragraph 161), and the first scan signal (Figure 13, Element S1i. Paragraph 154) has a higher signal frequency (Figures 6 and 13. Paragraphs 114 and 166) than the second scan signal (Figure 13, Element S2i. Paragraph 161).
It would have been obvious to a person of ordinary skill in the art to modify the teachings of the pixel circuit of Cho and the reset circuit connections of Tseng et al. with the driving frequencies of Kim et al. The motivation to modify the teachings of Cho and Tseng et al. with the teachings of Kim et al. is to improve image quality, as taught by Kim et al. (Paragraph 6).
Regarding Claim 3, Park et al. in view of Tseng et al. teach the pixel circuit (Figure 2, Element 140. Paragraph 50) according to claim 1 (See Above), wherein the blocking circuit (Figure 2, Element M3. Paragraph 56) comprises a third thin film transistor (Figure 2, Element M3. Paragraph 56);
wherein a source of the third thin film transistor (Figure 2, Element M3. Paragraph 56) is respectively connected to the second terminal of the driving circuit (Figure 2, Element M1. Paragraph 53) and the first terminal of the second light-emitting control circuit (Figure 2, Element M6. Paragraph 59), a drain of the third thin film transistor (Figure 2, Element M3. Paragraph 56) is respectively connected to the source of the first thin film transistor (Figure 2, Element M5. Paragraph 58) and the drain of the second thin film transistor (Figure 2, Element M4. Paragraph 57), and a gate of the third thin film transistor (Figure 2, Element M3. Paragraph 56) is connected to the first scan line of a current row (Figure 2, Element Sn. Paragraph 55).
Regarding Claim 4, Park et al. in view of Tseng et al. teach the pixel circuit (Figure 2, Element 140. Paragraph 50) according to claim 1 (See Above), wherein the first thin film transistor (Figure 2, Element M5. Paragraph 58) is a single gate thin film transistor (Figure 2. Paragraph 58) or a double gate thin film transistor (Figure 4. Paragraph 74), and the second thin film transistor (Figure 2, Element M4. Paragraph 57) is a single gate thin film transistor (Figure 2. Paragraph 57) or a double gate thin film transistor.
Regarding Claim 5, Park et al. in view of Tseng et al. teach the pixel circuit (Figure 2, Element 140. Paragraph 50) according to claim 1 (See Above), wherein a third terminal of the reset circuit (Figure 5, Element M8. Paragraphs 76 - 79) is connected to the source of the second thin film transistor (Figure 2, Element M4. Paragraph 57).
Tseng et al. teach and the first initial voltage signal (Figure 3, Element Vinit. Paragraph 51) and the second initial voltage signal (Figure 3, Element Vinit. Paragraph 51) are a same signal (Seen in Figure 3).
It would have been obvious to a person of ordinary skill in the art to modify the pixel circuit of Park et al. with the reset circuit connections of Tseng et al. The motivation to modify the teachings of Cho with the teachings of Tseng et al. is to reduce the number of signal ports and wiring space, as taught by Tseng et al. (Paragraph 55).
Regarding Claim 6, Park et al. in view of Tseng et al. teach the pixel circuit (Figure 2, Element 140. Paragraph 50) according to claim 1 (See Above), wherein the driving circuit (Figure 2, Element M1. Paragraph 53) includes a fourth thin film transistor (Figure 2, Element M1. Paragraph 53);
wherein a source of the fourth thin film transistor (Figure 2, Element M1. Paragraph 53) is respectively connected to the first terminal of the first light-emitting control circuit (Figure 2, Element M7. Paragraph 60) and the first terminal of the data writing circuit (Figure 2, Element M2. Paragraph 55), a drain of the fourth thin film transistor (Figure 2, Element M1. Paragraph 53) is respectively connected to (Figure 2. Park et al. shows the connection through transistor M3) the source of the first thin film transistor (Figure 2, Element M5. Paragraph 58), the drain of the second thin film transistor (Figure 2, Element M4. Paragraph 57) and the first terminal of the second light-emitting control circuit (Figure 2, Element M6. Paragraph 59), and a gate of the fourth thin film transistor (Figure 2, Element M1. Paragraph 53) is respectively connected to the drain of the first thin film transistor (Figure 2, Element M5. Paragraph 58) and the first terminal of the storage circuit (Figure 2, Element Cst. Paragraph 61).
Regarding Claim 7, Park et al. in view of Tseng et al. teach the pixel circuit (Figure 2, Element 140. Paragraph 50) according to claim 6 (See Above), wherein the first light-emitting control circuit (Figure 2, Element M7. Paragraph 60) includes a fifth thin film transistor (Figure 2, Element M7. Paragraph 60);
wherein a source of the fifth thin film transistor (Figure 2, Element M7. Paragraph 60) is respectively connected to the second terminal of the storage circuit (Figure 2, Element Cst. Paragraph 61) and the voltage source (Figure 2, Element ELVDD. Paragraph 60), a drain of the fifth thin film transistor (Figure 2, Element M7. Paragraph 60) is connected to the source of the fourth thin film transistor (Figure 2, Element M1. Paragraph 53), and a gate of the fifth thin film transistor (Figure 2, Element M7. Paragraph 60) is connected to receive the light-emitting signal (Figure 2, Element En. Paragraph 60).
Regarding Claim 8, Park et al. in view of Tseng et al. teach the pixel circuit (Figure 2, Element 140. Paragraph 50) according to claim 7 (See Above), wherein the second light-emitting control circuit (Figure 2, Element M6. Paragraph 59) includes a sixth thin film transistor (Figure 2, Element M6. Paragraph 59);
wherein a source of the sixth thin film transistor (Figure 2, Element M6. Paragraph 59) is respectively connected to (Figure 2. Park et al. shows the connection through transistor M3) the source of the first thin film transistor (Figure 2, Element M5. Paragraph 58), the drain of the second thin film transistor (Figure 2, Element M4. Paragraph 57) and the drain of the fourth thin film transistor (Figure 2, Element M1. Paragraph 53), a gate of the sixth thin film transistor (Figure 2, Element M6. Paragraph 59) is connected to receive the light-emitting signal (Figure 2, Element En. Paragraph 60), a drain of the sixth thin film transistor (Figure 2, Element M6. Paragraph 59) is connected to (Figure 2. Park et al. shows the connection through transistor M3) the first terminal of the reset circuit (Figure 5, Element M8. Paragraphs 76 - 79) and is configured to connect to the light-emitting device (Figure 2, Element OLED. Paragraphs 50 - 52).
Regarding Claim 9, Park et al. in view of Tseng et al. teach the pixel circuit (Figure 2, Element 140. Paragraph 50) according to claim 8 (See Above), wherein the data writing circuit (Figure 2, Element M2. Paragraph 55) includes a seventh thin film transistor (Figure 2, Element M2. Paragraph 55);
wherein a drain of the seventh thin film transistor (Figure 2, Element M2. Paragraph 55) is respectively connected to the source of the fourth thin film transistor (Figure 2, Element M1. Paragraph 53) and the drain of the fifth thin film transistor (Figure 2, Element M7. Paragraph 60), a gate of the seventh thin film transistor (Figure 2, Element M2. Paragraph 55) is connected to the first scan line of a current row (Figure 2, Element Sn. Paragraph 55), and a source of the seventh thin film transistor (Figure 2, Element M2. Paragraph 55) is connected to the data line (Figure 2, Element Dm. Paragraph 55).
Regarding Claim 10, Park et al. in view of Tseng et al. teach the pixel circuit (Figure 2, Element 140. Paragraph 50) according to claim 9 (See Above), wherein the reset circuit (Figure 5, Element M8. Paragraphs 76 - 79) includes an eighth thin film transistor (Figure 5, Element M8. Paragraphs 76 - 79);
wherein a drain of the eighth thin film transistor (Figure 5, Element M8. Paragraphs 76 - 79) is respectively connected to (Figure 2. Park et al. shows the connection through transistor M3) the drain of the sixth thin film transistor (Figure 2, Element M6. Paragraph 59), and a source of the eighth thin film transistor (Figure 5, Element M8. Paragraphs 76 - 79) is connected to receive the first initial voltage signal (Figure 5, Element Vref. Paragraph 79).
Park et al. is silent with regards to a gate of the eighth thin film transistor is connected to the first scan line of a current row.
Tseng et al. teach a drain of the eighth thin film transistor (Figure 3, Element M8. Paragraph 55) is respectively connected to the drain of the sixth thin film transistor (Figure 3, Element M6. Paragraphs 36 – 37), a gate of the eighth thin film transistor (Figure 3, Element M8. Paragraph 55) is connected to the first scan line of a current row (Figure 3, Element S1. Paragraph 55).
It would have been obvious to a person of ordinary skill in the art to modify the pixel circuit of Park et al. with the reset circuit connections of Tseng et al. The motivation to modify the teachings of Cho with the teachings of Tseng et al. is to reduce the number of signal ports and wiring space, as taught by Tseng et al. (Paragraph 55).
Regarding Claim 11, Park et al. in view of Tseng et al. teach the pixel circuit (Figure 2, Element 140. Paragraph 50) according to claim 10 (See Above), wherein the storage circuit (Figure 2, Element Cst. Paragraph 61) includes a capacitor (Figure 2, Element Cst. Paragraph 61);
wherein a first terminal of the capacitor (Figure 2, Element Cst. Paragraph 61) is connected to the gate of the fourth thin film transistor (Figure 2, Element M1. Paragraph 53), and a second terminal of the capacitor (Figure 2, Element Cst. Paragraph 61) is connected to the source of the fifth thin film transistor (Figure 2, Element M7. Paragraph 60).
Regarding Claim 12, Park et al. teach a display panel (Figure 1, Element 130. Paragraph 44), comprising a light-emitting layer (Figure 1, Element not labeled, but is the layer where OLED emit light. Paragraph 51) and a driving layer (Figure 1, Element not labeled, but is the layer containing the pixel circuit. Paragraph 48), wherein the driving layer (Figure 1, Element not labeled, but is the layer containing the pixel circuit. Paragraph 48) is configured to drive the light-emitting layer (Figure 1, Element not labeled, but is the layer where OLED emit light. Paragraph 51) to emit light;
wherein the driving layer (Figure 1, Element not labeled, but is the layer containing the pixel circuit. Paragraph 48) comprises a pixel circuit (Figure 2, Element 140. Paragraph 50);
wherein the pixel circuit (Figure 2, Element 140. Paragraph 50) comprises a driving circuit (Figure 2, Element M1. Paragraph 53), a first light-emitting control circuit (Figure 2, Element M7. Paragraph 60), a second light-emitting control circuit (Figure 2, Element M6. Paragraph 59), a data writing circuit (Figure 2, Element M2. Paragraph 55), a reset circuit (Figure 5, Element M8. Paragraphs 76 - 79), a storage circuit (Figure 2, Element Cst. Paragraph 61), a first thin film transistor (Figure 2, Element M5. Paragraph 58), and a second thin film transistor (Figure 2, Element M4. Paragraph 57);
wherein a first terminal of the driving circuit (Figure 2, Element M1. Paragraph 53) is respectively connected to a first terminal of the first light-emitting control circuit (Figure 2, Element M7. Paragraph 60) and the first terminal of the data writing circuit (Figure 2, Element M2. Paragraph 55), a second terminal of the driving circuit (Figure 2, Element M1. Paragraph 53) is respectively connected to a source (Figure 2. Park et al. shows the connection through transistor M3) of the first thin film transistor (Figure 2, Element M5. Paragraph 58), a drain (Figure 2. Park et al. shows the connection through transistor M3) of the second thin film transistor (Figure 2, Element M4. Paragraph 57) and a first terminal of the second light-emitting control circuit (Figure 2, Element M6. Paragraph 59), and a third terminal (Figure 2, Element N1. Paragraph 53) of the driving circuit (Figure 2, Element M1. Paragraph 53) is respectively connected to a drain of the first thin film transistor (Figure 2, Element M5. Paragraph 58) and a first terminal of the storage circuit (Figure 2, Element Cst. Paragraph 61);
wherein a second terminal of the first light-emitting control circuit (Figure 2, Element M7. Paragraph 60) is respectively connected to a second terminal of the storage circuit (Figure 2, Element Cst. Paragraph 61) and a voltage source (Figure 2, Element ELVDD. Paragraph 60), a third terminal of the first light-emitting control circuit (Figure 2, Element M7. Paragraph 60) is connected to receive a light-emitting signal (Figure 2, Element En. Paragraph 60), a second terminal of the second light-emitting control circuit (Figure 2, Element M6. Paragraph 59) is connected to receive the light-emitting signal (Figure 2, Element En. Paragraph 60), and a third terminal of the second light-emitting control circuit (Figure 2, Element M6. Paragraph 59) is connected to (Figure 2. Park et al. shows the connection through transistor M3) a first terminal of the reset circuit (Figure 5, Element M8. Paragraphs 76 - 79) and is configured to connect to a light-emitting device (Figure 2, Element OLED. Paragraphs 50 - 52);
wherein a second terminal of the data writing circuit (Figure 2, Element M2. Paragraph 55) is connected to a first scan line of a current row (Figure 2, Element Sn. Paragraph 55), a third terminal of the data writing circuit (Figure 2, Element M2. Paragraph 55) is connected to a data line (Figure 2, Element Dm. Paragraph 55), and a third terminal of the reset circuit (Figure 5, Element M8. Paragraphs 76 - 79) is connected to receive a first initial voltage signal (Figure 5, Element Vref. Paragraph 79); and
wherein a gate of the first thin film transistor (Figure 2, Element M5. Paragraph 58) is connected to a second scan line of a current row (Figure 5, Element /En. Paragraph 58), a gate of the second thin film transistor (Figure 2, Element M4. Paragraph 57) is connected to the first scan line of a previous row (Figure 5, Element Sn-1. Paragraph 57), and a source of the second thin film transistor (Figure 2, Element M4. Paragraph 57) is connected to receive a second initial voltage signal (Figure 5, Element Vint. Paragraph 57);
wherein the pixel circuit (Figure 2, Element 140. Paragraph 50) further comprises a blocking circuit (Figure 2, Element M3. Paragraph 56);
wherein a first terminal of the blocking circuit (Figure 2, Element M3. Paragraph 56) is connected to the second terminal of the driving circuit (Figure 2, Element M1. Paragraph 53) and the first terminal of the second light-emitting control circuit (Figure 2, Element M6. Paragraph 59), a second terminal of the blocking circuit (Figure 2, Element M3. Paragraph 56) is connected to the source of the first thin film transistor (Figure 2, Element M5. Paragraph 58) and the drain of the second thin film transistor (Figure 2, Element M4. Paragraph 57), and a third terminal of the blocking circuit (Figure 2, Element M3. Paragraph 56) is connected to the first scan line of a current row (Figure 2, Element Sn. Paragraph 55);
wherein in a stage of resetting a potential of the third terminal (Figure 2, Element N1. Paragraph 53) of the driving circuit (Figure 2, Element M1. Paragraph 53), the first scan line of the previous row (Figure 5, Element Sn-1. Paragraph 57) is configured to turn on (Paragraph 63) the second thin film transistor (Figure 2, Element M4. Paragraph 57), the second scan line of the current row (Figure 5, Element /En. Paragraph 58) is configured to turn on (Paragraph 64) the first thin film transistor (Figure 2, Element M5. Paragraph 58), and the first scan line of the current row (Figure 2, Element Sn. Paragraph 55) is configured to turn off (Paragraphs 65 – 66) the blocking circuit (Figure 2, Element M3. Paragraph 56) such that the potential of the third terminal (Figure 2, Element N1. Paragraph 53) of the driving circuit (Figure 2, Element M1. Paragraph 53) is reset to (Paragraph 64) the second initial voltage signal (Figure 5, Element Vint. Paragraph 57) derived from the source of the second thin film transistor (Figure 2, Element M4. Paragraph 57).
Park et al. is silent with regards to a second terminal of the reset circuit is connected to the first scan line of a current row, and wherein the first scan line of the current row and the first scan line of the previous row are configured to transmit a first scan signal, the second scan line of the current row is configured to transmit a second scan signal, and the first scan signal has a higher signal frequency than the second scan signal.
Tseng et al. teach a second terminal of the reset circuit (Figure 3, Element M8. Paragraph 55) is connected to the first scan line of a current row (Figure 3, Element S1. Paragraph 55).
It would have been obvious to a person of ordinary skill in the art to modify the pixel circuit of Park et al. with the reset circuit connections of Tseng et al. The motivation to modify the teachings of Cho with the teachings of Tseng et al. is to reduce the number of signal ports and wiring space, as taught by Tseng et al. (Paragraph 55).
Kim et al. teach wherein the first scan line of the current row (Figure 13, Element S1i. Paragraph 154) and the first scan line of the previous row (Figure 13, Element S1i. Paragraph 154) are configured to transmit a first scan signal (Figure 13, Element S1i. Paragraph 154), the second scan line of the current row (Figure 13, Element S2i. Paragraph 161) is configured to transmit a second scan signal (Figure 13, Element S2i. Paragraph 161), and the first scan signal (Figure 13, Element S1i. Paragraph 154) has a higher signal frequency (Figures 6 and 13. Paragraphs 114 and 166) than the second scan signal (Figure 13, Element S2i. Paragraph 161).
It would have been obvious to a person of ordinary skill in the art to modify the teachings of the pixel circuit of Cho and the reset circuit connections of Tseng et al. with the driving frequencies of Kim et al. The motivation to modify the teachings of Cho and Tseng et al. with the teachings of Kim et al. is to improve image quality, as taught by Kim et al. (Paragraph 6).
Response to Arguments
Regarding the first argument, in which the applicant asserts that the prior art of record fails to teach at least “wherein a gate of the first thin film transistor is connected to a second scan line of a current row, a gate of the second thin film transistor is connected to the first scan line of a previous row…and the first scan signal has a higher signal frequency than the second scan signal” of at least newly amended Claim 1. The applicant argues that Figures 6 and 13 of Kim et al. fail to teach the above configuration. The examiner respectfully disagrees with the applicant’s assertion. Park et al. teaches a pixel configuration with four gate lines (Sn, Sn-1, EN, and /EN) connected to each pixel circuit. The above Rejection (as well as the previous Non-Final Rejection (November 6, 2025) map line Sn-1 to the first scan line of a previous row and line /EN to the second scan line of a current row. Kim et al. teaches a pixel configuration with four gate lines (S1i, S2i, S2i-1, and EN). Park et al. is relied upon for teaching the pixel configuration and Kim et al. is relied upon to modify the pixel circuit of Park et al. with the frequency of the signal lines. Therefore, Kim et al. does not require the specific pixel configuration of Park et al. and the specific transistor with the specific signal lines will be taught by the modified pixel circuit with the frequency of the lines. The Office is unmoved by the applicant’s arguments and the rejection is maintained.
All other arguments are considered moot in light of the above rejection and/or the response to the first and/or second argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Park et al. (U.S. PG Pub 2016/0322446); Na et al. (U.S. PG Pub 2019/0385523); Feng et al. (U.S. PG Pub 2022/0114958); and Liu et al. (U.S. PG Pub 2024/0105119) disclose a pixel circuit that is similar to the pixel circuit in the instant invention.
Wang et al. (U.S. PG Pub 2022/0157238) discloses a commonly owned pixel circuit that is similar to the instant invention.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW B SCHNIREL whose telephone number is (571)270-7690. The examiner can normally be reached Monday - Friday, 10 - 6 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Boddie can be reached at 571-272-0666. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/A.B.S/Examiner, Art Unit 2625
/WILLIAM BODDIE/Supervisory Patent Examiner, Art Unit 2625
Prosecution Insights