DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/16/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 14-18, 21, 23 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nishitani et al. (US 20150269483) in view of Bhattacharyya (US 7285798).
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With respect to claim 14, Nishitani et al. discloses an arithmetic circuit comprising: a variable resistance element (10) having three terminals of a first terminal (15), a second terminal (14), and a third terminal (13) and configured such that a resistance value is variable (variable resistance) ;an input line connected to the first terminal (15 connected at 13) ;a capacitor (fig. 4, element 36) directly connected to the second terminal in series and provided between the second terminal and a reference potential terminal (fig. 4 and (+) terminal);a first switching element (22) connected to the third terminal (at 13);a wiring connected to the third terminal through the first switching element (from node 18 to node 17);a second switching element (21) connected to a first end of the wiring (at node 18); a third switching element (35) connected to a second end of the wiring (via 10), and wherein an electric charge accumulated in the capacitor (36) is output to the wiring as a spiking signal (see 0088]-[0089]),the arithmetic circuit further comprises a control unit (29) configured to control the first switching element (22), the second switching element (21), and the third switching element (35 via output at 43), the control unit is configured to turn on the first switching element and the second switching element, and the control unit is configured to turn off the second switching element and to turn on the third switching element after the electric charge is accumulated in the capacitor but fails to disclose a fourth switching between the input line and the first terminal.
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Figure 1 of Bhattacharyya (US 7285798) teaches a well-known structure of an inverter. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use the inverter in figure 1 of Bhattacharyya in the circuit of Nishitani et al. for the purpose of giving details of the logic circuitry of the inverter, and implementing the logic circuitry of the inverter.
As such, the resulting device would produce a fourth switching element (inverter 213 between the input terminal line at 13 and the first terminal 15 in Nishitani et al. as implemented by fig. 1 elments 6 or 4 in Bhattacharyya (US 7285798)) between the input line and the first terminal ( 15).
With respect to claim 15, the combination above produces the arithmetic circuit according to Claim 14, wherein the variable resistance element (10) is configured such that a resistance value between the first terminal and the third terminal varies based on a pulse current flowing between the second terminal and the third terminal.
With respect to claim 16, the combination above produces the arithmetic circuit according to Claim 14, wherein the control unit (29) is configured to turn off the first switching element while an input signal is input from the input line, and turn on the first switching element after electric charge is accumulated in the capacitor.
With respect to claim 17, the combination above produces the arithmetic circuit according to Claim 16, wherein a signal output from the third terminal by turning on the first switching element is determined by a resistance value (from variable resistive element) of the variable resistance element and the input signal (at 51).
With respect to claim 18, the combination above produces the arithmetic circuit according to Claim 14, further comprising: a resistor (37) between the first switching element (16) and the second switching element (17). (Here, “between” is an extremely broad adjective. Although 37 would not be between nodes 18 and node 26, resistor 37 would be between node 17 and node 27 ).
With respect to claim 21, the combination above produces the arithmetic circuit according to Claim 14, wherein a plurality of units (see for example 2A illustrating a block diagram illustrating an example of the configurations of the neural network circuit formed using the neural network circuit element of Fig. 1) each including the input line (i.e. 51), the variable resistance element (i.e. 10), the capacitor (i.e. 36), and the first switching element (i.e. 23) are connected to the wiring.
With respect to claim 23, the combination above produces the arithmetic circuit according to Claim 21, wherein the control unit controls the first switching elements of at least a part of the plurality of units not to be synchronized with one another. (Note the switching units can be configured to be synchronized or unsynchronized with one another and deemed to be as such according to the user’s needs)
With respect to claim 25, the combination above produces a neuromorphic device (artificial neural network would be considered neuromorphic) comprising: the arithmetic circuit according to Claim 14; an input circuit (i.e. 41) connected to the input line of the arithmetic circuit; a charging circuit (i.e. 31) connected to the second switching element (21) of the arithmetic circuit; and an output circuit (i.e. 33 or 46) connected to the third switching element of the arithmetic circuit.
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nishitani et al. (US 20150269483) in view of Bhattacharyya (US 7285798) in further view of A et al. (US 8847656). .
With respect to claim 22, the combination above produces the arithmetic circuit according to Claim 21, wherein the control unit (29) controls the first switching element (22) but fails to disclose switching elements of at least a part of the plurality of units to be synchronized with one another.
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A et al. teaches the use MOSFETs in parallel with the same input. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use multiple MOSFETs in parallel with the same input to replace the single switch of 22 for the purpose of increasing redundancy and enhancing reliability. The resulting circuit would produce a plurality of switching elements synchronized with one another.
Response to Arguments
Applicant's arguments filed 3/6/2026 have been fully considered but they are not persuasive.
With respect to applicant’s argument concerning the 102(a)(1) rejections, upon further consideration the claims have been rejected based on obviousness an inverter comprising switching elements.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Allowable Subject Matter
Claims 24 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 24, the prior art fails to suggest or disclose wherein the variable resistance element is a magnetic domain wall motion element, and the magnetic domain wall motion element includes: a magnetic recording layer connecting the second terminal and the third terminal; a nonmagnetic layer stacked on the magnetic recording layer; and a ferromagnetic layer sandwiching the non-magnetic layer with the magnetic recording layer.
Claims 26-31 allowed.
The following is an examiner’s statement of reasons for allowance:
With respect toc alim 26, the prior art fails to suggest or disclose wherein the variable resistance element is a magnetic domain wall motion element, and the magnetic domain wall motion element includes: a magnetic recording layer connecting the second terminal and the third terminal; a nonmagnetic layer stacked on the magnetic recording layer; and a ferromagnetic layer sandwiching the non-magnetic layer with the magnetic recording layer.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F (8:00am-4:00pm).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at M-F (8:00am-4:00pm). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAREEM E ALMO/Examiner, Art Unit 2849
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