Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Moon et al. [US PGPUB 20230073848] (hereinafter Moon).
Regarding claim 1, Moon teaches an array substrate, wherein the array substrate comprises a display area (see annotated Fig. 13) and a peripheral area (see annotated Fig. 13) adjacent to the display area (Fig. 13), and the array substrate comprises:
a base (110/111/211/120, Fig. 13) comprising stacked layers of a substrate (110, Para 119), a sheltering-and-wiring metal layer (211, Para 157, Fig. 13), a buffer layer (lowermost layer of layer 120, Para 160), a shielding metal layer (111, Para 157, Fig. 13), and a blocking insulation layer (uppermost layer of layer 120, Para 160);
an active layer (A2 and material connected to opposite ends of A2, Para 158, Fig. 13) disposed on the base (Fig. 13), wherein the active layer comprises an active segment (A2, Fig. 13) and a first conductor segment (right material connected to D2, Fig. 13) and a second conductor segment (left material connected to S2, Fig. 13) disposed at two ends of the active segment (Fig. 13);
a first insulation layer (120, Para 163) disposed on the base and the active layer (Fig. 13);
a first metal layer (material layer on layer 160 connecting material in holes H6/H7/H4, Para 168) disposed on the first insulation layer (Fig. 13);
a second insulation layer (160, Para 167) disposed on the first insulation layer and the first metal layer (Fig. 13);
a second metal layer (DL, Para 153) disposed on the second insulation layer (Fig. 13),
wherein the array substrate further comprises a first via hole (H7, Para 173) defined above the sheltering- and-wiring metal layer (Fig. 13), a second via hole (H3, Para 170) defined above the shielding metal layer (Fig. 13), a third via hole (H6, Para 173) defined above the first conductor segment (Fig. 13), a fourth via hole (H5, Para 172) defined above the second conductor segment (Fig. 13), and a first connection segment (materials in holes H6, H7 and material on layer 160 connecting the materials in the hole, Fig. 13) located within the display area (Fig. 13) and a second connection segment (PL, Para 152, Fig. 13) located within the peripheral area (Fig. 13),
wherein an end of the first connection segment passes through the first via hole to connect with the sheltering-and-wiring metal layer, another end of the first connection segment passes through the third via hole to connect with the first conductor segment (Fig. 13), the second connection segment passes through the second via hole to connect with the shielding metal layer (Fig. 13), the second metal layer passes through the fourth via hole to connect with the second conductor segment (Fig. 13),
wherein the first metal layer comprises the first connection segment and the second connection segment (Fig. 13); or
the second metal layer comprises the first connection segment and the second connection segment.
Regarding claim 11, Moon teaches a display panel (310, Para 135), wherein the display panel comprises an array substrate, the array substrate comprises a display area (see annotated Fig. 13) and a peripheral area (see annotated Fig. 13) adjacent to the display area (Fig. 13), and the array substrate comprises:
a base (110/111/211/120, Fig. 13) comprising stacked layers of a substrate (110, Para 119), a sheltering-and-wiring metal layer (211, Para 157, Fig. 13), a buffer layer (lowermost layer of layer 120, Para 160), a shielding metal layer (111, Para 157, Fig. 13), and a blocking insulation layer (uppermost layer of layer 120, Para 160);
an active layer (A2 and material connected to opposite ends of A2, Para 158, Fig. 13) disposed on the base (Fig. 13), wherein the active layer comprises an active segment (A2, Fig. 13) and a first conductor segment (right material connected to D2, Fig. 13) and a second conductor segment (left material connected to S2, Fig. 13) disposed at two ends of the active segment (Fig. 13);
a first insulation layer (120, Para 163) disposed on the base and the active layer (Fig. 13);
a first metal layer (material layer on layer 160 connecting material in holes H6/H7/H4, Para 168) disposed on the first insulation layer (Fig. 13);
a second insulation layer (160, Para 167) disposed on the first insulation layer and the first metal layer (Fig. 13);
a second metal layer (DL, Para 153) disposed on the second insulation layer (Fig. 13),
wherein the array substrate further comprises a first via hole (H7, Para 173) defined above the sheltering- and-wiring metal layer (Fig. 13), a second via hole (H3, Para 170) defined above the shielding metal layer (Fig. 13), a third via hole (H6, Para 173) defined above the first conductor segment (Fig. 13), a fourth via hole (H5, Para 172) defined above the second conductor segment (Fig. 13), and a first connection segment (materials in holes H6, H7 and material on layer 160 connecting the materials in the hole, Fig. 13) located within the display area (Fig. 13) and a second connection segment (PL, Para 152, Fig. 13) located within the peripheral area (Fig. 13),
wherein an end of the first connection segment passes through the first via hole to connect with the sheltering-and-wiring metal layer, another end of the first connection segment passes through the third via hole to connect with the first conductor segment (Fig. 13), the second connection segment passes through the second via hole to connect with the shielding metal layer (Fig. 13), the second metal layer passes through the fourth via hole to connect with the second conductor segment (Fig. 13),
wherein the first metal layer comprises the first connection segment and the second connection segment (Fig. 13); or
the second metal layer comprises the first connection segment and the second connection segment.
Allowable Subject Matter
Claims 2-10 and 12-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 2-4, 6, 12-14 and 16 are objected to because the prior arts of record and related prior arts fail to anticipate or render obvious the limitation of claim 2-4, 6, 12-14 and 16. Although individual elements of claim 2-4, 6, 12-14 and 16 may be found in one of more of the prior arts, none of the prior arts, alone or in combination, teaches or suggests the particularly claimed combination of individual elements or the relationship of the claimed individual elements. Wherein any combination of the prior arts to arrive at the claimed combination would be nothing short of impermissible hindsight.
Claims 5, 7-10, 15, and 17-20 are allowable base on their dependency on allowable claims.
Conclusion
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/ISMAIL A MUSE/Primary Examiner, Art Unit 2812
