Prosecution Insights
Last updated: April 19, 2026
Application No. 17/636,090

ELECTRONIC CIRCUITS AND CIRCUIT ELEMENTS

Final Rejection §103§112
Filed
Feb 17, 2022
Examiner
CAO, PHAT X
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Pragmatic Semiconductor Limited
OA Round
2 (Final)
72%
Grant Probability
Favorable
3-4
OA Rounds
2y 8m
To Grant
74%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allow Rate
582 granted / 810 resolved
+3.9% vs TC avg
Minimal +2% lift
Without
With
+2.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
3 currently pending
Career history
813
Total Applications
across all art units

Statute-Specific Performance

§103
46.7%
+6.7% vs TC avg
§102
27.2%
-12.8% vs TC avg
§112
18.4%
-21.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 810 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 44 and 47 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Independent claim 44 (and dependent claim 47 dependent therefrom), lines 6-7, the limitation “the resistor comprising … a second body of material providing a resistive or semiconductive current path…” is unclear. It is not clear that how the device can be called as “a resistor” when the body of the device providing a “semiconductive current path”. The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claim 36 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 36, lines 2-3, the limitation “forming the first, second, third, and fourth terminals after … forming the first and second bodies” is not supported by the original disclosure. It is note that claim 36 depends from claim 1. Claim 1 recites “a first terminal” referred to the terminal 3001 and “a second terminal” referred to terminal 3002 of the Schottky diode. However, Fig. 31 of the present invention illustrates “the first terminals” 3001 is formed before, but not “after” the forming of the first body 3010 as claimed. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 4, 6, 10-11, 14, 22, 32, 35, 44 and 47 are rejected under 35 U.S.C. 103 as being unpatentable over Schalberger et al (US 9,446,946) in view of Yamazaki et al (US 2014/0306219). Regarding claim 1, Schalberger (Figs. a-f) discloses a method of manufacturing an electronic circuit comprising a Schottky diode “Diode” (column 2, lines 56-58, “Schottky diode”) and a second device “TFT”, the Schottky diode comprising a first terminal 102c (column 4, lines 12-19), a second terminal 107c (column 5, lines 25-29), and a first body of semiconductive material 104c (column 4, lines 38-43) providing a semiconductive path between the first and second terminals, the second device “TFT” comprising a third terminal 102a (left 102a, column 4, lines 12-19), a fourth terminal 102a (right 102a) , and a second body 104a of material providing a current path between the third terminal and the fourth terminal, and a substrate 101, the method comprising: forming the first body 104c; and forming the second body 104a, wherein the first body 104c comprises a first quantity of a metal oxide (column 4, lines 38-43) and the second body 104a comprises a second quantity of said metal oxide (column 4, lines 38-43), wherein forming said first quantity comprises forming said first quantity 104c on a first region of the substrate 101, and forming said second quantity comprises forming said second quantity 104a on a second region of the substrate 101. Schalberger discloses the second device including a gate electrode structure 107a, and being functioning as a transistor when corresponding voltage is applied to the gate electrode (column 2, lines 63-67). Schalberger does not disclose the second device being a resistor. However, Yamazaki (Fig. 1C) teaches a method of manufacturing an electronic circuit comprising: a device 100 including a body of metal oxide 108a ([0041] and a gate electrode structure 103a ([0041]), the device 100 being functioning as a resistor when corresponding voltage is applied to the gate electrode 103a ([0042]). Accordingly, in view of teachings of Yamazaki, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the second device of Schalberger to function either as a transistor or a resistor because it is a matter of obvious design choice, depending upon the desired voltages that are applied to the gate electrode of the second device. Regarding claims 4, 6, 10 and 11, Schalberger (Figs. a-f) further discloses: said forming of said first and/or second quantity 104c/104a comprises forming said first and/or second quantity using a technique selected from a list comprising: physical deposition; physical vapor deposition (PVD); chemical deposition; chemical vapor deposition (CVD); atomic layer deposition (ALD); physical-chemical deposition; evaporation; sputtering; sol-gel techniques; chemical bath deposition; spray pyrolysis; plating techniques; pulsed laser deposition (PLD); solution processing; and spin coating (column 3, lines 65-67 through column 4, lines 1-3); forming said first or second quantity comprises depositing said first or second quantity 104c/104a of said metal oxide (column 4, lines 38-43); forming of said first or second quantity 104c/104a comprises forming a first or a second layer, film, or sheet, of said metal oxide (column 4, lines 38-43), said first layer, film, or sheet comprising said first or second quantity 104c/104a; and forming the first body or second body 104 comprises patterning the first layer, film, or sheet (column 4, lines 48-62). Regarding claims 14 and 22, Schalberger (Figs. a-f) further teaches that the first and/or second body 104c/104a are formed on a doped “injection layer” 103 (column 3, lines 29-37), which is similar to a doped semiconductor layer 100/72 as discloses in Fig. 5 of the present invention. Therefore, the doped “injection layer” 103 would inherently inject the doping to the first or second body 104c/104a formed thereon to increase or decrease an electrical conductivity of the first or second body (also see 26-30, “The electrical properties of the transistors are considerably improved with such injection layer”). Regarding claim 32, Schalberger further discloses forming the first and second bodies 104c/104a in a common plane (Fig. b). Regarding claim 35, it has been held that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, claimed properties or functions are presumed to be inherent. In re Best, 195 USPQ 430, 433 (CCPA 1977). In this case, because the claimed first and second bodies and Schalberger’s first and second bodies are produced by substantially identical in structure or composition (i.e., metal oxide comprising indium, gallium, zinc, column 4, lines 37-43), claimed property or function of “substantially transparent to electromagnetic radiation in the range visible to the naked human eye” is presumed to be inherent. Regarding claim 44, Schalberger (Figs. a-f) discloses an electronic circuit comprising a Schottky diode “Diode” (column 2, lines 56-58, “Schottky diode”), a second device “TFT”, and a substrate 101 arranged to support the Schottky diode and second device, the Schottky diode comprising a first terminal 102c (column 4, lines 12-19), a second terminal 107c (column 5, lines 25-29), and a first body 104c of semiconductive material (column 4, lines 38-43) providing a semiconductive path between the first and second terminals, the second device “TFT” comprising a third terminal 102a (left 102a), a fourth terminal 102a (right 102a) , and a second body 104a of material providing a current path (i.e., TFT) between the third terminal and the fourth terminal, wherein said first body 104c of material comprises a metal oxide (e.g. comprises a first quantity of said metal oxide) (column 4, lines 38-43) and said second body 104a of material comprises said metal oxide (e.g. comprises a second quantity of said metal oxide) (column 4, lines 38-43). Schalberger discloses the second device including a gate electrode structure 107a, and being functioning as a transistor when corresponding voltage is applied to the gate electrode (column 2, lines 63-67). Schalberger does not disclose the second device being a resistor. However, Yamazaki (Fig. 1C) teaches a method of manufacturing an electronic circuit comprising: a device 100 including a body of metal oxide 108a ([0041] and a gate electrode structure 103a ([0041]), the device 100 being functioning as a resistor when corresponding voltage is applied to the gate electrode 103a ([0042]). Accordingly, in view of teachings of Yamazaki, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the second device of Schalberger to function either as a transistor or a resistor because it is a matter of obvious design choice, depending upon the desired voltages that are applied to the gate electrode of the second device. Regarding claim 47, Schalberger (Figs. a-f) further discloses: at least one further device (i.e., resistors, not shown, see column 6, lines 7-11) having a third body comprising a third quantity of said metal oxide, wherein the substrate 101 is arranged to support, each of said devices (column 1, lines 39-44). Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Schalberger et al and Yamazaki et al as applied to claim 1 above, and further in view of Lai et al (US 2010/0148168). Schalberger does not disclose the forming of the first quantity is performed after the forming of the second quantity. However, Lai (Fig. 4) teaches a method comprising a first device 450 and a second device 440, the first device comprising a first body including a first quantity 454 of a metal oxide ([0047]) and the second device comprising a second body including a second quantity 444 of a metal oxide ([0047]), and the forming of the first quantity 454 is performed after the forming of the second quantity 444 ([0047], “the first oxide semiconductor layer 444 and the second oxide semiconductor layer 454 are fabricated according to different gas conditions”). Furthermore, it has been held that selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. In re Gibson, 5 USPQ 230 (CCPA 1930). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform the step of the forming of the first quantity before or after the step of the forming of the second quantity because the order of the process steps of forming the first quantity and second quantity are not critical and the same purpose of providing the first quantity separating from the second quantity would result. Claims 29-30, 34, 36, 40 and 41 are rejected under 35 U.S.C. 103 as being unpatentable over Schalberger et al and Yamazaki et al as applied to claim 1 above, and further in view of in view of JP 2011-77106 (with English Translation attached). Regarding claim 29, Schalberger further discloses each of the first and second bodies 104c/104a comprises a respective layer, film, or sheet of the metal oxide (column 4, lines 38-43). Schalberger does not disclose each said respective layer, film, or sheet may have a thickness in the range as claimed. However, JP ‘106 (Fig. 5) teaches a method comprising a first device 4C and a second device 4A, the first device 4C comprising a first body including a first quantity of a metal oxide (page 5, paragraph 4 of translation) and the second device 4A comprising a second body including a second quantity of a metal oxide (page 5, paragraph 4 of translation), each of the first and second bodies comprises a respective layer having a thickness in the range as claimed (i.e., 10-150 nm, page 6, paragraph 1 of translation). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide each respective layer of the metal oxide having a thickness in the range as claimed because such thickness could be optimized during routine experimentation depending upon the film formation conditions and the conductivities which are desired for the first and second bodies of the film, as taught by JP ‘106 (page 6, paragraph 1 of translation). Regarding claim 30, Schalberger further discloses each said respective layer, film, or sheet 104 has the same thickness. Regarding claim 34, Schalberger discloses that the second device can be formed as a resistor (as taught by Yamazaki above) having a second body, but does not disclose the second body has a sheet resistance value in the range as claimed. However, JP ‘106 (Fig. 5) further teaches a resistor 4c including a second body 4c having a sheet resistance value in the range as claimed (i.e., 10KOhm to 100KOhm, page 15, 2nd last paragraph of translation). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the second body of the metal oxide having a sheet resistance value in the range as claimed because such sheet resistance could be optimized during routine experimentation depending upon the desired thickness of the second body and the desired process conditions, as taught by JP ‘106 (page 15, 2nd last paragraph of translation). Regarding claim 36, JP ‘106 further teaches forming the first, second, third, and fourth terminals 6S, 6D, 6E and 6F before (Fig. 5) or after (Fig. 6) forming the first and second bodies 4A/4C. Regarding claim 40, Schalberger further discloses a third device (i.e., resistors, not shown, see column 6, lines 7-11) having a third body of material comprising a third quantity of the metal oxide (column 4, lines 38-43) directly or indirectly, on a third region of the substrate 101 (column 1, lines 39-44). Schalberger does not specifically discloses the third device having fifth and sixth terminals providing a resistive current path between the fifth and sixth terminals. However, JP ‘106 (Fig. 10A) further teaches a resistor device including a body 4C (page 15, 2nd last paragraph of translation) of material comprising a quantity of the metal oxide (page 5, paragraph 4 of translation), and the resistor device having terminals 6E/6F providing a resistive current path between the terminals. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the third device of Schalberger to have fifth and sixth terminals providing a resistive current path between the fifth and sixth terminals, in order to function the third device as a resistor. Regarding claim 41, JP ‘106 (Fig. 10A) further teaches processing (i.e., “plasma treatment”, page 15, paragraph 4 of the translation) the third body 4C differently from said second body 4A , such that the second and third bodies exhibit different conductivities at room temperature. Response to Arguments Applicant’s arguments with respect to independent claim(s) 1 and 44 have been considered but are moot because the new ground of rejection (i.e., new applied reference, new combination) is applied in the current rejection. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHAT X CAO whose telephone number is (571)272-1703. The examiner can normally be reached M-F, 8:00 am - 4:30 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARLON FLETCHER can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PHAT X CAO/ Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Feb 17, 2022
Application Filed
Apr 19, 2025
Non-Final Rejection — §103, §112
Jul 22, 2025
Response Filed
Oct 01, 2025
Final Rejection — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
72%
Grant Probability
74%
With Interview (+2.0%)
2y 8m
Median Time to Grant
Moderate
PTA Risk
Based on 810 resolved cases by this examiner. Grant probability derived from career allow rate.

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