Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
Response filed on 23 April 2025 has been entered. Applicant has amended claims 1-2 and 4 and canceled claims 5-10. Claims 1-4 are pending.
Response to Arguments
Applicant’s arguments with respect to claim(s) claims 1-4 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Due to amendment, rejection of claims 1-4 under 35 U.S.C. 112 has been withdrawn.
Claim Objections
Claim 1 objected to because of the following informalities: The amended claim 1 removed the word “secured” and replaced with “separated from,” resulting in the word “from” being repeated. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2 and 4 rejected under 35 U.S.C. 103 as being unpatentable over Xiao et al. CN109148459A (hereinafter Xiao) in view of Nagashima et al. US20190333928A (hereinafter Nagashima).
Regarding claim 1, Xiao discloses (figs. 1-3) a three-dimensional flash memory aimed at integration comprising:
a plurality of memory cell strings (100, 4:55) formed on a substrate (101 and 201, 6:16-46) to extend in one direction, each of the plurality of memory cell strings (100) including a channel layer (111, 5:12-14) and a charge storage layer (113, 5: 11) surrounding the channel layer (5:30);
a plurality of word lines (WL1-WL4, 5:2) perpendicularly connected to the plurality of memory cell strings (figs. 1a-1b where WL1-WL4 are connected to M1-M4 memory transistors); and
at least one intermediate wiring layer (203, 9:8-13) that is formed at an intermediate point in a direction in which the plurality of memory cell strings (100) extend and is selectively used as one of a source electrode and a drain electrode for each of the plurality of memory cell strings (9:10-14, where “the high voltage P-well 203 serves as a common source region for the channel pillar”),
wherein at least one memory cell string (140, 8:16-32) among the plurality of memory cell strings is formed in a spare region (A02, fig. 3b, 8:16-17) separated from the plurality of word lines (WL1-WL4) and located between the intermediate wiring layer (203) and a lower wiring layer (103, 8:6-11)(figs. 2 and 3d-3h),
wherein none of the plurality of memory cell strings are formed above the at least one memory cell string (140).
Xiao does not disclose wherein none of the plurality of memory cell strings are formed above the at least one memory cell string (140) in a region between the intermediate wiring layer (203) and an upper wiring layer that is located above the plurality of memory cell strings as Xiao is silent on peripheral circuit (3:29) at the top of the second array structure L02.
In same field of endeavor, Nagashima discloses (figs. 1-5) a three-dimensional flash memory with memory cell strings that that use an upper wiring layer (112) (¶52, 73) located above each of the plurality of memory cell strings (MG) (¶32-33, 47, 70) and the at least one intermediate wiring layer (111) (¶48-51, 57-58, 68-70, 74).
It would have been obvious to one of ordinary skill in the art at the time of filing for the memory cell of Xiao to include an upper wiring layer as disclosed by Nagashima, improving the flash memory capacity by increasing storage through additional array structures.
Regarding claim 2, Xiao in view of Nagashima discloses the three-dimensional flash memory of claim 1,
wherein the spare region (A02 within L01, Xiao fig. 3b, 8:16-17) is a region located between the at least one intermediate wiring layer (203, Xiao 9:8-13) and the lower wiring layer (103, Xiao 8:6-11) in the plurality of word lines (WL1-WL4, 5:2).
Regarding claim 4, Xiao in view of Nagashima discloses the three-dimensional flash memory of claim 2,
Nagashima discloses wherein at least one memory cell string (UMS) (¶32-33, 47, 70) other than the at least one memory cell string formed in the spare region among the plurality of memory cell strings (LMSL) (¶32-33, 47, 70) uses the upper wiring layer (112) (¶52, 73) located above each of the plurality of memory cell strings (MG) (¶32-33, 47, 70) and the at least one intermediate wiring layer (111) (¶48-51, 57-58, 68-70, 74) as the source electrode and the drain electrode, respectively (112 can function as a source and 111 can function as a drain for UMS).
It would have been obvious to one of ordinary skill in the art at the time of filing for upper memory cell strings to use adjacent upper and intermediate wiring layers, improving memory by providing control of source/drain distances to the transistors within each memory cell string.
Allowable Subject Matter
Claim 3 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, none of the prior art of record discloses, alone or in combination,
wherein the at least one memory cell string formed in the spare region uses the at least one intermediate wiring layer and the lower wiring layer as the source electrode and the drain electrode, respectively.
Nagashima discloses lower memory cell strings using the intermediate and lower wiring layers, but also includes upper memory cell strings located inline with these cells.
Xiao discloses use a memory cell string in the spare region, as indicated for claim 1, but they cells are disclosed as structural supports, which do not appear underneath the intermediate wiring layer (203) and also do not extend through the insulating array (L03) or the substrate (201) within the second memory array (L02).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Seth D Lawson/ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893