DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities:
Not every paragraph of the specification is numbered.
Appropriate correction is required.
Claim Objections
Claims 8-10 are objected to because of the following informalities:
Change “the reference direction” to “the predetermined reference direction” for clear antecedent basis.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites the limitation "the second wiring unit and the third wiring unit". There is insufficient antecedent basis for this limitation in the claim. The parent claim does not disclose a second wiring unit and a third wiring unit, however claim 11 discloses disclose a second wiring unit and a third wiring unit.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 11-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mashiko (US 5396581 A, from IDS filed on 03/25/2025) , hereinafter “Mashiko”.
As per claim 1, Mashiko teaches An arithmetic apparatus, comprising:
a plurality of arithmetic circuit units (Mashiko: Fig. 8; col 11 lines 55-58; each group corresponding to an arithmetic circuit unit; col 11 lines 41-51) each including a plurality of input lines which is arranged in parallel using a predetermined direction as an extending direction and into which electrical signals corresponding to input values are respectively input (Mashiko: Fig. 8 elements A1-A4; col 11 lines 53-55), and a plurality of output lines which is arranged in parallel so as to intersect with the plurality of input lines, using a direction different from the predetermined direction as an extending direction, and each of which outputs a multiply-accumulate signal (Mashiko: col 14 lines 53-56) representing a sum of product values obtained by multiplying the input values, which are generated on a basis of the electrical signals input into the plurality of input lines, by weight values (Mashiko: Fig. 8 elements B11-B14; col 11 lines 52-54, 59-61);
a signal output circuit including a plurality of signal output lines capable of outputting electrical signals, respectively (Mashiko: Fig. 9 element 104; col 16 lines 21-26; Fig. 9 element 104 is equivalent to Fig. 8 element 10);
and a common wiring unit that electrically connects the plurality of signal output lines of the signal output circuit to the plurality of input lines, which each of the plurality of arithmetic circuit units includes (Mashiko: Fig 3 element 105 is equivalent to Fig 9 element 113; col 3 lines 17-22; element 113 is the right of Fig. 9 that connects register 104 with input lines A1-Al), wherein the plurality of arithmetic circuit units includes a first arithmetic circuit unit and a second arithmetic circuit unit (Mashiko: Fig. 8 elements GRA, GRB; col 11 lines 55-58;), the electrical signals output from the plurality of signal output lines of the signal output circuit are input into the plurality of input lines, which each of the first arithmetic circuit unit and the second arithmetic circuit unit includes, as electrical signals corresponding to the input values (Mashiko: Fig. 9 element 104; col 16 lines 21-26) via the common wiring unit (Mashiko: col 3 lines 17-22), and the extending direction of the plurality of output lines of the first arithmetic circuit unit and the extending direction of the plurality of output lines of the second arithmetic circuit unit are configured to be parallel to each other (Mashiko: Fig. 8 elements B11-B22).
As per claim 2, Mashiko further teaches The arithmetic apparatus according to claim 1, wherein the common wiring unit is configured using, as a reference, a wiring reference plane set on a basis of a positional relationship between the first arithmetic circuit unit and the second arithmetic circuit unit (Mashiko: Fig. 9 element 113.; col 17 lines 16-18; element 113 is positioned relative to input lines A1-AL).
As per claim 3, Mashiko further teaches The arithmetic apparatus according to claim 2, wherein the common wiring unit includes a plurality of reference wires that is arranged in parallel and extends in an identical direction on the wiring reference plane (Mashiko: Fig. 9 element 113; col 17 lines 16-18; element 113 are all in the horizontal direction).
As per claim 4, Mashiko further teaches The arithmetic apparatus according to claim 2, wherein in each of the plurality of arithmetic circuit units, the plurality of input lines and the plurality of output lines are arranged by using a predetermined plane as a reference plane, and the wiring reference plane is set on a basis of a positional relationship between a first reference plane that is the reference plane of the first arithmetic circuit unit and a second reference plane that is the reference plane of the second arithmetic circuit unit (Mashiko: Fig. 8).
As per claim 5, Mashiko further teaches The arithmetic apparatus according to claim 4, wherein the first reference plane and the second reference plane are disposed to be arranged side by side on an identical plane, and the wiring reference plane is set to be parallel to the identical plane on which the first reference plane and the second reference plane are disposed (Mashiko: Fig. 8 elements GRA, GRB; Fig. 9 element 113 is set on a parallel plane to the corresponding arithmetic circuits).
As per claim 6, Mashiko further teaches The arithmetic apparatus according to claim 5, wherein the common wiring unit includes a plurality of reference wires that is arranged in parallel and extends in an identical direction on the wiring reference plane, and the extending direction of the plurality of reference wires is set to be parallel to a direction in which the first reference plane and the second reference plane are arranged side by side (Mashiko: Fig.9 element 113; the wires of element 113 are parallel with the plane of the corresponding arithmetic circuits).
As per claim 7, Mashiko further teaches The arithmetic apparatus according to claim 6, wherein the first reference plane and the second reference plane are arranged side by side in the extending direction of the plurality of input lines of the first arithmetic circuit unit (Mashiko: Fig. 8 elements A1-A4).
As per claim 11, Mashiko further teaches The arithmetic apparatus according to claim 2, wherein the common wiring unit includes a plurality of reference wires that is arranged in parallel and extends in an identical direction on the wiring reference plane, and the common wiring unit includes at least one of a first wiring unit that electrically connects the plurality of signal output lines of the signal output circuit to the plurality of reference wires, a second wiring unit that electrically connects the plurality of reference wires to the plurality of input lines of the first arithmetic circuit unit, or a third wiring unit that electrically connects the plurality of reference wires to the plurality of input lines of the second arithmetic circuit unit (Mashiko: Fig. 8, 9 element 113; col 17 lines 16-18; element 113 connects register outputs to inputs of GRA and GRB).
As per claim 12, Mashiko further teaches The arithmetic apparatus according to claim 11, wherein the common wiring unit includes the first wiring unit, the second wiring unit, and the third wiring unit, and the first wiring unit, the second wiring unit, and the third wiring unit extend in an identical direction (Mashiko: Fig. 8, 9 element 113; col 17 lines 16-18; element 113 connects register outputs to inputs of GRA and GRB).
As per claim 13, Mashiko further teaches The arithmetic apparatus according to claim 1, wherein the common wiring unit includes the second wiring unit and the third wiring unit, and the second wiring unit and the third wiring unit are constituted by an identical wiring unit (Mashiko: Fig. 8, 9 element 113; col 17 lines 16-18; element 113 connects register outputs to inputs of GRA and GRB).
As per claim 14, Mashiko further teaches The arithmetic apparatus according to claim 2, wherein the common wiring unit includes a plurality of reference wires that is arranged in parallel and extends in an identical direction on the wiring reference plane, and the plurality of reference wires is connected to each of end portions on an output side of the plurality of signal output lines of the signal output circuit, end portions on an input side of the plurality of input lines of the first arithmetic circuit unit, and end portions on an input side of the plurality of input lines of the second arithmetic circuit unit (Mashiko: Fig. 8, 9 element 113; col 17 lines 16-18; element 113 connects register outputs to inputs of GRA and GRB).
As per claim 15, Mashiko further teaches The arithmetic apparatus according to claim 1, wherein the extending direction of the plurality of input lines of the first arithmetic circuit unit and the extending direction of the plurality of input lines of the second arithmetic circuit unit are configured to be parallel to each other (Mashiko: Fig. 8 elements A1-A4;).
As per claim 16, Mashiko further teaches The arithmetic apparatus according to claim 1, wherein the plurality of signal output lines of the signal output circuit is arranged in parallel and extends in an identical direction, and the extending direction of the plurality of signal output lines of the signal output circuit is configured to be parallel to the extending direction of the plurality of input lines of the first arithmetic circuit unit (Mashiko: Fig. 9 elements A1-AL;).
As per claim 17, Mashiko further teaches The arithmetic apparatus according to claim 1, wherein the extending direction of the plurality of output lines, which each of the plurality of arithmetic circuit units includes, is configured to be parallel to the extending direction of the plurality of output lines of the first arithmetic circuit unit, and the electrical signals output from the plurality of signal output lines of the signal output circuit are input into the plurality of input lines, which each of the plurality of arithmetic circuit units includes, as the electrical signals corresponding to the input value via the common wiring unit (Mashiko: Fig. 9 elements A1-AL, B11-BMN;).
As per claim 18, Mashiko further teaches The arithmetic apparatus according to claim 1, wherein the common wiring unit includes a switch unit that outputs the electrical signals output from the plurality of signal output lines of the signal output circuit to each of the plurality of arithmetic circuit units in a switchable manner (Mashiko: Fig. 9 element 113; col 17 lines 16-18).
As per claim 19, the claim is directed to an arithmetic apparatus that implements the same features as the arithmetic apparatus of claim 1, and is therefore rejected for at least the same reasons therein. Furthermore, Mashiko teaches and each of which outputs a multiply-accumulate signal representing a sum of product values obtained by multiplying the input values, which are generated on a basis of the electrical signals input into the plurality of input lines, by weight values, and a plurality of multiply-accumulate result signal output lines that outputs multiply-accumulate result signals representing multiply-accumulate results generated on a basis of the multiply-accumulate signals output through the plurality of output lines (Mashiko: Fig. 8 elements B11-B22; col 14 lines 53-56);
a signal input circuit including a plurality of signal input lines into each of which the multiply- accumulate result signal output from each of the plurality of multiply-accumulate result signal output lines is input (Mashiko: Fig. 8, 10 elements SA1, SA2; col 12 lines 45-56);
and a common wiring unit that electrically connects the plurality of multiply-accumulate result signal output lines, which each of the plurality of arithmetic circuit units includes, to the plurality of signal input lines of the signal input circuit (Mashiko: Fig. 10 element 115; col 20 lines 31-34),
As per claim 20, the claim is directed to an arithmetic apparatus that implements the same features as the arithmetic apparatus of claim 1, and is therefore rejected for at least the same reasons therein. Furthermore, Mashiko teaches a network circuit configured by connecting the plurality of arithmetic circuit units (Mashiko: Fig. 8 elements A1-A4; col 11 lines 41-51).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Mashiko in view of Robinett (US 20120098566 A1), hereinafter “Robinett”.
As per claim 8, Mashiko further teaches The arithmetic apparatus according to claim 4,
Mashiko does not teach wherein the first reference plane and the second reference plane are arranged side by side to be orthogonal to a predetermined reference direction, and the wiring reference plane is set to be parallel to the reference direction.
Robinett teaches wherein the first reference plane and the second reference plane are arranged side by side to be orthogonal to a predetermined reference direction, and the wiring reference plane is set to be parallel to the reference direction (Robinett: Fig. 5A-5B; [0048]; crossbars 507-X are on planes that are orthogonal to the plane of via 504).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the resistive matrix of Mashiko with the teachings of Robinett. One would have been motivated to combine these references because both references disclose semiconductor arrays, “crossbar layers increase the bit density and decrease the planar area” (Robinett: [0026]).
As per claim 9, Mashiko/Robinett further teaches The arithmetic apparatus according to claim 8, wherein the wiring reference plane is set to be parallel to the reference direction and the extending direction of the plurality of output lines of the first arithmetic circuit unit (Mashiko: Fig. 8 elements B11-B14).
As per claim 10, Mashiko/Robinett further teaches The arithmetic apparatus according to claim 8, wherein the common wiring unit includes a plurality of reference wires that is arranged in parallel and extends in an identical direction on the wiring reference plane, and the extending direction of the plurality of reference wires is set to be parallel to be the reference direction (Robinett: Fig. 5A-5B element 504).
It would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the resistive matrix of Mashiko with the teachings of Robinett for at least the same reasons as discussed above in claim 8.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHAT N LE whose telephone number is (571)272-0546. The examiner can normally be reached Monday-Friday 8:30AM-5PM ET.
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/P.N.L./
Phat LeExaminer, Art Unit 2182 (571) 272-0546
/EMILY E LAROCQUE/Primary Examiner, Art Unit 2182