DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 16 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claim 16, the limitation “the second nitride-based semiconductor layer” in line 7 lacks antecedent basis. It appears “the second nitride-based semiconductor layer” should be “the nitride-based barrier layer”.
Clear explanation or claim modification is required.
Regarding claim 17-20, these claims are rejected since they inherit the indefiniteness of the claim from which they depend.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhao et al. (CN publication 113016074 A, using WO 2022/174400 A1 as English equivalent), hereinafter referred to as Zhao074.
Regarding claim 16, Zhao074 teaches a method for manufacturing a nitride-based bidirectional switching device (fig. 3a-3m (making of a device in fig. 1c) and related text), comprising: forming a nitride-based active layer (104, [0058], fig. 3a) over a substrate (102, [0058]); forming a nitride-based barrier layer (106, [0021-0022 and 0058]) having a bandgap greater than a bandgap of the nitride-based active layer on the nitride-based active layer ([0021-0022]); forming a first (a gate 110 on left, [0059], fig. 3b) and a second (a gate similar to 110 on right (not labelled), fig. 3b) gate electrodes over the nitride-based barrier layer; forming a first passivation layer (116, [0019 and 0059]) on the nitride-based barrier layer to cover the first and second gate electrodes (fig. 3b); forming a lower blanket field plate (150, [0060-0061], fig. 3c) on the first passivation layer; patterning the lower blanket field plate to respectively form a first and a second lower field plates (122 on left (not labelled) and right, fig. 3e) above the first and second gate electrodes using a wet etching process ([0060-0062], fig. 3c-3e); forming a second passivation layer (118, [0019 and 0063], fig. 3f) on the first passivation layer to cover the first and second lower field plates (fig. 3f); forming an upper blanket field plate (123, [0063-0064], fig. 3f) on the second passivation layer; and patterning the upper blanket field plate to respectively form a first and a second upper field plates (124 on left (not labelled) and right, [0663-0066], fig. 3i) above the first and second lower field plates using a dry etching process ([0063-0066], fig. 3f-3i).
Regarding claim 17, Zhao074 teaches further comprising: forming a third passivation layer (120, [0066], fig. 3i) to cover the first and second upper field plates (fig. 3i-3j).
Regarding claim 18, Zhao074 teaches further comprising: forming a pair of first (126 on left of fig. 1c, [0068-0069]) and second source (similar to 126 on right (not labelled) of fig. 1c) electrodes over the nitride-based barrier layer, such that the first and second gate electrodes, the first and second lower field plate, and the first and second upper field plates are located between the first and second source electrodes (fig. 3k-3m).
Regarding claim 19, Zhao074 teaches wherein patterning the lower blanket field plate is performed such that: the first lower field plate laterally spans at least a part of the first gate structure and a region which is directly adjacent to the first gate structure and between the first and second gate structures; the second lower field plate spans at least a part of the second gate structure and a region which is directly adjacent to the second gate structure and between the first and second gate structures; and the first and second lower field plates are laterally spaced apart from each other (fig. 3b-3e).
Regarding claim 20, Zhao074 teaches wherein patterning the upper blanket field plate is performed such that: the first upper field plate spans at least a part of the first lower field plate and a region which is directly adjacent to the first lower field plate and between the first and second lower field plates; the second upper field plate spans at least a part of the second lower field plate and a region which is directly adjacent to the second lower field plate and between the first and second lower field plates; and the first and second upper field plates are laterally spaced apart from each other (fig. 3f-3i).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-12 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al. (CN publication 113016074 A, using WO 2022/174400 A1 as English equivalent), hereinafter referred to as Zhao074, in view of Bobde et al. (US publication 2017/0338337 A1), hereinafter referred to as Bobde337.
Regarding claim 1, Zhao074 teaches a nitride-based bidirectional switching device (fig. 1a-1c & fig. 2 and related text) comprising: a nitride-based active layer (104, [0019-0021]) disposed on a substrate (102, [0019]); a nitride-based barrier layer (106, [0021-0022]) disposed on the nitride-based active layer and having a bandgap greater than a bandgap of the nitride-based active layer ([0021-0022]); a plurality of spacer layers (116/118/120, [0019]) disposed above the nitride-based barrier layer and comprising at least a first spacer layer (116, [0019]) and a second spacer layer (118, [0019]) disposed above the first spacer layer; and a dual gate transistor (a transistor shown in fig. 1c with a gate 110 on left and a gate similar to 110 on right (not labelled), [0019], fig. 1c) comprising: a first (126 on left of fig. 1c, [0018]) and a second source (similar to 126 on right (not labelled) of fig. 1c) electrodes disposed on the plurality of spacer layers (fig. 1c), and a first (110 on left of fig. 1c) and a second gate (similar to 110 on right (not labelled) of fig. 1c) structures disposed on the nitride-based barrier layer and laterally between the first and second source electrodes (fig. 1c), the first gate structure including a first gate electrode (114 on left of fig. 1c, [0018]) and the second gate structure including a second gate electrode (similar to 114 on right (not labelled) of fig. 1c).
Zhao074 does not explicitly teach a switching device for working with a battery protection controller having a power input terminal, a discharge over-current protection (DO) terminal, a charge over-current protection (CO) terminal, a voltage monitoring (VM) terminal and a ground terminal, and the first source electrode being configured for electrically connecting to a ground terminal of the battery protection controller and the second source electrode being configured for connecting to the VM terminal of the controller through a voltage monitoring resistor; a first gate electrode configured for electrically connecting to the DO terminal of the battery protection controller and a second gate electrode configured for electrically connecting to the CO terminal of the battery protection controller.
Bobde337 teaches a switching device for working with a battery protection controller having a power input terminal, a discharge over-current protection (DO) terminal, a charge over-current protection (CO) terminal, a voltage monitoring (VM) terminal and a ground terminal (fig. 1a-1b), and the first source electrode (S1, fig. 1a-1b) being configured for electrically connecting to a ground terminal (Vss, fig. 1b) of the battery protection controller and the second source electrode (S2) being configured for connecting to the VM terminal of the controller through a voltage monitoring resistor (fig. 1b); a first gate electrode (G on left, fig. 1a-1b) configured for electrically connecting to the DO terminal of the battery protection controller (fig. 1b) and a second gate electrode (G on right) configured for electrically connecting to the CO terminal of the battery protection controller (fig. 1b).
It would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to combine the teachings of Zhao074 with that of Bobde337 so that a nitride-based bidirectional switching device for working with a battery protection controller having a power input terminal, a discharge over-current protection (DO) terminal, a charge over-current protection (CO) terminal, a voltage monitoring (VM) terminal and a ground terminal, the nitride-based bidirectional switching device comprising: a nitride-based active layer disposed on a substrate; a nitride-based barrier layer disposed on the nitride-based active layer and having a bandgap greater than a bandgap of the nitride-based active layer; a plurality of spacer layers disposed above the nitride-based barrier layer and comprising at least a first spacer layer and a second spacer layer disposed above the first spacer layer; and a dual gate transistor comprising: a first and a second source electrodes disposed on the plurality of spacer layers, the first source electrode being configured for electrically connecting to a ground terminal of the battery protection controller and the second source electrode being configured for connecting to the VM terminal of the controller through a voltage monitoring resistor; and a first and a second gate structures disposed on the nitride-based barrier layer and laterally between the first and second source electrodes, the first gate structure including a first gate electrode configured for electrically connecting to the DO terminal of the battery protection controller and the second gate structure including a second gate electrode configured for electrically connecting to the CO terminal of the battery protection controller for allowing for current control in both directions: charger to battery and battery to load ([0002]).
Regarding claim 2, Zhao074 teaches further comprising: a first lower field plate (122 on left of fig. 1c) disposed on the first spacer layer, separated from the first gate structure and laterally spanning at least a part of the first gate structure and a region which is directly adjacent to the first gate structure and between the first and second gate structures (fig. 1c); and a second lower field plate (similar to 122 on right (not labelled) of fig. 1c) disposed on the first spacer layer, separated from the second gate structure and laterally spanning at least a part of the second gate structure and a region which is directly adjacent to the second gate structure and between the first and second gate structures, wherein the first and second lower field plates are laterally spaced apart from each other (fig. 1c).
Regarding claim 2, Zhao074 teaches further comprising: a first lower field plate (124 on left of fig. 1c) disposed on the first spacer layer, separated from the first gate structure and laterally spanning at least a part of the first gate structure and a region which is directly adjacent to the first gate structure and between the first and second gate structures (fig. 1c); and a second lower field plate (similar to 124 on right (not labelled) of fig. 1c) disposed on the first spacer layer, separated from the second gate structure and laterally spanning at least a part of the second gate structure and a region which is directly adjacent to the second gate structure and between the first and second gate structures, wherein the first and second lower field plates are laterally spaced apart from each other (fig. 1c).
Regarding claim 3, Zhao074 teaches further comprising: a first upper field plate (124 on left of fig. 1c) disposed on the second spacer layer, separated from the first lower field plate and laterally spanning at least a part of the first lower field plate and a region which is directly adjacent to the first lower field plate and between the first and second lower field plates; and a second upper field plate (similar to 124 on right (not labelled) of fig. 1c) disposed on the second spacer layer, separated from the second lower field plate and laterally spanning at least a part of the second lower field plate and a region which is directly adjacent to the second lower field plate and between the first and second lower field plates, wherein the first and second upper field plates are laterally spaced apart from each other (fig. 1c).
Regarding claim 3, Zhao074 teaches further comprising: a first upper field plate (122 on left of fig. 1c) disposed on the second spacer layer, separated from the first lower field plate and laterally spanning at least a part of the first lower field plate and a region which is directly adjacent to the first lower field plate and between the first and second lower field plates; and a second upper field plate (similar to 122 on right (not labelled) of fig. 1c) disposed on the second spacer layer, separated from the second lower field plate and laterally spanning at least a part of the second lower field plate and a region which is directly adjacent to the second lower field plate and between the first and second lower field plates, wherein the first and second upper field plates are laterally spaced apart from each other (fig. 1c).
Regarding claim 4, Zhao074 teaches wherein a sidewall of the first lower field plate has a profile different than that of a sidewall of the first upper field plate, wherein a sidewall of the second lower field plate has a profile different than that of a sidewall of the second upper field plate (fig. 1c).
Regarding claim 5, Zhao074 teaches wherein the first and second lower field plates have sidewalls extending upward from the first spacer layer and recessed inward to receive the second spacer layer (fig. 1c).
Regarding claim 6, Zhao074 teaches wherein the first and second upper field plates have sidewalls being oblique (fig. 1c).
Regarding claim 7, Zhao074 teaches wherein the first and second lower field plates have approximately the same thickness as those of the first and second upper second field plates (fig. 1c).
Regarding claim 8, Zhao074 teaches wherein the first and second lower field plates have sidewalls with a first surface roughness, the first and second upper field plates have sidewalls with a second surface roughness which is greater than the first surface roughness (fig. 1c).
Regarding claim 9, Zhao074 teaches wherein the first lower field plate is laterally overlapped with the first gate structure for a distance equal to entire length of the first gate structure, wherein the second lower field plate is laterally overlapped with the second gate structure for a distance equal to entire length of the second gate structure (fig. 1c).
Regarding claim 10, Zhao074 teaches wherein the first upper field plate is laterally overlapped with the first lower field plate for a distance equal to entire length of the first lower field plate, wherein the second upper field plate is laterally overlapped with the second lower field plate for a distance equal to entire length of the second lower field plate (fig. 1c).
Regarding claim 11, Zhao074 teaches wherein the first upper field plate is laterally overlapped with the first lower field plate for a distance less than entire length of the first lower field plate, wherein the second upper field plate is laterally overlapped with the second lower field plate for a distance less than entire length of the second lower field plate (fig. 1c).
Regarding claim 12, Zhao074 teaches wherein the first upper field plate is laterally overlapped with the first gate structure for a distance equal to entire length of the first gate structure, wherein the second upper field plate is laterally overlapped with the second gate structure for a distance equal to entire length of the second gate structure (fig. 1c).
Claim 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao074 in view of Bobde337, as applied to claim 1 or 3 above, and further in view of Wu et al. (US publication 2005/0253168 A1), hereinafter referred to as Wu168.
Regarding claim 13, Zhao074 and Bobde337 disclose all the limitations of claim 3 as discussed above on which this claim depends.
Zhao074 and Bobde337 do not explicitly disclose wherein the first upper field plate is laterally overlapped with the first gate structure for a distance less than entire length of the first gate structure, wherein the second upper field plate is laterally overlapped with the second gate structure for a distance less than entire length of the second gate structure.
Wu168 discloses wherein the upper field plate (150, [0068]) is laterally overlapped with the gate structure (142, [0066]) for a distance less than entire length of the gate structure (fig. 11).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zhao074 and Bobde337 with that of Wu168 so that wherein the first upper field plate is laterally overlapped with the first gate structure for a distance less than entire length of the first gate structure, wherein the second upper field plate is laterally overlapped with the second gate structure for a distance less than entire length of the second gate structure for reducing the peak electric field in the device, resulting in increased breakdown voltage and reduced trapping and can also yield other benefits such as reduced leakage currents and enhanced reliability ([0029]).
Regarding claim 14, Zhao074 and Bobde337 disclose all the limitations of claim 3 as discussed above on which this claim depends.
Zhao074 and Bobde337 do not explicitly disclose wherein the first lower field plate is laterally overlapped with the first gate structure for a distance less than entire length of the first gate structure, wherein the second lower field plate is laterally overlapped with the second gate structure for a distance less than entire length of the second gate structure.
Wu168 discloses wherein the lower field plate (146, [0066]) is laterally overlapped with the gate structure (142, [0066]) for a distance less than entire length of the gate structure (fig. 11).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zhao074 and Bobde337 with that of Wu168 so that wherein the first lower field plate is laterally overlapped with the first gate structure for a distance less than entire length of the first gate structure, wherein the second lower field plate is laterally overlapped with the second gate structure for a distance less than entire length of the second gate structure for reducing the peak electric field in the device, resulting in increased breakdown voltage and reduced trapping and can also yield other benefits such as reduced leakage currents and enhanced reliability ([0029]).
Regarding claim 15, Zhao074 and Bobde337 disclose all the limitations of claim 3 as discussed above on which this claim depends.
Zhao074 and Bobde337 do not explicitly disclose wherein the first upper field plate is laterally overlapped with the first gate structure for a distance less than entire length of the first gate structure, wherein the second upper field plate is laterally overlapped with the second gate structure for a distance less than entire length of the second gate structure.
Wu168 discloses wherein the upper field plate (150, [0068]) is laterally overlapped with the gate structure (142, [0066]) for a distance less than entire length of the gate structure (fig. 11).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zhao074 and Bobde337 with that of Wu168 so that wherein the first upper field plate is laterally overlapped with the first gate structure for a distance less than entire length of the first gate structure, wherein the second upper field plate is laterally overlapped with the second gate structure for a distance less than entire length of the second gate structure for reducing the peak electric field in the device, resulting in increased breakdown voltage and reduced trapping and can also yield other benefits such as reduced leakage currents and enhanced reliability ([0029]).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 16-20 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-5 of U.S. Patent No. 12,218,207 B2.
Although the conflicting claims are not identical, they are not patentably distinct from each other because the subject matter of claim 16-20 of the instant application is encompassed by the subject matter of the Claim 1-5 of U.S. Patent No. 12,218,207 and is obvious.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mohammed R Alam whose telephone number is 469-295-9205 and can normally be reached between 8:00am-6:00pm (M-F) or by e-mail via Mohammed.Alam1@uspto.gov.
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/MOHAMMED R ALAM/Primary Examiner, Art Unit 2897