DETAILED ACTION
AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1, 10 and 11 are amended.
Claims 1-20 are pending.
Claims 1-20 are rejected (Final Rejection).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/20/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS has been considered by the examiner.
Response to Amendments
Applicant’s amendments referred to below were filed 04/16/2026.
Applicant’s amendments to claims 1, 10 and 11 obviate the prior 35 U.S.C. §§ 112(a) and (b) rejections.
For these reasons, the previous 35 U.S.C. §§ 112(a) and (b) rejections have been withdrawn.
However, Applicant’s amendments to the specification and claims 1, 10 and 11 include “new matter” (and corresponding 35 U.S.C. § 112(a) and (b) rejections are introduced) as discussed below.
Response to Arguments
Applicant’s arguments, at Pages 16-18, filed 04/16/2026, with respect to the rejections under 35 U.S.C. § 103 have been fully considered and are persuasive. Therefore, the previous prior art (§ 103) rejections have been withdrawn. However, upon further consideration, new ground(s) of rejection under § 103 are made.
Claim Rejections - 35 U.S.C. § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a), as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Claim 1 has been amended to recite “wherein the simulated completion time and the state transition log for each state machine provide an indication of production efficiency of the manufacturing cell, including non-linear inefficiencies arising during processing of the workpiece order” (emphasis added).
As noted by Applicant’s remarks (at page 15), Para. [0035] of the specification indicates “the planning system 100 enables scheduling for processing different workpiece configurations in a non-linear sequence, including for short-duration production runs” (emphasis added). Thus, Para. [0035] of the specification supports “different workpiece configurations in a non-linear sequence” but does not appear to show “non-linear inefficiencies”.
Viewing Applicant’s support Para. [0035] of the as-filed specification (as discussed above), the original disclosure does not support “non-linear inefficiencies”.
Accordingly, claim 1 is rejected for failing to comply with the written description requirement. Claims 10 and 11 have substantially similar limitations as recited in claim 1; therefore, they are rejected under 35 U.S.C. 112(a) for the same reasons. include similar. Claims 2-9 and 12-20 depend respectively from one or more of rejected claims 1, 10 and 11. Therefore, claims 2-9 and 12-20 are also rejected under the same rationale since these claims inherit the respective deficiencies of claims 1, 10 and 11.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-20 are rejected under 35 U.S.C. § 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention.
Claim 1 recites the limitation of “non-linear inefficiencies arising during processing of the workpiece order” (emphasis added). However, it is not clear what is meant by a non-linear inefficiency during processing of the workpiece order. The specification, at Para. [0035], indicates the scheduling may include different workpiece configurations in a non-linear sequence but it is not clear whether “non-linear inefficiencies” corresponds to the efficiency of a non-linear workpiece configuration schedule.
Accordingly, claim 1 is rejected under 35 U.S.C. § 112(b) for indefiniteness. Claims 10 and 11 have substantially similar limitations as recited in claim 1; therefore, they are rejected under 35 U.S.C. 112(a) for the same reasons. include similar. Claims 2-9 and 12-20 depend respectively from one or more of rejected claims 1, 10 and 11. Therefore, claims 2-9 and 12-20 are also rejected under the same rationale since these claims inherit the respective deficiencies of claims 1, 10 and 11.
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 5-7, 9-14, 16-18 and 20 are rejected under 35 U.S.C. § 103 as being unpatentable over CHAU et al. (U.S. Patent Application Publication No. 2022/0171373 A1) in view of CHIBA (U.S. Patent Application Publication No. 2024/0210927 A1).
Regarding claim 1, CHAU discloses a production utilization planner (PUP) core (model for scheduling [planning] to achieve highest tool/fleet utilization, shortest wait times, and fastest throughput, Para. [0089] of CHAU; See also FIG. 16 shows an example of a tool comprising a plurality of processing modules (e.g., electroplating cells), Para. [0074] of CHAU) for a manufacturing cell (semiconductor manufacturers use one or more substrate processing tools to perform deposition, etching, cleaning, and/or other substrate treatments during fabrication of semiconductor wafers, Para. [0004] of CHAU; See also system for processing semiconductor substrates in a tool comprising a plurality of processing chambers configured to process the semiconductor substrates according to a recipe, Para. [0006] of CHAU; [processing chambers for processing semiconductor substrates are interpreted as manufacturing cells]), including a processor and a memory storing instructions that, when executed by the processor, cause the PUP core to (system … comprises a processor and memory storing instructions for execution by the processor, Para. [0006] of CHAU) perform as: a simulation manager simulating the processing of workpieces arranged in a workpiece order by performing the following steps (instructions are configured to simulate … a plurality of processing scenarios and scheduling parameters for the plurality of processing scenarios for processing the semiconductor substrates in the plurality of processing chambers according to the recipe, Para. [0006] of CHAU; See also simulator 1404 simulates the tool configuration and simulates the processing of the wafers [workpieces] in the tool, Para. [0196] of CHAU; [wafers and/or substrates are interpreted as corresponding to workpieces in this context]; See also regarding arranged in an order/schedule: “predict, using the further trained model, second processing times, second transfer times, and a second route for processing the additional semiconductor substrates in the tool; and a second time to schedule a next set of semiconductor substrates for processing in the tool”, Para. [0048] of CHAU; [Examiner’s Note: the simulation “by performing the following steps” is disclosed when “the following steps” are disclosed]): creating, at initiation of a simulation, an instance of a simulation controller (simulator 1404 may be implemented using a computing device such as a computer … storing one or more computer programs that simulate the operating and processing environment of a tool (e.g., the tool 1406) on the computer … the computer programs additionally comprise instructions for generating, training, and validating the neural networks 1410 and the scheduler level neural network 1412 of the model 1402 on the simulator 1404 as explained below with reference to FIGS. 15A and 15B, Para. [0191] of CHAU; [Examiner’s Note: Applicant’s claim limitation of “creating … an instance of a simulation controller” is interpreted as creating a software instance that controls simulation [and not a piece of hardware]) and an instance of a software model of the manufacturing cell (a model for scheduler pacing is built using nested neural networks or other machine learning algorithms … the model is initially built, trained, and tested offsite using simulation, Para. [0181] of CHAU; See also the model is continually refined and trained further onsite on the actual tool by incrementally using data streams from the tool to make further adjustments to the model that reflect the tool-specific and recipe-specific robot transfer times and that compensate for any process drift … the onsite training also adjusts the model for any recipe changes and/or tool hardware changes, Para. [0181] of CHAU; See also discrete event simulator 1202 communicates with a tool's system software (e.g., the controller 138 of a tool 100 shown in FIG. 1 that executes the tool's system software) and the reinforcement learning model 1204 (e.g., the model generated by the system 400 shown in FIG. 4), Para. [0156] of CHAU; [because the model is tool-specific, and the tool’s system software includes a controller, the creation/building of the model is interpreted to also create an instance of a simulation tool controller]) having state machines (the model 1204 includes a deep neural network that is trained using a reinforcement learning method as explained in further detail with reference to FIG. 13, reinforcement learning involves an agent, a set of states S and a set A of actions per state, and by performing an action ‘a’ from the set A, the agent transitions from state to state, Para. [0165] of CHAU; See also the reinforcement learning method used by the model 1204 can include Q-learning … Q-learning finds an optimal policy for any finite Markov decision process (FMDP), Para. [0166]; [a Markov decision process, including the sets of states and actions, is interpreted as defining a set of states and transition between them [i.e., a state machine]]) configured to perform timed actions on the workpieces (the model is trained using data collected from preventive maintenance operations (PMs), recipe times, and wafer-less auto clean (WAC) times as inputs to the model, Para. [0081] of CHAU; [wafers and/or substrates are interpreted as the workpieces in this semiconductor/etching context]; See also wafer wait times and process time recipe, Para. [0080] of CHAU; See also one neural network is used per robot to predict the transfer times for each robot, Para. [0179]; See also wait time is an amount of time wafers have to wait after processing of the wafers is completed in a processing module until the processing of the wafers can begin in a next processing module, Para. [0188] of CHAU; See also the predetermined criteria may include determining whether the model outputs ensure a small wafer idle time, Para. [0146] of CHAU; [Examiner’s Note: etching/processing/machining time, transfer/transit time, wait time, clean time and idle time are the same and/or similar to the states/processes/timed actions discussed in Applicant’s specification at Para. [0067], which recites “AGV 420 has the states of ‘idle,’ ‘charging,’ ‘transiting/unload,’ ‘waiting/pickup,’ ‘picking up,’ ‘transiting/loaded,’ ‘waiting/drop off,’ and ‘dropping off.’) and Para. [0093], which recites “[e]xamples of timed actions performed by workers 258 include machining a workpiece 452 via a robotic device 262 in the machining subcell 402, cleaning a workpiece 452”), and each state machine has a state during the timed actions (as discussed above, Paras. [0080], [0081], [0146], [0179] and [0188] of CHAU disclose preventive maintenance operations (PMs), clean times, idle times, wait times, process time recipe and recipe times, transfer times), and a state transition from state to state (agent transitions from state to state, Para. [0165] of CHAU); determining, via the simulation controller, a next timed action to be performed by the state machines (instructions are configured to, for each of the plurality of states, send to the model a current state of the plurality of states and multiple schedulable operations to progress to a next state of the plurality of states, receive from the model a best operation from the multiple schedulable operations selected by the model based on the current state to progress to the next state, and simulate execution of the best operation to simulate progression to the next state, Para. [0027] of CHAU; See also model 1204 uses the memorized best next operation for each state when that particular state occurs in the tool during actual wafer processing, Para. [0170] of CHAU); incrementing the simulation to the next timed action (the instructions are configured to further train the model incrementally based on data generated during the processing of the semiconductor substrates and the additional semiconductor substrates in the semiconductor processing tool, Para. [0056] of CHAU; See also the model is continually refined and trained further onsite on the actual tool by incrementally using data streams from the tool to make further adjustments to the model that reflect the tool-specific and recipe-specific robot transfer times and that compensate for any process drift, Para. [0181] of CHAU; Regarding “next state”, see also instructions are configured to, for each of the plurality of states, send to the model a current state of the plurality of states and multiple schedulable operations to progress to a next state of the plurality of states, receive from the model a best operation from the multiple schedulable operations selected by the model based on the current state to progress to the next state, and simulate execution of the best operation to simulate progression to the next state, Para. [0027] of CHAU; See also model 1204 uses the memorized best next operation for each state when that particular state occurs in the tool during actual wafer processing, Para. [0170] of CHAU); updating the software model and the simulation controller each time a state machine performs a timed action (the training of the model incrementally discussed above in relation to Paras. [0056] and [0181] of CHAU corresponds to updating the model; See also discrete event simulator 1202 communicates with a tool's system software (e.g., the controller 138 of a tool 100 shown in FIG. 1 that executes the tool's system software) and the reinforcement learning model 1204 (e.g., the model generated by the system 400 shown in FIG. 4), Para. [0156] of CHAU; See also third phase includes online real-time and unsupervised learning … continuous (i.e., ongoing) training is needed since process recipes and/or hardware can change … when such changes occur, the model needs to adapt to the changes, which can be accomplished by continuous training, Para. [0186] of CHAU); recording, for each state machine, a state transition log comprising an ordered sequence of timed actions (tool system controllers 348 record lot history, detailed event logs, lot-based alarms, time-based alarms, tool controller health, parts tracking, component history, material scheduling, Para. [0112] of CHAU; See also tool system controllers 348-1, 348-2, … 348-N, FIG. 3 & Para. [0111] of CHAU; See also Paras. [0102] & [0164] of CHAU) performed by that state machine during simulated processing of the workpiece order (discrete event simulator 1202 can simulate a wafer processing sequence that takes about an hour in less than a minute, Para. [0164] of CHAU; See also the model generator 408 can identify and store a set of optimum configurations and run scenarios per tool and store the set for automatic selection … the simulator 404 can generate training data for various combinations of tool configurations, wafer-flow types, recipe/WAC times, and run scenarios, Para. [0132] of CHAU); repeating the steps of determining the next timed action, incrementing the simulation, updating the software model and the simulation controller, and recording the state transition log for each state machine, until all of the workpieces have been processed (models generated using machine learning can produce reliable, repeatable decisions and results, and uncover hidden insights through learning from historical relationships and trends in the data, Para. [0149] of CHAU; See also discrete event simulator 1202 repeats steps 1304-1312 until the final state is reached, Para. [0170]; See also processing chambers in the substrate processing tools usually repeat the same task on multiple substrates, Para. [0005] of CHAU; [Examiner has cited to citations in CHAU teaching repeating of operations, and the determining, incrementing, updating and recording operations have been mapped above]; Regarding “until all of the workpieces have been processed”, see total processing time for all the wafers, Para. [0128] of CHAU; [all of the wafers is interpreted to correspond to all of the workpieces, and total processing time for all of the wafers/workpieces is interpreted to correspond to an indication that all of the wafers have been processed]).
Although CHAU outputs, from a neural network, a predicted program execution time and a total processing time for all wafers (Paras. [0128] & [0189] of CHAU), which is similar/same as simulated completion time, and vaguely discusses remote access for monitoring performance metrics (Para. [0224] of CHAU), CHAU does not appear to explicitly disclose outputting, for review by a user, a simulated completion time for the simulation, and the state transition log for each state machine, each state transition log representing execution of the ordered sequence of timed actions performed by the respective state machine during simulated processing of the workpiece order, wherein the simulated completion time and the state transition log for each state machine provide an indication of production efficiency of the manufacturing cell, including non-linear inefficiencies arising during processing of the workpiece order, and thereby support determination of adjustments to at least one of the following: a physical layout of workers in the manufacturing cell, a worker schedule, and/or a worker behavior, to thereby increase worker efficiency.
CHIBA, however, teaches outputting, for review by a user, a processing of the workpiece order, and the state transition log for each state machine, each state transition log representing execution of the ordered sequence of timed actions performed by the respective state machine during (FIG. 7 of CHIBA shows a time chart “representing individual manufacturing processes based on the manufacturing results, and is exemplary display of visualized manufacturing statuses of products manufactured through a plurality of manufacturing processes in order”, Paras. [0052]-[0054] of CHIBA; See also the machine operation state, the machine event, and the maintenance history are displayed on the timeline created from the viewpoint of the products of interest, Para. [0073] of CHIBA; See also the manufacturing results 122 include information about products manufactured in manufacturing units (such as the start time, end time, and processing period of each of processes constituting the manufacturing line), statuses of machines in operation, Para. [0026] of CHIBA), wherein the (Examiner’s note: this “wherein” and “thereby” limitation is interpreted as simply stating what can be done with the order completion time (and the log/history), i.e., identify/indicate efficiency (and support schedule decision making), which would be inherent (i.e., the faster the job/processing completes (i.e., the lower the order completion time), the more efficient the manufacturing cell is); nonetheless, CHIBA teaches the operation efficiency may change when an operation method is modified, or the operation efficiency may change when the procedure of operation methods is modified … an operation method change history (changes in procedure or operation details) can be accumulated … for example, the Method of the process characteristic factor is linked to the manufacturing recipe result data illustrated in FIG. 3, Para. [0041] of CHIBA; See also when the works in each process are performed with no problem, the product moves smoothly and the bars overlap evenly … however, when the smooth work flow is prevented for any reason, the bars overlap unevenly and the non-smooth work has a darker or lighter color than the remaining works … this allows the user to know the work status intuitively … in addition, the user can see the relationship between the manufacturing work periods of the product shown by the bars and the 5M1E change points, Para. [0102] of CHIBA).
CHIBA is analogous prior art because it is from the “same field of endeavor” as the claimed invention. See MPEP 2141.01(a)(I) and Para. [0006] of CHIBA (information processing of manufacturing log information about manufacturing of products grouped in manufacturing units). Before the effective filing date of the claimed invention, it would have been obvious for one of ordinary skill in the art, having the teachings of CHAU and CHIBA before him or her, to modify CHAU to include output/display manufacturing recipe time-series data as taught by CHIBA (including the simulated manufacturing recipes of CHAU). The suggestion/motivation for doing so would have been to allow the user to know the work status intuitively (Para. [0103] of CHIBA) by visibly displaying changes in process characteristic factors caused during one or more of manufacturing processes of products manufactured through the manufacturing processes (Para. [0005] of CHIBA).
Regarding claim 2, CHAU as modified by CHIBA discloses the PUP core of Claim 1, wherein the instructions, when executed by the processor, cause the PUP core to perform as: a batch analysis tool (the trained model uses reinforced learning to handle batch/multiple substrates in various processing scenarios, Paras. [0080]-[0081] of CHAU) performing a batch analysis on a quantity of iterations of the workpiece order (batch (multiple substrates) processing tools used for multiple parallel material deposition processes with restrictions on wafer wait times, pacing a scheduler of a tool to achieve best throughput and least wafer wait time, Para. [0080] of CHAU; See also to improve the accuracy of scheduler pacing used in tools for multiple parallel material deposition (e.g., multi-layer plating) processes, the present disclosure proposes a machine learning method based on nested neural networks for accurately predicting scheduler pacing for different processes, Para. [0089] of CHAU) to simulate, by performing the following: randomizing the workpiece order by arranging the workpieces into a different ordering than previously simulated (Q-learning can handle problems with stochastic transitions and rewards without requiring adaptations … Q-learning finds an optimal policy for any finite Markov decision process (FMDP) … Q-learning maximizes the expected value of the total reward over all successive steps, starting from the current state, Para. [0166] of CHAU; [Examiner’s note: stochastic means randomly determined and a Markov process is a stochastic/random process]; See also simulator is used to simulate, using realistic transfer times in actual tools, various scheduling scenarios and wafer routing paths that may be feasible in real tools … the simulator performs these simulations based on hardware configurations of different tools and based on various processes that can be used in the tools for processing wafers, Para. [0183] of CHAU); performing, using the simulation manager, a simulation of the randomized workpiece order (Q-learning can handle problems with stochastic transitions and rewards without requiring adaptations … Q-learning finds an optimal policy for any finite Markov decision process (FMDP) … Q-learning maximizes the expected value of the total reward over all successive steps, starting from the current state, Para. [0166] of CHAU; [Examiner’s note: stochastic means randomly determined and a Markov process is a stochastic/random process]; See also simulator is used to simulate, using realistic transfer times in actual tools, various scheduling scenarios and wafer routing paths that may be feasible in real tools … the simulator performs these simulations based on hardware configurations of different tools and based on various processes that can be used in the tools for processing wafers, Para. [0183] of CHAU); repeating the steps of randomizing the workpiece order, and performing a simulation of the randomized workpiece order, until all of the iterations have been completed (models generated using machine learning can produce reliable, repeatable decisions and results, and uncover hidden insights through learning from historical relationships and trends in the data, Para. [0149] of CHAU; See also discrete event simulator 1202 repeats steps 1304-1312 until the final state is reached, Para. [0170] of CHAU; See also processing chambers in the substrate processing tools usually repeat the same task on multiple substrates, Para. [0005] of CHAU; [Examiner has cited to citations in CHAU teaching repeating of operations, and the repeatable operations (randomizing order, and performing the simulation have been mapped above]; Regarding “until all of the iterations have been completed”, see total processing time for all the wafers, Para. [0128] of CHAU; [total processing time for all of the wafers is interpreted to correspond to all of the iterations have been completed/processed]); and outputting a batch analysis list of the simulated completion time for each randomized workpiece order (CHAU, as discussed above, teaches the workpiece order(s) may be simulated randomized workpiece order(s); CHIBA teaches outputting a batch analysis list of the completion time for each workpiece order: FIG. 7 of CHIBA shows a time chart “representing individual manufacturing processes based on the manufacturing results, and is exemplary display of visualized manufacturing statuses of products manufactured through a plurality of manufacturing processes in order”, Paras. [0052]-[0054] of CHIBA; See also the machine operation state, the machine event, and the maintenance history are displayed on the timeline created from the viewpoint of the products of interest, Para. [0073] of CHIBA; See also the manufacturing results 122 include information about products manufactured in manufacturing units (such as the start time, end time, and processing period of each of processes constituting the manufacturing line), statuses of machines in operation, Para. [0026] of CHIBA).
Regarding claim 3, CHAU as modified by CHIBA discloses the PUP core of Claim 2, wherein the instructions, when executed by the processor, cause the PUP core to perform as: an uncertainty analysis tool performing an uncertainty analysis on a plurality of randomized workpiece orders selected from the batch analysis list, by performing the following ([Examiner’s Note: the uncertainty analysis “by performing the following” is disclosed when “the following [steps]” are disclosed]; See also Q-learning can handle problems with stochastic transitions and rewards without requiring adaptations … Q-learning finds an optimal policy for any finite Markov decision process (FMDP) … Q-learning maximizes the expected value of the total reward over all successive steps, starting from the current state, Para. [0166] of CHAU; [Examiner’s note: stochastic means randomly determined and a Markov process is a stochastic/random process]): changing a value of at least one timed action of at least one of the state machines (the instructions are configured to adjust the model for any changes to the recipe, the semiconductor processing tool, or both, Para. [0057] of CHAU; See also the predetermined criteria include determining whether the model can compensate for tool-to-tool variations and for same-tool performance drift, and whether the model can optimize for unavailable PMs, Para. [0146] of CHAU; [variations and performance drift are interpreted as changes to the tool’s performance, i.e., changes to the time of the processes/timed actions]; See also next sentence: the predetermined criteria may include determining whether the model outputs ensure a small wafer idle time (e.g., less than 2%) and high manufacturing efficiency (e.g., greater than 97%), Para. [0146] of CHAU; See also next paragraph: FIG. 8 shows a method 800 for validating the model in further detail … the total dataset is divided into one final test set and N other subsets, where N is an integer greater than one … each model is trained on all but one of the subsets to get N different estimates of the validation error rate, Para. [0148] of CHAU); performing, using the simulation manager, a simulation of one of the workpiece orders using the changed timed action (the instructions are configured to adjust the model for any changes to the recipe, the semiconductor processing tool, or both, Para. [0057] of CHAU; See also simulating the plurality of processing scenarios includes data generated based on a configuration of the tool, wafer-flow types, run scenarios, recipe times, and wafer-less auto clean times obtained from the tool, Para. [0043] of CHAU; See also additional training data are generated using simulations to cover various processing scenarios used by the semiconductor manufacturers using the tools, Para. [0082] of CHAU); updating the simulated completion time for the workpiece order as a result of the changed timed action (the instructions are configured to adjust the model for any changes to the recipe, the semiconductor processing tool, or both, Para. [0057] of CHAU; See also self-exploration process uses the discrete event simulator to automate efforts to find the best possible way to operate a system (e.g., to find the best path in which to move a wafer through a tool) at optimum throughput performance, Para. [0086] of CHAU; See also success criteria can also include whether wafer idle times are less than a small percentage (e.g., 2%) of total processing time for all the wafers, Para. [0128] of CHAU; See also the nested neural network based model is initially designed and trained offline using simulated data and then trained online using real tool data for predicting wafer routing path and scheduling, Para. [0172] of CHAU; See also discrete event simulator 1202 can simulate a wafer processing sequence that takes about an hour in less than a minute, Para. [0164] of CHAU; See also using the method, a model is developed and trained initially offline using simulation and then online using the actual tool for predicting wafer routing path and scheduling to achieve highest tool/fleet utilization, shortest wait times, and fastest throughput, Para. [0089] of CHAU; See also discussion of CHIBA above); repeating, for every workpiece order, the steps of changing the value of at least one timed action, performing the simulation of the workpiece order, and updating the simulated completion time (models generated using machine learning can produce reliable, repeatable decisions and results, and uncover hidden insights through learning from historical relationships and trends in the data, Para. [0149] of CHAU; See also discrete event simulator 1202 repeats steps 1304-1312 until the final state is reached, Para. [0170] of CHAU; See also processing chambers in the substrate processing tools usually repeat the same task on multiple substrates, Para. [0005] of CHAU; [Examiner has cited to citations in CHAU teaching repeating of operations, and the repeatable operations (changing the value, performing the simulation and updating the simulated completion time have been mapped above]; See also discussion of CHIBA above); and identifying, from among the workpiece orders subjected to the uncertainty analysis, the workpiece order that has the shortest simulated completion time (using the method, a model is developed and trained initially offline using simulation and then online using the actual tool for predicting wafer routing path and scheduling to achieve highest tool/fleet utilization, shortest wait times, and fastest throughput, Para. [0089] of CHAU; [the fastest throughput is interpreted to correspond to the shortest simulated completion time]; See also success criteria can also include whether wafer idle times are less than a small percentage (e.g., 2%) of total processing time for all the wafers, and whether a manufacturing efficiency (actual/theoretical cycle time) can be high (e.g., greater than 97%) for each recipe, Para. [0128] of CHAU; See also above discussion regarding simulation/simulator of CHAU involving the model; See also discussion of CHIBA above).
Regarding claim 5, CHAU as modified by CHIBA discloses the PUP core of Claim 1, wherein the instructions, when executed by the processor, cause the PUP core to perform as: a hardware interface module transmitting the workpiece order from the PUP core to the manufacturing cell (the host computer 1802 is used by an operator to issue commands, provide recipe and so on to the tool 1600, Para. [0212] of CHAU; See also discrete event simulator 1202 communicates with a tool's system software (e.g., the controller 138 of a tool 100 shown in FIG. 1 that executes the tool's system software) and the reinforcement learning model 1204 (e.g., the model generated by the system 400 shown in FIG. 4), Para. [0156]; See also one or more of the elements 402-408 can be communicatively interconnected by one or more networks, Para. [0121]), and initiating production of the workpiece order upon user command (the host computer 1802 is used by an operator to issue commands, provide recipe and so on to the tool 1600, Para. [0212] of CHAU).
Regarding claim 6, CHAU as modified by CHIBA discloses the PUP core of Claim 5, wherein the instructions, when executed by the processor, cause the PUP core to perform as a health monitor module performing the following steps: monitoring real-time performance of the manufacturing cell during processing of the workpiece order (monitor current progress of fabrication operations, examine a history of past fabrication operations, examine trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process, Para. [0224] of CHAU; See also method employs both offline learning using simulation and online learning using real-time tool data, Para. [0180] of CHAU); comparing the real-time performance of the manufacturing cell to predicted performance based on the simulation of the workpiece order in the software model (to determine if one model can cover all possible scenarios or a dedicated model will be needed, the model generator 408 can apply the selected machine learning method to generate a model based on data collected from multiple tool configurations and run scenarios to check if prediction accuracy can meet success criteria …. success criteria can also include whether wafer idle times are less than a small percentage (e.g., 2%) of total processing time for all the wafers, and whether a manufacturing efficiency (actual/theoretical cycle time) can be high (e.g., greater than 97%) for each recipe, Para. [0128] of CHAU); and detecting at least one of (Examiner’s Note: Claim 6 interpreted to only require detecting one of errors, failures or discrepancies): errors and/or failures of the manufacturing cell (each model is trained on all but one of the subsets to get N different estimates of the validation error rate … the model with the lowest validation error rate is deployed for use, Para. [0148] of CHAU); and discrepancies between the real-time performance of the manufacturing cell and the predicted performance based on the simulation (success criteria can also include whether wafer idle times are less than a small percentage (e.g., 2%) of total processing time for all the wafers, and whether a manufacturing efficiency (actual/theoretical cycle time) can be high (e.g., greater than 97%) for each recipe, Para. [0128] of CHAU).
Regarding claim 7, CHAU as modified by CHIBA discloses the PUP core of Claim 6, wherein the instructions, when executed by the processor, cause the PUP core to perform as the health monitor module performing the following steps: detecting trends in one or more modeled parameters of the state machines based on discrepancies between the real-time performance and a simulated performance (models generated using machine learning can produce reliable, repeatable decisions and results, and uncover hidden insights through learning from historical relationships and trends in the data, Para. [0149] of CHAU; See also monitor current progress of fabrication operations, examine a history of past fabrication operations, examine trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process, Para. [0224] of CHAU); and proposing changes to one or more of the modeled parameters of the software model based on a trend (monitor current progress of fabrication operations, examine a history of past fabrication operations, examine trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process, Para. [0224] of CHAU; See also the further trained model is configured to output a recommendation for a tool configuration in response to receiving recipe information as input, Para. [0052] of CHAU; [the output recommendation of a tool configuration is interpreted to correspond to a proposed tool parameter, which is a part of the trained CHAU model]), to reflect the real-time performance of the manufacturing cell (method employs both offline learning using simulation and online learning using real-time tool data, Para. [0180] of CHAU).
Regarding claim 9, CHAU as modified by CHIBA discloses the PUP core of Claim 1, further comprising: a user interface configured to perform at least one of the following ([Examiner’s Note: the user interface configured to perform “at least one of the following” is disclosed when a “user interface” configured to perform “one of the following [steps]” is disclosed]): facilitate user entry of a least one of simulation parameters, worker schedules, and availability dates and completion dates of the workpieces; display upcoming tasks to be performed by workers, including at least technicians or a robotic device; display alerts of potential health issues of the manufacturing cell; display proposed changes to one or more modelled parameters of the software model based on discrepancies between real-time performance and simulated performance of the manufacturing cell; and facilitate user adjustment of one of more of the modelled parameters (remote computer may include a user interface that enables entry or programming of parameters and/or settings, which are then communicated to the system from the remote computer, Para. [0225] of CHAU; See also set of model results can be coded into a user interface to facilitate automatic scheduling parameter selection by the tool operator based on the tool's tool configuration and run scenario selected by the tool operator, Para. [0132] of CHAU; See also lot-based alarms, time-based alarms, Para. [0112] of CHAU; [alerts are interpreted to correspond to alarms]).
Regarding claim 10, CHAU discloses a planning system (model for scheduling [planning] to achieve highest tool/fleet utilization, shortest wait times, and fastest throughput, Para. [0089] of CHAU) for simulating the processing of workpieces by a manufacturing cell (FIG. 16 shows an example of a tool comprising a plurality of processing modules (e.g., electroplating cells), Para. [0074]; See also semiconductor manufacturers use one or more substrate processing tools to perform deposition, etching, cleaning, and/or other substrate treatments during fabrication of semiconductor wafers, Para. [0004] of CHAU; See also system for processing semiconductor substrates in a tool comprising a plurality of processing chambers configured to process the semiconductor substrates according to a recipe, Para. [0006] of CHAU; [processing chambers for processing semiconductor substrates are interpreted as manufacturing cells]), the planning system comprising: a production utilization planner (PUP) core (model for scheduling to achieve highest tool/fleet utilization, shortest wait times, and fastest throughput, Para. [0089] of CHAU) having a simulation and analysis module having a processor and a memory (system … comprises a processor and memory storing instructions for execution by the processor, Para. [0006] of CHAU), the memory storing instructions that, when executed by the processor, cause the simulation and analysis module to (system for processing semiconductor substrates in a tool comprising a plurality of processing chambers configured to process the semiconductor substrates according to a recipe, comprises a processor and memory storing instructions for execution by the processor … instructions are configured to simulate, using the second data, a plurality of processing scenarios and scheduling parameters for the plurality of processing scenarios for processing the semiconductor substrates in the plurality of processing chambers according to the recipe, Para. [0006] of CHAU) perform as: a simulation manager configured to simulate the processing of workpieces arranged in a workpiece order, by performing the following steps (instructions are configured to simulate … a plurality of processing scenarios and scheduling parameters for the plurality of processing scenarios for processing the semiconductor substrates in the plurality of processing chambers according to the recipe, Para. [0006] of CHAU; See also simulator 1404 simulates the tool configuration and simulates the processing of the wafers in the tool, Para. [0196]; [wafers are workpieces in this context]; See also regarding arranged in an order/schedule: “predict, using the further trained model, second processing times, second transfer times, and a second route for processing the additional semiconductor substrates in the tool; and a second time to schedule a next set of semiconductor substrates for processing in the tool”, Para. [0048] of CHAU; [Examiner’s Note: the simulation “by performing the following steps” is disclosed when “the following steps” are disclosed]): creating, at initiation of a simulation, an instance of a simulation controller (simulator 1404 may be implemented using a computing device such as a computer comprising one or more hardware processors (e.g., CPUs) and one or more memory devices storing one or more computer programs that simulate the operating and processing environment of a tool (e.g., the tool 1406) on the computer … the computer programs additionally comprise instructions for generating, training, and validating the neural networks 1410 and the scheduler level neural network 1412 of the model 1402 on the simulator 1404 as explained below with reference to FIGS. 15A and 15B, Para. [0191] of CHAU; [Examiner’s Note: Applicant’s claim limitation of “creating … an instance of a simulation controller” is interpreted as creating a software instance that controls simulation [and not a piece of hardware]), and an instance of a software model of the manufacturing cell, the software model having state machines (a model for scheduler pacing is built using nested neural networks or other machine learning algorithms … the model is initially built, trained, and tested offsite using simulation, Para. [0181] of CHAU; See also the model is continually refined and trained further onsite on the actual tool by incrementally using data streams from the tool to make further adjustments to the model that reflect the tool-specific and recipe-specific robot transfer times and that compensate for any process drift … the onsite training also adjusts the model for any recipe changes and/or tool hardware changes, Para. [0181] of CHAU; See also discrete event simulator 1202 communicates with a tool's system software (e.g., the controller 138 of a tool 100 shown in FIG. 1 that executes the tool's system software) and the reinforcement learning model 1204 (e.g., the model generated by the system 400 shown in FIG. 4), Para. [0156] of CHAU; [because the model is tool-specific, and the tool’s system software includes a controller, the creation/building of the model is interpreted to also create an instance of a simulation tool controller]) having state machines (the model 1204 includes a deep neural network that is trained using a reinforcement learning method as explained in further detail with reference to FIG. 13, reinforcement learning involves an agent, a set of states S and a set A of actions per state, and by performing an action ‘a’ from the set A, the agent transitions from state to state, Para. [0165] of CHAU; See also the reinforcement learning method used by the model 1204 can include Q-learning … Q-learning finds an optimal policy for any finite Markov decision process (FMDP), Para. [0166]; [a Markov decision process is interpreted as defining a set of states and transition between them [i.e., a state machine]]) configured to perform timed actions on the workpieces (the model is trained using data collected from preventive maintenance operations (PMs), recipe times, and wafer-less auto clean (WAC) times as inputs to the model, Para. [0081] of CHAU; [wafers and/or substrates are interpreted as the workpieces in this semiconductor/etching context]; See also wafer wait times and process time recipe, Para. [0080] of CHAU; See also one neural network is used per robot to predict the transfer times for each robot, Para. [0179]; See also wait time is an amount of time wafers have to wait after processing of the wafers is completed in a processing module until the processing of the wafers can begin in a next processing module, Para. [0188] of CHAU; See also the predetermined criteria may include determining whether the model outputs ensure a small wafer idle time, Para. [0146] of CHAU; [Examiner’s Note: etching/processing/machining time, transfer/transit time, wait time, clean time and idle time are the same and/or similar to the states/processes/timed actions discussed in Applicant’s specification at Para. [0067], which recites “AGV 420 has the states of ‘idle,’ ‘charging,’ ‘transiting/unload,’ ‘waiting/pickup,’ ‘picking up,’ ‘transiting/loaded,’ ‘waiting/drop off,’ and ‘dropping off.’) and Para. [0093], which recites “[e]xamples of timed actions performed by workers 258 include machining a workpiece 452 via a robotic device 262 in the machining subcell 402, cleaning a workpiece 452”]), the state machines comprising workers (see workers being robotic devices as discussed below with relation to Paras. [0179] & [0181] of CHAU), workpiece stations (transfer time for a robot is an amount of time a robot takes to move wafers from point A to point B (e.g., from one processing module to another or from an airlock to a processing module, and from a loading station of the tool to an airlock), Para. [0188] of CHAU), and automated ground vehicles (transport controller 134 control robots 112 and 124, actuators and sensors related to the transportation of substrates to and from the substrate processing tool 100, Para. [0093] of CHAU; See also a front-end robot 1610 transports the substrates 1606 from the FOUP 1608 to a spindle 1612 and then to one of the pre-processing modules 1604, Para. [0207] of CHAU; See also after pre-processing, a backend robot 1614 transports the substrates 1606 from the pre-processing modules 1604 to one or more of the processing modules 1602 for electroplating, Para. [0208] of CHAU; [transport control robots are interpreted as corresponding to automated ground vehicles, where a vehicle is defined as a thing used for transporting goods on land or a means for transport]), the workers comprising technicians and/or robotic devices (the model is continually refined and trained further onsite on the actual tool by incrementally using data streams from the tool to make further adjustments to the model that reflect the tool-specific and recipe-specific robot transfer times and that compensate for any process drift … the onsite training also adjusts the model for any recipe changes and/or tool hardware changes, Para. [0181] of CHAU; See also one neural network is used per robot to predict the transfer times for each robot, Para. [0179] of CHAU), and each state machine has a state during the timed actions (as discussed above, Paras. [0080], [0081], [0146], [0179] and [0188] of CHAU disclose preventive maintenance operations (PMs), clean times, idle times, wait times, process time recipe and recipe times, transfer times), and a state transition from state to state (agent transitions from state to state, Para. [0165] of CHAU); determining, via the simulation controller, a next timed action to be performed by the state machines (instructions are configured to, for each of the plurality of states, send to the model a current state of the plurality of states and multiple schedulable operations to progress to a next state of the plurality of states, receive from the model a best operation from the multiple schedulable operations selected by the model based on the current state to progress to the next state, and simulate execution of the best operation to simulate progression to the next state, Para. [0027] of CHAU; See also model 1204 uses the memorized best next operation for each state when that particular state occurs in the tool during actual wafer processing, Para. [0170] of CHAU); incrementing the simulation to the next timed action (the instructions are configured to further train the model incrementally based on data generated during the processing of the semiconductor substrates and the additional semiconductor substrates in the semiconductor processing tool, Para. [0056] of CHAU; See also the model is continually refined and trained further onsite on the actual tool by incrementally using data streams from the tool to make further adjustments to the model that reflect the tool-specific and recipe-specific robot transfer times and that compensate for any process drift, Para. [0181] of CHAU; Regarding “next state”, see also instructions are configured to, for each of the plurality of states, send to the model a current state of the plurality of states and multiple schedulable operations to progress to a next state of the plurality of states, receive from the model a best operation from the multiple schedulable operations selected by the model based on the current state to progress to the next state, and simulate execution of the best operation to simulate progression to the next state, Para. [0027] of CHAU; See also model 1204 uses the memorized best next operation for each state when that particular state occurs in the tool during actual wafer processing, Para. [0170] of CHAU); updating the software model and the simulation controller each time a state machine performs a timed action (the training of the model incrementally discussed above in relation to Paras. [0056] and [0181] of CHAU corresponds to updating the model; See also discrete event simulator 1202 communicates with a tool's system software (e.g., the controller 138 of a tool 100 shown in FIG. 1 that executes the tool's system software) and the reinforcement learning model 1204 (e.g., the model generated by the system 400 shown in FIG. 4), Para. [0156] of CHAU; See also third phase includes online real-time and unsupervised learning … continuous (i.e., ongoing) training is needed since process recipes and/or hardware can change … when such changes occur, the model needs to adapt to the changes, which can be accomplished by continuous training, Para. [0186] of CHAU); recording, for each state machine, a state transition log comprising an ordered sequence of timed actions (tool system controllers 348 record lot history, detailed event logs, lot-based alarms, time-based alarms, tool controller health, parts tracking, component history, material scheduling, Para. [0112] of CHAU; See also tool system controllers 348-1, 348-2, … 348-N, FIG. 3 & Para. [0111] of CHAU; See also Paras. [0102] & [0164] of CHAU) performed by that state machine during simulated processing of the workpiece order (discrete event simulator 1202 can simulate a wafer processing sequence that takes about an hour in less than a minute, Para. [0164] of CHAU; See also the model generator 408 can identify and store a set of optimum configurations and run scenarios per tool and store the set for automatic selection … the simulator 404 can generate training data for various combinations of tool configurations, wafer-flow types, recipe/WAC times, and run scenarios, Para. [0132] of CHAU); repeating the steps of determining the next timed action, incrementing the simulation, updating the software model and the simulation controller, and recording the state transition log for each state machine, until all of the workpieces have been processed (models generated using machine learning can produce reliable, repeatable decisions and results, and uncover hidden insights through learning from historical relationships and trends in the data, Para. [0149] of CHAU; See also discrete event simulator 1202 repeats steps 1304-1312 until the final state is reached, Para. [0170]; See also processing chambers in the substrate processing tools usually repeat the same task on multiple substrates, Para. [0005] of CHAU; [Examiner has cited to citations in CHAU teaching repeating of operations, and the determining, incrementing and updating have been mapped above]; Regarding “until all of the workpieces have been processed”, see total processing time for all the wafers, Para. [0128] of CHAU; [all of the wafers is interpreted to correspond to all of the workpieces, and total processing time for all of the wafers/workpieces is interpreted to correspond to an indication that all of the wafers have been processed]).
Although CHAU outputs, from a neural network, a predicted program execution time and a total processing time for all wafers (Paras. [0128] & [0189] of CHAU), which is similar/same as simulated completion time, and vaguely discusses remote access for monitoring performance metrics (Para. [0224] of CHAU), CHAU does not appear to explicitly discuss outputting, for review by a user, a simulated completion time for the simulation, and the state transition log for each state machine, each state transition log representing execution of the ordered sequence of timed actions performed by the respective state machine during simulated processing of the workpiece order, wherein the simulated completion time and the state transition log provide an indication of production efficiency of the manufacturing cell, including non-linear inefficiencies arising during processing of the workpiece order, and thereby support determination of adjustments to at least one of the following: a physical layout of workers in the manufacturing cell, a worker schedule, and/or a worker behavior, to thereby increase worker efficiency.
CHIBA, however, teaches outputting, for review by a user, a processing of the workpiece order, and the state transition log for each state machine, each state transition log representing execution of the ordered sequence of timed actions performed by the respective state machine during (FIG. 7 of CHIBA shows a time chart “representing individual manufacturing processes based on the manufacturing results, and is exemplary display of visualized manufacturing statuses of products manufactured through a plurality of manufacturing processes in order”, Paras. [0052]-[0054] of CHIBA; See also the machine operation state, the machine event, and the maintenance history are displayed on the timeline created from the viewpoint of the products of interest, Para. [0073] of CHIBA; See also the manufacturing results 122 include information about products manufactured in manufacturing units (such as the start time, end time, and processing period of each of processes constituting the manufacturing line), statuses of machines in operation, Para. [0026] of CHIBA), wherein the (Examiner’s note: this “wherein” and “thereby” limitation is interpreted as simply stating what can be done with the order completion time (and the log/history), i.e., identify/indicate efficiency (and support schedule decision making), which would be inherent (i.e., the faster the job/processing completes (i.e., the lower the order completion time), the more efficient the manufacturing cell is); nonetheless, CHIBA teaches the operation efficiency may change when an operation method is modified, or the operation efficiency may change when the procedure of operation methods is modified … an operation method change history (changes in procedure or operation details) can be accumulated … for example, the Method of the process characteristic factor is linked to the manufacturing recipe result data illustrated in FIG. 3, Para. [0041] of CHIBA; See also when the works in each process are performed with no problem, the product moves smoothly and the bars overlap evenly … however, when the smooth work flow is prevented for any reason, the bars overlap unevenly and the non-smooth work has a darker or lighter color than the remaining works … this allows the user to know the work status intuitively … in addition, the user can see the relationship between the manufacturing work periods of the product shown by the bars and the 5M1E change points, Para. [0102] of CHIBA).
CHIBA is analogous prior art because it is from the “same field of endeavor” as the claimed invention. See MPEP 2141.01(a)(I) and Para. [0006] of CHIBA (information processing of manufacturing log information about manufacturing of products grouped in manufacturing units). Before the effective filing date of the claimed invention, it would have been obvious for one of ordinary skill in the art, having the teachings of CHAU and CHIBA before him or her, to modify CHAU to include output/display manufacturing recipe time-series data as taught by CHIBA (including the simulated manufacturing recipes of CHAU). The suggestion/motivation for doing so would have been to allow the user to know the work status intuitively (Para. [0103] of CHIBA) by visibly displaying changes in process characteristic factors caused during one or more of manufacturing processes of products manufactured through the manufacturing processes (Para. [0005] of CHIBA).
Regarding claim 11, CHAU discloses a method of simulating, via a production utilization planner (PUP) core (model for scheduling [planning] to achieve highest tool/fleet utilization, shortest wait times, and fastest throughput, Para. [0089] of CHAU), the processing of workpieces in a workpiece order (instructions are configured to simulate … a plurality of processing scenarios and scheduling parameters for the plurality of processing scenarios for processing the semiconductor substrates in the plurality of processing chambers according to the recipe, Para. [0006] of CHAU; See also simulator 1404 simulates the tool configuration and simulates the processing of the wafers [workpieces] in the tool, Para. [0196] of CHAU; [wafers are interpreted as workpieces in this context]; [Examiner’s Note: the simulation “by performing the following steps” is disclosed when “the following steps” are disclosed]; See also regarding arranged in an order/schedule: “predict, using the further trained model, second processing times, second transfer times, and a second route for processing the additional semiconductor substrates in the tool; and a second time to schedule a next set of semiconductor substrates for processing in the tool”, Para. [0048] of CHAU) by a manufacturing cell (semiconductor manufacturers use one or more substrate processing tools to perform deposition, etching, cleaning, and/or other substrate treatments during fabrication of semiconductor wafers, Para. [0004] of CHAU; See also system for processing semiconductor substrates in a tool comprising a plurality of processing chambers configured to process the semiconductor substrates according to a recipe, Para. [0006] of CHAU; [processing chambers for processing semiconductor substrates are interpreted as manufacturing cells), the method comprising: creating, at initiation of a simulation, an instance of a simulation controller (simulator 1404 may be implemented using a computing device such as a computer … storing one or more computer programs that simulate the operating and processing environment of a tool (e.g., the tool 1406) on the computer … the computer programs additionally comprise instructions for generating, training, and validating the neural networks 1410 and the scheduler level neural network 1412 of the model 1402 on the simulator 1404 as explained below with reference to FIGS. 15A and 15B, Para. [0191] of CHAU; [Examiner’s Note: Applicant’s claim limitation of “creating … an instance of a simulation controller” is interpreted as creating a software instance that controls simulation [and not a piece of hardware]) and an instance of a software model of the manufacturing cell (a model for scheduler pacing is built using nested neural networks or other machine learning algorithms … the model is initially built, trained, and tested offsite using simulation, Para. [0181] of CHAU; See also the model is continually refined and trained further onsite on the actual tool by incrementally using data streams from the tool to make further adjustments to the model that reflect the tool-specific and recipe-specific robot transfer times and that compensate for any process drift … the onsite training also adjusts the model for any recipe changes and/or tool hardware changes, Para. [0181] of CHAU; See also discrete event simulator 1202 communicates with a tool's system software (e.g., the controller 138 of a tool 100 shown in FIG. 1 that executes the tool's system software) and the reinforcement learning model 1204 (e.g., the model generated by the system 400 shown in FIG. 4), Para. [0156] of CHAU; [because the model is tool-specific, and the tool’s system software includes a controller, the creation/building of the model is interpreted to also create an instance of a simulation tool controller]) having state machines (the model 1204 includes a deep neural network that is trained using a reinforcement learning method as explained in further detail with reference to FIG. 13, reinforcement learning involves an agent, a set of states S and a set A of actions per state, and by performing an action ‘a’ from the set A, the agent transitions from state to state, Para. [0165] of CHAU; See also the reinforcement learning method used by the model 1204 can include Q-learning … Q-learning finds an optimal policy for any finite Markov decision process (FMDP), Para. [0166]; [a Markov decision process is interpreted as defining a set of states and transition between them [i.e., a state machine]]) configured to perform timed actions on the workpieces (the model is trained using data collected from preventive maintenance operations (PMs), recipe times, and wafer-less auto clean (WAC) times as inputs to the model, Para. [0081] of CHAU; [wafers and/or substrates are interpreted as the workpieces in this semiconductor/etching context]; See also wafer wait times and process time recipe, Para. [0080] of CHAU; See also one neural network is used per robot to predict the transfer times for each robot, Para. [0179]; See also wait time is an amount of time wafers have to wait after processing of the wafers is completed in a processing module until the processing of the wafers can begin in a next processing module, Para. [0188] of CHAU; See also the predetermined criteria may include determining whether the model outputs ensure a small wafer idle time, Para. [0146] of CHAU; [Examiner’s Note: etching/processing/machining time, transfer/transit time, wait time, clean time and idle time are the same and/or similar to the states/processes/timed actions discussed in Applicant’s specification at Para. [0067], which recites “AGV 420 has the states of ‘idle,’ ‘charging,’ ‘transiting/unload,’ ‘waiting/pickup,’ ‘picking up,’ ‘transiting/loaded,’ ‘waiting/drop off,’ and ‘dropping off.’) and Para. [0093], which recites “[e]xamples of timed actions performed by workers 258 include machining a workpiece 452 via a robotic device 262 in the machining subcell 402, cleaning a workpiece 452”]), and each state machine has a state during the timed actions (as discussed above, Paras. [0080], [0081], [0146], [0179] and [0188] of CHAU disclose preventive maintenance operations (PMs), clean times, idle times, wait times, process time recipe and recipe times, transfer times), and a state transition from state to state (agent transitions from state to state, Para. [0165] of CHAU); determining a next timed action to be performed by the state machines (instructions are configured to, for each of the plurality of states, send to the model a current state of the plurality of states and multiple schedulable operations to progress to a next state of the plurality of states, receive from the model a best operation from the multiple schedulable operations selected by the model based on the current state to progress to the next state, and simulate execution of the best operation to simulate progression to the next state, Para. [0027] of CHAU; See also model 1204 uses the memorized best next operation for each state when that particular state occurs in the tool during actual wafer processing, Para. [0170] of CHAU); incrementing the simulation to the next timed action (the instructions are configured to further train the model incrementally based on data generated during the processing of the semiconductor substrates and the additional semiconductor substrates in the semiconductor processing tool, Para. [0056] of CHAU; See also the model is continually refined and trained further onsite on the actual tool by incrementally using data streams from the tool to make further adjustments to the model that reflect the tool-specific and recipe-specific robot transfer times and that compensate for any process drift, Para. [0181] of CHAU; Regarding “next state”, see also instructions are configured to, for each of the plurality of states, send to the model a current state of the plurality of states and multiple schedulable operations to progress to a next state of the plurality of states, receive from the model a best operation from the multiple schedulable operations selected by the model based on the current state to progress to the next state, and simulate execution of the best operation to simulate progression to the next state, Para. [0027] of CHAU; See also model 1204 uses the memorized best next operation for each state when that particular state occurs in the tool during actual wafer processing, Para. [0170] of CHAU); updating the software model and the simulation controller each time a state machine performs a timed action (the training of the model incrementally discussed above in relation to Paras. [0056] and [0181] of CHAU corresponds to updating the model; See also discrete event simulator 1202 communicates with a tool's system software (e.g., the controller 138 of a tool 100 shown in FIG. 1 that executes the tool's system software) and the reinforcement learning model 1204 (e.g., the model generated by the system 400 shown in FIG. 4), Para. [0156] of CHAU; See also third phase includes online real-time and unsupervised learning … continuous (i.e., ongoing) training is needed since process recipes and/or hardware can change … when such changes occur, the model needs to adapt to the changes, which can be accomplished by continuous training, Para. [0186] of CHAU); recording, for each state machine, a state transition log comprising an ordered sequence of timed actions (tool system controllers 348 record lot history, detailed event logs, lot-based alarms, time-based alarms, tool controller health, parts tracking, component history, material scheduling, Para. [0112] of CHAU; See also tool system controllers 348-1, 348-2, … 348-N, FIG. 3 & Para. [0111] of CHAU; See also Paras. [0102] & [0164] of CHAU) performed by that state machine during simulated processing of the workpiece order (discrete event simulator 1202 can simulate a wafer processing sequence that takes about an hour in less than a minute, Para. [0164] of CHAU; See also the model generator 408 can identify and store a set of optimum configurations and run scenarios per tool and store the set for automatic selection … the simulator 404 can generate training data for various combinations of tool configurations, wafer-flow types, recipe/WAC times, and run scenarios, Para. [0132] of CHAU); repeating the steps of determining the next timed action, incrementing the simulation, and updating the software model and the simulation controller, until all of the workpieces have been processed (models generated using machine learning can produce reliable, repeatable decisions and results, and uncover hidden insights through learning from historical relationships and trends in the data, Para. [0149] of CHAU; See also discrete event simulator 1202 repeats steps 1304-1312 until the final state is reached, Para. [0170]; See also processing chambers in the substrate processing tools usually repeat the same task on multiple substrates, Para. [0005] of CHAU; [Examiner has cited to citations in CHAU teaching repeating of operations, and the determining, incrementing and updating have been mapped above]; Regarding “until all of the workpieces have been processed”, see total processing time for all the wafers, Para. [0128] of CHAU; [all of the wafers is interpreted to correspond to all of the workpieces, and total processing time for all of the wafers/workpieces is interpreted to correspond to an indication that all of the wafers have been processed]).
Although CHAU outputs, from a neural network, a predicted program execution time and a total processing time for all wafers (Paras. [0128] & [0189] of CHAU), which is similar/same as simulated completion time, and vaguely discusses remote access for monitoring performance metrics (Para. [0224] of CHAU), CHAU does not appear to explicitly disclose outputting, for review by a user, a simulated completion time for the simulation, and the state transition log for each state machine, each state transition log representing execution of the ordered sequence of timed actions performed by the respective state machine during simulated processing of the workpiece order, wherein the simulated completion time and the state transition log for each state machine provide an indication of production efficiency of the manufacturing cell, including non-linear inefficiencies arising during processing of the workpiece order, and thereby support determination of adjustments to at least one of the following: a physical layout of workers in the manufacturing cell, a worker schedule, and/or a worker behavior, to thereby increase worker efficiency.
CHIBA, however, teaches outputting, for review by a user, a processing of the workpiece order, and the state transition log for each state machine, each state transition log representing execution of the ordered sequence of timed actions performed by the respective state machine during (FIG. 7 of CHIBA shows a time chart “representing individual manufacturing processes based on the manufacturing results, and is exemplary display of visualized manufacturing statuses of products manufactured through a plurality of manufacturing processes in order”, Paras. [0052]-[0054] of CHIBA; See also the machine operation state, the machine event, and the maintenance history are displayed on the timeline created from the viewpoint of the products of interest, Para. [0073] of CHIBA; See also the manufacturing results 122 include information about products manufactured in manufacturing units (such as the start time, end time, and processing period of each of processes constituting the manufacturing line), statuses of machines in operation, Para. [0026] of CHIBA), wherein the (Examiner’s note: this “wherein” and “thereby” limitation is interpreted as simply stating what can be done with the order completion time (and the log/history), i.e., identify/indicate efficiency (and support schedule decision making), which would be inherent (i.e., the faster the job/processing completes (i.e., the lower the order completion time), the more efficient the manufacturing cell is); nonetheless, CHIBA teaches the operation efficiency may change when an operation method is modified, or the operation efficiency may change when the procedure of operation methods is modified … an operation method change history (changes in procedure or operation details) can be accumulated … for example, the Method of the process characteristic factor is linked to the manufacturing recipe result data illustrated in FIG. 3, Para. [0041] of CHIBA; See also when the works in each process are performed with no problem, the product moves smoothly and the bars overlap evenly … however, when the smooth work flow is prevented for any reason, the bars overlap unevenly and the non-smooth work has a darker or lighter color than the remaining works … this allows the user to know the work status intuitively … in addition, the user can see the relationship between the manufacturing work periods of the product shown by the bars and the 5M1E change points, Para. [0102] of CHIBA).
CHIBA is analogous prior art because it is from the “same field of endeavor” as the claimed invention. See MPEP 2141.01(a)(I) and Para. [0006] of CHIBA (information processing of manufacturing log information about manufacturing of products grouped in manufacturing units). Before the effective filing date of the claimed invention, it would have been obvious for one of ordinary skill in the art, having the teachings of CHAU and CHIBA before him or her, to modify CHAU to include output/display manufacturing recipe time-series data as taught by CHIBA (including the simulated manufacturing recipes of CHAU). The suggestion/motivation for doing so would have been to allow the user to know the work status intuitively (Para. [0103] of CHIBA) by visibly displaying changes in process characteristic factors caused during one or more of manufacturing processes of products manufactured through the manufacturing processes (Para. [0005] of CHIBA).
Regarding claim 12, CHAU as modified by CHIBA discloses the method of Claim 11, wherein the state machines comprise at least one of a technician and a robotic device (the model is continually refined and trained further onsite on the actual tool by incrementally using data streams from the tool to make further adjustments to the model that reflect the tool-specific and recipe-specific robot transfer times and that compensate for any process drift … the onsite training also adjusts the model for any recipe changes and/or tool hardware changes, Para. [0181] of CHAU; See also one neural network is used per robot to predict the transfer times for each robot, Para. [0179] of CHAU).
Claim 13 has substantially similar limitations as recited in claim 2, except it depends from parent base claim 11; therefore, it is rejected under 35 U.S.C. § 103 using CHAU and CHIBA, as applied in claim 2.
Claim 14 has substantially similar limitations as recited in claim 3, except it depends (indirectly) from parent base claim 11; therefore, it is rejected under 35 U.S.C. § 103 using CHAU and CHIBA, as applied in claim 3.
Claim 16 has substantially similar limitations as recited in claim 5, except it depends from parent base claim 11; therefore, it is rejected under 35 U.S.C. § 103 using CHAU and CHIBA, as applied in claim 5.
Claim 17 has substantially similar limitations as recited in claim 6, except it depends (indirectly) from parent base claim 11; therefore, it is rejected under 35 U.S.C. § 103 using CHAU and CHIBA, as applied in claim 6.
Claim 18 has substantially similar limitations as recited in claim 7, except it depends (indirectly) from parent base claim 11; therefore, it is rejected under 35 U.S.C. § 103 using CHAU and CHIBA, as applied in claim 7.
Claim 20 has substantially similar limitations as recited in claim 9, except it depends from parent claim 11; therefore, it is rejected under 35 U.S.C. § 103 using CHAU and CHIBA, as applied in claim 9.
Claims 4 and 15 are rejected under 35 U.S.C. § 103 as being unpatentable over CHAU et al. (U.S. Patent Application Publication No. 2022/0171373 A1) in view of CHIBA (U.S. Patent Application Publication No. 2024/0210927 A1), and further in view of BHATTACHARYA (U.S. Patent Application Publication No. 2021/0241859 A1).
Regarding claim 4, CHAU as modified by CHIBA discloses the PUP core of Claim 3, wherein the instructions, when executed by the processor, cause the PUP core to perform as: a controller analysis tool, coupled to a plurality of simulation controllers (processing chamber controllers 130 associated with the processing chambers 104 generally follow a recipe that specifies the timing of steps, process gases to be supplied, temperature, pressure, RF power, and so on, Para. [0094] of CHAU), each of the simulation controllers having a different set of rules for determining the order in which the timed actions are performed on the workpieces (a recipe defines sequencing, operating temperatures, pressures, gas chemistry, plasma usage, parallel modules, periods for each operation or sub-operation, substrate routing path, and/or other parameters, and the substrates may be transferred between two or more processing chambers in a particular sequence to undergo different treatments, Para. [0005] of CHAU; See also recipes with more processing layers can have longer processing times, Para. [0175] of CHAU; [Paras. [0005] & [0175] of CHAU indicate that there are recipes with different processing layers, and the recipes defines the sequences/order; hence it is interpreted that the different recipes with different processing layers have different processing sequences/orders]), wherein the controller analysis tool evaluates the effect of each one of the simulation controllers on the completion time for processing the workpieces, by performing the following ([Examiner’s Note: the evaluation “by performing the following” is disclosed when “the following [steps]” are disclosed]; See also each model is trained on one partition and is evaluated on the remaining partitions ... validation scores are assigned for each evaluation, Para. [0147] of CHAU; See also a recipe defines sequencing, operating temperatures, pressures, gas chemistry, plasma usage, parallel modules, periods for each operation or sub-operation, substrate routing path, and/or other parameters, and the substrates may be transferred between two or more processing chambers in a particular sequence to undergo different treatments, Para. [0005] of CHAU; See also recipes with more processing layers can have longer processing times, Para. [0175] of CHAU; [Paras. [0005] & [0175] of CHAU indicate that there are recipes with different processing layers, and the recipes defines the sequences/order; [hence it is interpreted that the different recipes with different processing layers have different processing sequences/orders]): performing a batch analysis for simulating a plurality of workpiece orders (batch (multiple substrates) processing tools used for multiple parallel material deposition processes with restrictions on wafer wait times, pacing a scheduler of a tool to achieve best throughput and least wafer wait time, Para. [0080] of CHAU; See also to improve the accuracy of scheduler pacing used in tools for multiple parallel material deposition (e.g., multi-layer plating) processes, the present disclosure proposes a machine learning method based on nested neural networks for accurately predicting scheduler pacing for different processes, Para. [0089] of CHAU), using one of the simulation controllers previously unused in a simulation ([Examiner’s Note: Claim 4 and 15’s claim limitation of “one of the simulation controllers previously unused in a simulation” is interpreted to be any simulation controller because “a simulation” could be any simulation, such “a simulation” scheduled in the future, or “a simulation” related to driving a vehicle. “A simulation” is a broad term that could be any simulation]); saving, for each workpiece order simulated via the batch analysis, the simulated completion time using the simulation controller (the instructions are configured to train the model, using historical data regarding processing of the semiconductor substrates received from the tool and by simulating a plurality of processing scenarios for the tool, to predict optimum scheduling parameters for processing the semiconductor substrate in the plurality of processing chambers according to the recipe, Para. [0028] of CHAU; [training the model using simulated data is interpreted as corresponding to and/or inherently requiring saving the data]; See also the simulated data (of simulated processing scenarios) includes simulated completion time(s) using the simulation controller: recipes with more processing layers can have longer processing times, Para. [0175] of CHAU); determining, for the simulation controller, the workpiece order that has a shorter simulated completion time than 90 percent of all of the workpiece orders simulated using the simulation controller (a design may be globally optimum if the design is optimal with respect to possible design options for one or more criteria. In embodiments, a design may be globally optimum if the design is optimal with respect to a large percentage (such as 80% or more) of possible design options for one or more criteria, Para. [0148] of BHATTACHARYA; [80% or more is interpreted as including 90 percent]; See also concentrating recommendations and design analysis on designs on or near the convex hull greatly reduces the number of designs that need to be examined … in some cases only one or two percent of the total simulated designs need to be considered when initial design recommendations provided by the platform are on or near the convex hull, Para. [0755] of BHATTACHARYA; See also designs may minimize duration: trial designs that maximize or minimize other design goals, such as the probability of success (POS), discounted cost, and study duration, Para. [0347] of BHATTACHARYA); repeating, for each simulation controller until all simulation controllers have results, the steps of performing the batch analysis, saving the simulated completion time (models generated using machine learning can produce reliable, repeatable decisions and results, and uncover hidden insights through learning from historical relationships and trends in the data, Para. [0149] of CHAU; See also discrete event simulator 1202 repeats steps 1304-1312 until the final state is reached, Para. [0170] of CHAU; See also processing chambers in the substrate processing tools usually repeat the same task on multiple substrates, Para. [0005] of CHAU; [Examiner has cited to citations in CHAU teaching repeating of operations, which could include the modified functions of performing the batch analysis, saving the simulated completion time, and determining the workpiece order that has the shorter simulated completion time); performing, for each simulation controller, the uncertainty analysis on each workpiece order that has the shorter simulated completion time (Q-learning can handle problems with stochastic transitions and rewards without requiring adaptations … Q-learning finds an optimal policy for any finite Markov decision process (FMDP) … Q-learning maximizes the expected value of the total reward over all successive steps, starting from the current state, Para. [0166] of CHAU; [Examiner’s note: stochastic means randomly determined and a Markov process is a stochastic/random process]; See also the instructions are configured to adjust the model for any changes to the recipe, the semiconductor processing tool, or both, Para. [0057]; See also the predetermined criteria include determining whether the model can compensate for tool-to-tool variations and for same-tool performance drift, and whether the model can optimize for unavailable PMs, Para. [0146]; [variations and performance drift are interpreted as changes to the tool’s performance, i.e., changes to the time of the processes/timed actions]; See also next sentence: the predetermined criteria may include determining whether the model outputs ensure a small wafer idle time (e.g., less than 2%) and high manufacturing efficiency (e.g., greater than 97%), Para. [0146]; See also next paragraph: FIG. 8 shows a method 800 for validating the model in further detail … the total dataset is divided into one final test set and N other subsets, where N is an integer greater than one … each model is trained on all but one of the subsets to get N different estimates of the validation error rate, Para. [0148] of CHAU; See also simulating the plurality of processing scenarios includes data generated based on a configuration of the tool, wafer-flow types, run scenarios, recipe times, and wafer-less auto clean times obtained from the tool, Para. [0043] of CHAU; See also additional training data are generated using simulations to cover various processing scenarios used by the semiconductor manufacturers using the tools, Para. [0082] of CHAU; See also self-exploration process uses the discrete event simulator to automate efforts to find the best possible way to operate a system (e.g., to find the best path in which to move a wafer through a tool) at optimum throughput performance, Para. [0086] of CHAU; See also success criteria can also include whether wafer idle times are less than a small percentage (e.g., 2%) of total processing time for all the wafers, Para. [0128]; See also the nested neural network based model is initially designed and trained offline using simulated data and then trained online using real tool data for predicting wafer routing path and scheduling, Para. [0172] of CHAU; See also discrete event simulator 1202 can simulate a wafer processing sequence that takes about an hour in less than a minute, Para. [0164] of CHAU; See also using the method, a model is developed and trained initially offline using simulation and then online using the actual tool for predicting wafer routing path and scheduling to achieve highest tool/fleet utilization, shortest wait times, and fastest throughput, Para. [0089] of CHAU).
CHAU as modified by CHIBA does not appear to explicitly disclose determining, for the simulation controller, the workpiece order that has a shorter simulated completion time than 90 percent of all of the workpiece orders simulated using the simulation controller; repeating, for each simulation controller until all simulation controllers have results, determining the workpiece order that has the shorter simulated completion time; and identifying the simulation controller that results in the shortest simulated completion time.
BHATTACHARYA, however, teaches determining, for the simulation controller, the workpiece order that has a shorter simulated completion time than 90 percent of all of the workpiece orders simulated using the simulation controller (a design may be globally optimum if the design is optimal with respect to possible design options for one or more criteria … in embodiments, a design may be globally optimum if the design is optimal with respect to a large percentage (such as 80% or more) of possible design options for one or more criteria, Para. [0148] of BHATTACHARYA; [80% or more is interpreted as including 90 percent]; See also concentrating recommendations and design analysis on designs on or near the convex hull greatly reduces the number of designs that need to be examined … in some cases only one or two percent of the total simulated designs need to be considered when initial design recommendations provided by the platform are on or near the convex hull, Para. [0755] of BHATTACHARYA; See also designs may minimize duration: trial designs that maximize or minimize other design goals, such as the probability of success (POS), discounted cost, and study duration, Para. [0347] of BHATTACHARYA); repeating, for each simulation controller until all simulation controllers have results, determining the workpiece order that has the shorter simulated completion time (processes may be repeated, Paras. [0336], [0453] & [0532] of BHATTACHARYA); and identifying the simulation controller that results in the shortest simulated completion time (a user may have previously determined the globally optimum design with respect to shortest duration and wish to do so again for the second globally optimum design, Para. [0537] of BHATTACHARYA; [the performance criteria of BHATTACHARYA could be applied as performance criteria in the simulations of CHAU]; See also using the method, a model is developed and trained initially offline using simulation and then online using the actual tool for predicting wafer routing path and scheduling to achieve highest tool/fleet utilization, shortest wait times, and fastest throughput, Para. [0089] of CHAU; [the fastest throughput is interpreted to correspond to a shortest simulated completion time]).
BHATTACHARYA is analogous prior art because it is from the “same field of endeavor” as the claimed invention. See MPEP 2141.01(a)(I) and Para. [0010] of BHATTACHARYA (evaluating and optimizing resource availability). Before the effective filing date of the claimed invention, it would have been obvious for one of ordinary skill in the art, having the teachings of CHAU, CHIBA and BHATTACHARYA before him or her, to modify CHAU as modified by CHIBA to include identifying the controller providing the shortest completion time as taught by BHATTACHARYA (including the simulated manufacturing recipes of CHAU). The suggestion/motivation for doing so would have been to evaluate hundreds, thousands, or even millions of selection options and may be used to find the optimal or near-optimal resource availability (Para. [0010] of BHATTACHARYA).
Claims 15 has substantially similar limitations as recited in claim 4, except it depends (indirectly) from parent base claim 11; therefore, it is rejected under 35 U.S.C. § 103 using CHAU, CHIBA and BHATTACHARYA, as applied in claim 4.
Claims 8 and 19 are rejected under 35 U.S.C. § 103 as being unpatentable over CHAU et al. (U.S. Patent Application Publication No. 2022/0171373 A1) in view of CHIBA (U.S. Patent Application Publication No. 2024/0210927 A1), and further in view of HARAMATI et al. (U.S. Patent Application Publication No. 2021/0157978 A1) and BAHRAMSHAHRY et al. (U.S. Patent Application Publication No. 2020/0026564 A1).
Regarding claim 8, CHAU as modified by CHIBA discloses the PUP core of Claim 1, wherein the instructions, when executed by the processor, cause the PUP core to perform as a simulation and analysis module continuously evaluating the status of the simulation prior to simulating all of the workpieces in the workpiece order (the model is continually refined and trained further onsite on the actual tool by incrementally using data streams from the tool to make further adjustments to the model that reflect the tool-specific and recipe-specific robot transfer times and that compensate for any process drift, Para. [0181]; See also the training of the model incrementally discussed above in relation to Paras. [0056] and [0181] of CHAU corresponds to updating the model; See also discrete event simulator 1202 communicates with a tool's system software (e.g., the controller 138 of a tool 100 shown in FIG. 1 that executes the tool's system software) and the reinforcement learning model 1204 (e.g., the model generated by the system 400 shown in FIG. 4), Para. [0156]; See also third phase includes online real-time and unsupervised learning … continuous (i.e., ongoing) training is needed since process recipes and/or hardware can change … when such changes occur, the model needs to adapt to the changes, which can be accomplished by continuous training, Para. [0186]; See also model generator 408 can apply the selected machine learning method to generate a model based on data collected from multiple tool configurations and run scenarios to check if prediction accuracy can meet success criteria … the success criteria can also include whether wafer idle times are less than a small percentage (e.g., 2%) of total processing time for all the wafers, and whether a manufacturing efficiency (actual/theoretical cycle time) can be high (e.g., greater than 97%) for each recipe, Para. [0128]; [the percentage of wafer idle times of total processing time and actual cycle time divided by theoretical cycle time are interpreted as statistics]).
CHAU as modified by CHIBA appears to fail to explicitly disclose performing the following after each update of the software model: adding the duration of the most recently completed simulated timed action to a running total of the duration of the simulated timed actions performed up to the most recent update of the software model; determining, at that point in the simulation, a statistically-modeled best-case interim time, calculated as a function of a statistically-modeled best-case completion time and the sum of the duration of every timed action required to complete the workpiece order; calculating the difference between the statistically-modeled best-case interim time to the running total of the duration of the simulated timed actions; and terminating the simulation of the workpiece order if the difference is greater than 50 percent of the statistically-modeled best-case interim time.
HARAMATI, however, is in the same field of optimizing workflows/schedules (Para. [0002 of HARAMATI) and teaches performing the following after each update of the software model: adding the duration of the most recently completed timed action to a running total of the duration of the timed actions performed up to the most recent update of the software model (project time tracking may include one or more of measuring, storing, managing, analyzing, prioritizing, recording, allocating, and organizing time, or any other mechanism for capturing of time, Para. [0679] of HARAMATI; See also next sentence: the time may be measured on an individual basis in order to capture the effort, costs, or workload of a particular individual or group of individuals, Para. [0679] of HARAMATI; See also next sentence: the time may also be measured and associated with an individual project to capture the effort, costs, or workload required by a particular project, Para. [0679] of HARAMATI; See also next sentence: additionally, the time may be measured on an individual basis and then aggregated in order to capture the effort, costs, or workload of a group of individuals as required by a particular project or projects, as disclosed herein, Para. [0679] of HARAMATI).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the invention to modify the simulation timed actions/states of CHAU (as modified by CHIBA) to use the time tracking features of HARAMATI for the purpose of capturing the effort, costs, or workload required by a particular project, person and/or group (See Para. [0679 of HARAMATI).
Also, BAHRAMSHAHRY is in the same field of optimizing workload scheduling (Paras. [0004]-[0006] of BAHRAMSHAHRY) and teaches determining, at that point in the simulation, a statistically-modeled best-case interim time, calculated as a function of a statistically-modeled best-case completion time and the sum of the duration of every timed action required to complete the workpiece order (the planner 127 of the scheduler may be utilized to allocate resource for the most efficient utilization or for best performance (e.g., the fastest execution), Para. [0114]; See also while passing tests may take a second each, and thus 1000 seconds total (approximately 16 minutes total), a workload having 1000 failing tests, each of which must wait 30 seconds, results in a total processing time of approximately 8 hours, which will incur a much larger dollar cost or compute resource consumption cost than is anticipated for such a workload, Para. [0627]); calculating the difference between the statistically-modeled best-case interim time to the running total of the duration (the planner 127 of the scheduler may be utilized to allocate resource for the most efficient utilization or for best performance (e.g., the fastest execution), Para. [0114]; See also while passing tests may take a second each, and thus 1000 seconds total (approximately 16 minutes total), a workload having 1000 failing tests, each of which must wait 30 seconds, results in a total processing time of approximately 8 hours, which will incur a much larger dollar cost or compute resource consumption cost than is anticipated for such a workload, Para. [0627]) of the simulated timed actions (iterating through the produce, calculate, select, and plan operations to yield a scheduling plan based on SLTs for the simulated workload tasks and the simulated data representing the additional computing hardware. Such a utility may be utilized to evaluate “what if” scenarios, Para. [0130]; See also next sentence: for instance, to evaluate whether additional computing hardware will sufficiently meet anticipated demand or sufficiently meet actual historical demand, and because the scheduler simply pulls data from the local cache, it is agnostic to the fact that the data in local cache is being provided by a simulator rather than being actual production data, Para. [0130]); and terminating the simulation of the workpiece order if the difference is greater than 50 percent of the statistically-modeled best-case interim time (a watchdog ROI engine 3195, which constantly evaluates all running jobs and if a running job is evaluated by the watchdog and determined to have an ROI below a threshold then the watchdog will issue the termination instructions to terminate the executing and currently running workload, Para. [0623]; See also the scheduling service may be configured to not pick up work for execution on the basis of cost, Para. [0627]; See also next sentence: for example, a workload with 1000's of tests may utilize timeouts, such as 30 seconds, but each test runs very quickly when passing, Para. [0627]; See also next sentence: however, if a bad code submission is received or a bad change list is being processed, then many of the tests or even every test may fail, thus causing every test to wait for its timeout which is much more CPU intensive and costly in terms of time and dollars as the workload must wait for every failing test to reach its timeout, Para. [0627]; See also next sentence: thus, while passing tests may take a second each, and thus 1000 seconds total (approximately 16 minutes total), a workload having 1000 failing tests, each of which must wait 30 seconds, results in a total processing time of approximately 8 hours, which will incur a much larger dollar cost or compute resource consumption cost than is anticipated for such a workload, Para. [0627]; See also next sentence: therefore, the watchdog ROI engine 3195 which is analyzing currently executing workloads may perform its ROI analysis on the workload having the failing tests and affirmatively kill or terminate the execution to save cost and compute resource, Para. [0627]; See also next sentence: thus, where a catastrophic failure is identified by the watchdog ROI engine 3195, such a finding may dictate termination of the workload rather than permitting the workload to execute, Para. [0627]; [8 hours is “greater than 50 percent of” 16 minutes, and 30 seconds is “greater than 50 percent of” a (one) second]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the invention to modify the simulation method of CHAU (as modified by CHIBA) to use the features of the simulation method of BAHRAMSHAHRY for the purpose of efficiently using computing resources (See BAHRAMSHAHRY at Para. [0627]: by cutting the losses short for such a workload it is known already that there is a catastrophic failure and spending dollars to complete the remaining failing tests will not likely yield additional informational data points for the cost incurred, thus negating any potential ROI for the workload).
Claim 19 has substantially similar limitations as recited in claim 8, except it depends from parent base claim 11; therefore, it is rejected under 35 U.S.C. § 103 using CHAU, CHIBA, HARAMATI and BAHRAMSHAHRY, as applied in claim 8.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
LINDER et al. (US 20180107198 A1) published April 19, 2018. See, e.g., Para. [0130] teaches “Step 904 involves receiving at least one modification to the process via the interactive template”, Para. [0131] teaches “Step 906 involves gathering data related to the performance of at least one step of the process” and Para. [0132] teaches “Step 908 involves converting the gathered data related to the performance of the at least one step of the process into a format providing manufacturing results data … the data gathered in step 906 may be processed into a variety of data points useful for analyzing the performance of the process … for example, the gathered data may be converted into various derivatives, including but not limited to simple averages (i.e., a means(s)), weighted averages, standard deviations, etc.”; See also Para. [0024] teaches “testing the process includes simulating the execution of the process” and Para. [0025] teaches “the server is further configured to identify errors in the created process prior to execution or the runtime configuration”.
SAWYER et al. (US 20190278878 A1) published Sept. 12, 2019. See, e.g., Para. [0081] teaches “a simulation may determine runtimes and lead times, parameters depending on either runtimes or lead times, and other factors such as feasibility or availability of manufacturing devices, with the assumption that multiple parts may be simultaneously manufactured, either in entirety or for at least a stage of each part's respective manufacturing procedure; simulation may, for instance, reduce the runtime per part where multiple parts may be manufactured simultaneously.”
GRISWOLD et al (by Applicant: The Boeing Company) (US 20170235853 A1) published Aug. 17, 2017. See e.g., Para. [0030] teaches “computer processor 104, generates a simulated flow model 117 for the manufacturing facility based on the initial facility layout concept 114 (and/or the modified facility layout concept 115)” and Para. [0037] teaches “the simulated flow model 117 is satisfactory if the duration of the simulated flow is below a threshold amount of time”.
FAMA et al. (US 20190130329 A1) published May 2, 2019. See e.g., Para. [0024] teaches “example list of states includes available, busy, after-call work, and unavailable” and Para. [0098] teaches “to achieve acceptable performance, sampling may be performed, either randomly ordering the Activity Permutations or ordering the Activity Permutations via which Activities/Queues have the shortest service goal”.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN P HOCKER whose telephone number is (571)272-0501. The examiner can normally be reached Monday-Friday 9:00 AM - 5:00 PM EST.
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JOHN P. HOCKER
Examiner
Art Unit 2189
/JOHN P HOCKER/Examiner, Art Unit 2189
/REHANA PERVEEN/Supervisory Patent Examiner, Art Unit 2189
Prosecution Insights