Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on December 8, 2025 has been entered.
Response to Amendment
Amendment to claims 1, 8, 15, 16 and 20 submitted on December 8, 2025 is acknowledged and has since been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pille (US 20200161300 A1).
Regarding Claim 1, Pille teaches a device (100, see Fig. 6b), comprising:
a first power rail (181);
a second power rail (191);
a first Field Effect Transistor (110b, shown Fig. 1b) comprising a first gate (113) and wherein the first FET is connected to the first power rail (shown Figs. 6a-6b);
a second FET (110a) comprising a second gate (113, see also Fig. 1b), and wherein the second FET is connected to the second power rail (shown Figs. 6a-6b), wherein the first gate is different from the second gate (shown as separate gate structures in Fig. 1b); and
an insulator (112, shown Fig. 1b) separating the first FET from the second FET, wherein the insulator separates the first gate from the second gate (shown Fig. 6b), wherein the first power rail, the second power rail, the first gate, and the second gate are aligned on a shared axis, and wherein the first power rail and the second power rail are located on opposite sides of the device (shown Fig. 6b).
Regarding Claim 3, Pille teaches the device of claim 1, wherein the first power rail and the second power rail are disposed at a cell boundary (shown Fig. 6b).
Regarding Claim 5, Pille teaches the device of claim 1, wherein the first FET includes a first source contact (111, see Figs. 1a-1b) and a first drain contact (shown Fig. 1b) and wherein the second FET includes a second source contact (shown Fig. 1b, interpreted as a semiconductor portion between the first FET and second FET which acts as a drain for the first FET and a source for the second FET, see also [0071] and [0083]) and a second drain contact (114).
Regarding Claim 7, Pille teaches the device of claim 1, wherein the device comprises a stacked arrangement, wherein the first power rail is on a top side of the stacked arrangement, and wherein the second power rail is on a bottom side of the stacked arrangement (shown Fig. 6b).
Regarding Claim 8, Pille teaches the device of claim 1, , wherein the first FET and the second FET are either FinFET transistors or nanosheet transistors (see [0015]).
Regarding Claim 15, Pille teaches a device (100, shown Fig. 6b), comprising:
a first Field Effect Transistor (FET) (110b) comprising a first gate (113);
a second FET (110a) comprising a second gate (113, see Fig. 1b), wherein the first gate is aligned on a first axis (a vertical axis) with the second gate located on opposite sides on a plane (defined as a cross-sectional plane between the lower FET and upper FET) perpendicular to the first axis, wherein the first gate is different than the second gate;
a first power rail (181, shown Fig. 6b) connected to the first FET along the first axis; and
a second power rail (191) connected to the second FET along the first axis, wherein the first power rail and the second power rail are located on opposite sides of the device (shown Fig. 6b).
Regarding Claim 16, Pille teaches the device of claim 15, further comprising:
an insulator (112, shown Fig. 1b) separating the first FET from the second FET, wherein the insulator separates the first gate from the second gate (shown Fig. 1b), wherein the first FET projects in a first direction (upwards as shown in Fig. 1b) from the insulator and the second FET projects in a second direction (downwards), opposite to the first direction, from the insulator.
Regarding Claim 19, Pille teaches the device of claim 15, the device comprises a stacked arrangement, wherein the first power rail is on a top side of the stacked arrangement (shown Fig. 6b) and wherein the second power rail is on a bottom side of the stacked arrangement (shown Fig. 6b).
Regarding Claim 20, Pille teaches the device of claim 15, wherein the first FET and the second FET are either FinFET transistors or nanosheet transistors (see [0015]).
Claim(s) 2 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Pille (US 20200161300 A1) in further view of Peng (US 20220122971 A1).
Regarding Claim 2, Pille teaches the device of claim 1 but is silent regarding the resistance value between a first power rail and first FET and a second power rail and second FET.
Peng further suggests that tuning a resistance between a power rail and a FET is an effective way to reduce power consumption and optimize speed of the device (see [0045]).
As such, a first resistance between the first power rail and the first FET being substantially equal to a second resistance between the second power rail and the second FET would be obvious through routine optimization as this would advantageously minimize power consumption of the stacked FET structure as applied to Pille.
Furthermore, a modification of this kind may be patentable "if it ‘produce[s] a new and unexpected result which is different in kind and not merely in degree from the results of the prior art.”(see Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)). The original disclosure does not describe such a result of unexpected advantageous properties.
Regarding Claim 17, Pille teaches the device of claim 15 but is silent regarding the resistance value between a first power rail and first FET and a second power rail and second FET.
Peng further suggests that tuning a resistance between a power rail and a FET is an effective way to reduce power consumption and optimize speed of the device (see [0045]).
As such, a first resistance between the first power rail and the first FET being substantially equal to a second resistance between the second power rail and the second FET would be obvious through routine optimization as this would advantageously minimize power consumption of the stacked FET structure as applied to Pille.
Furthermore, a modification of this kind may be patentable "if it ‘produce[s] a new and unexpected result which is different in kind and not merely in degree from the results of the prior art.”(see Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)). The original disclosure does not describe such a result of unexpected advantageous properties.
More specifically, this optimization would teach a first contact connecting the first power rail to the first FET has a first resistance value and a second contact connecting the second FET to the second power rail has the first resistance value.
Claim(s) 4 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Pille (US 20200161300 A1) in further view of Masuoka (US 20160204251 A1).
Regarding Claim 4, Pille teaches the device of claim 1, wherein the first FET and the second FET are either n-type or p-type depending on device design (see [0040]). Pille does not explicitly teach a first FET being n-type and a second FET being p-type.
Masuoka teaches a similar vertically stacked FET configuration (shown Fig. 8) wherein a lower FET (116a) is an n-type FET and an upper FET (116b) is a p-type FET.
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the device of Pille to comprise oppositely doped transistors being vertically stacked as suggested by Masuoka as this configuration would provide a complementary FET with reduced circuit area (see Masuoka: [0008]), thus reducing overall size.
Regarding Claim 18, Pille teaches the device of claim 15, wherein the first FET and the second FET are either n-type or p-type depending on device design (see [0040]). Pille does not explicitly teach a first FET being n-type and a second FET being p-type.
Masuoka teaches a similar vertically stacked FET configuration (shown Fig. 8) wherein a lower FET (116a) is an n-type FET and an upper FET (116b) is a p-type FET.
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the device of Pille to comprise oppositely doped transistors being vertically stacked as suggested by Masuoka as this configuration would provide a complementary FET with reduced circuit area (see Masuoka: [0008]), thus reducing overall size.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/C.P.B./Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893