Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is in response to the application filed on 12/23/2025.
Claims 1-9, 11, 13-23 are pending and claims 10 and 12 are cancelled.
Claim Objections
Claims 5, 14 and 16 objected to because of the following informalities:
Regarding claim 5, it recites “The software according to claim 4”, however, claim 4 recites “software module”. Thus, the examiner recommends amending the claim to recite “The software module according to claim 4”.
Regarding claim 14, it recites “The software module according to claim 13”, however, claim 13 recites “the processing unit”. Thus, the examiner suggests amending the claim to recite “The processing unit according to claim 13”
Regarding claim 16, it recites “The software module according to claim 15”, however, claim 16 recites “the processing unit”. Thus, the examiner suggests amending the claim to recite “The processing unit according to claim 15”
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-3, 5-9, 11, 13-23 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Claim 5, this claim is within at least one of the four categories of patent eligible subject matter as it is directing to a method claim under Step 1.
However, the limitations to “generate a subset is comprised by an exploring process”, as drafted, recite functions that, under its broadest reasonable interpretation, covers functions that could reasonably be performed in the mind, including with the aid of pen and paper, but for the recitation of generic computer components. That is, the limitation as drafted, is a function that, under its broadest reasonable interpretation, recite the abstract idea of a mental process. The limitations encompass a human mind carrying out the function through observation, evaluation, judgment and /or opinion, or even with the aid of pen and paper. Thus, these limitations recite and fall within the “Mental Processes” grouping of abstract ideas under Prong 1 Step 2A.
Under Prong 2 Step 2A, this judicial exception is not integrated into a practical application. The claim recites the following additional elements “processing circuitry” “one or more interfaces”, “one or more interfaces configured to communicate with a processing unit”, “processing circuitry configured to control the one or more interfaces”, “receive information about a superset of a plurality of hardware microservices of at least one hardware component” and “provide information about the superset”. The “processing circuitry” “one or more interfaces” are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using a generic computer component, or merely a generic computer or generic computer components to perform the judicial exception. The addition elements “one or more interfaces configured to communicate with a processing unit”, “processing circuitry configured to control the one or more interfaces” are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using generic computer, and/or mere computer components. Further, “receive information about a superset of a plurality of hardware microservices of at least one hardware component”, “provide information about the superset” and “wherein providing information about the superset includes rendering the superset as a hierarchical tree” do nothing more than add insignificant extra solution activity to the judicial exception of merely send/receive and displaying data/information. Accordingly, the additional elements do not integrate the recited judicial exception into a practical application and the claim is therefore directed to the judicial exception. See MPEP 2106.05(g).
Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of the “processing circuitry” “one or more interfaces” amount to no more than mere instructions, or generic computer/computer components to carry out the exception. Furthermore, the limitations “receive information about a superset of a plurality of hardware microservices of at least one hardware component”, “provide information about the superset” and “wherein providing information about the superset includes rendering the superset as a hierarchical tree” have been identified by the courts as merely receiving/transmitting data and displaying data/information on a display which is well-understood, routine and conventional activity. See MPEP 2106.05(d). The recitation of generic computer instruction and computer components to apply the judicial exception, and merely displaying data do not amount to significantly more, thus, cannot provide an inventive concept. Accordingly, the claims are not patent eligible under 35 USC 101.
Even when considered in combination, these additional elements represent mere instructions to apply an exception with well understood, routine, and conventional insignificant extra-solution activity, which does not provide significantly more to the abstract idea. The claim is not patent eligible.
Claim 6 recites additional mental step of checking and mere data gathering step of receiving which does not integrate the abstract idea into a practical application nor amount to significantly more. Claim 7 further recites an additional mental step of synchronizing and a mere data gathering Claim 8 recites additional mental step which is not patent eligible. Claim 9 recites mere post solution activity of rendering which is insignificant extra solution activity and Well-Understood, Routine, and conventional. See 2106.05(d) Presenting offers and gathering statistics, OIP Techs., 788 F.3d at 1362-63, 115 USPQ2d at 1092-93.
Claim 1, this claim is within at least one of the four categories of patent eligible subject matter as it is directing to a system claim under Step 1.
However, the limitations to “determine a superset of a plurality of hardware microservices of the at least one hardware component, wherein determining the superset includes: discovering a loaded set of current hardware microservices loaded on the at least one hardware component, merging the loaded set and the loadable set to form the superset, generate a sequence flow of a selected subset of the plurality of hardware microservices based on a user input and for the generated sequence flow, automatically check if an output parameter of a first hardware microservice in the sequence flow matches a required input parameter of a second, subsequent hardware microservice in the sequence flow”, as drafted, recite functions that, under its broadest reasonable interpretation, covers functions that could reasonably be performed in the mind, including with the aid of pen and paper, but for the recitation of generic computer components. That is, the limitation as drafted, is a function that, under its broadest reasonable interpretation, recite the abstract idea of a mental process. The limitations encompass a human mind carrying out the function through observation, evaluation, judgment and /or opinion, or even with the aid of pen and paper. Thus, these limitations recite and fall within the “Mental Processes” grouping of abstract ideas under Prong 1 Step 2A.
Under Prong 2 Step 2A, this judicial exception is not integrated into a practical application. The claim recites the following additional elements “processing circuitry” “one or more interfaces”, “one or more interfaces configured to communicate with at least one hardware component”, “processing circuitry configured to control the one or more interfaces” and “and querying a cloud registry for a loadable set further of hardware microservices further loadable on the at least one hardware component,”. The “processing circuitry” “one or more interfaces” are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using a generic computer component, or merely a generic computer or generic computer components to perform the judicial exception. The addition elements “one or more interfaces configured to communicate with at least one hardware component”, “processing circuitry configured to control the one or more interfaces” are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using generic computer, and/or mere computer components. Further, “querying a cloud registry for a loadable set further of hardware microservices further loadable on the at least one hardware component” do nothing more than add insignificant extra solution activity to the judicial exception of merely transmit and receive data/information. Accordingly, the additional elements do not integrate the recited judicial exception into a practical application and the claim is therefore directed to the judicial exception. See MPEP 2106.05(g).
Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of the “processing circuitry”, “one or more interfaces”, one or more interfaces configured to communicate with at least one hardware component”, “processing circuitry configured to control the one or more interfaces” amount to no more than mere instructions, or generic computer/computer components to carry out the exception. Furthermore, the limitations “querying a cloud registry for a loadable set further of hardware microservices further loadable on the at least one hardware component” have been identified by the courts as merely receiving/transmitting data and displaying data/information on a display which is well-understood, routine and conventional activity. See MPEP 2106.05(d). The recitation of generic computer instruction and computer components to apply the judicial exception, and merely displaying data do not amount to significantly more, thus, cannot provide an inventive concept. Accordingly, the claims are not patent eligible under 35 USC 101.
Even when considered in combination, these additional elements represent mere instructions to apply an exception with well understood, routine, and conventional insignificant extra-solution activity, which does not provide significantly more to the abstract idea. The claim is not patent eligible.
Claim set 2 recites insignificant extra solution activity of storing data does not integrate the judicial exception into a practical application. See MPEP 2106.05(d). Claim 3 further recites mental steps which are not patent eligible. Claims 11 further recite additional mental steps that are not patent eligible. Claim 13 recites an “apply it” step which are mere instructions to implement an abstract idea on a computer or merely uses a computer as a tool to perform an abstract idea. Claim 14 further recites a post solution insignificant extra-solution activity a form of mere data gathering which does not integrate the abstract idea into a practical application nor amount to significantly more. Claim 15 recites an “apply it” step which are mere instructions to implement an abstract idea on a computer or merely uses a computer as a tool to perform an abstract idea. Claim 16 further recites a post solution insignificant extra-solution activity a form of mere data gathering which does not integrate the abstract idea into a practical application nor amount to significantly more.
Claim set 17-22 is similarly rejected to claim set 1-3 and 5-16 for having similar limitations.
Claim 23 is also similarly rejected to claim 17 for reciting similar limitations.
Therefore, the examiner believes the claims are not patent-eligible.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jose et al. (US 2017/0160880 A1) hereinafter Jose in view of Sorani et al. (US 10,754,666 B1) hereinafter Sorani and further and further in view of Rangasamy et al. (US 2020/0293337 A1) hereinafter Rangasamy.
Regarding claim 1, Jose discloses
A processing unit, comprising:
one or more interfaces configured to communicate with at least one hardware component (Jose [0067] discloses the application server 114 (see FIG. 1) runs the execution application 134 (see FIG. 1) to execute the program flow 600. The execution is as follows. After the start box 652, the box 653 indicates that the application server 114 runs the execution application 134 to process the program flow 600. Based on the program flow 600, the application server 114 calls the microservice 654 that corresponds to the microservice object 604 (see FIG. 6A). The box 655 indicates that after the microservice 654 has generated its results, the application server 114 provides the results of the microservice 654 as it calls the microservice 656 (corresponding to the microservice object 606 of FIG. 6A) and the microservice 658 (corresponding to the microservice object 608 of FIG. 6A). Where Fig. 1 illustrates the apps of Application Server 114 communicating through Network 108 with Microservices 110 and Sensor 111.); and
processing circuitry configured to control the one or more interfaces (Jose [0092] discloses Client Computer 116 controlling the application server 114 through user selection.) and to:
determine a superset of a plurality of hardware microservices of the at least one hardware component (Jose [0052] The user can then browse the source area 202 to find relevant microservices. Each of the microservices in the source area 202 corresponds to one of the microservices (e.g., 110 in FIG. 1) that is available to the user. Jose [0118] The user finds a relevant microservice X and drags it into the flow layout area 204. The user places a flow arrow routing the output of the microservice X. The user clicks on a “suggestion” icon and the system calculates the weights of the usage data to see the most relevant microservices that follow microservice X according to the weighted usage data. The system displays the top 5 microservices with the highest weight that follow microservice X according to the usage data. The user selects one of the top 5 microservices, microservice Y. The system positions microservice Y following microservice X in the flow layout area 204, and the system updates the usage data with this new usage. Jose [0093] discloses At 1008, a list of suggested microservice objects of the plurality of microservice objects is determined. For example, the application server 114 may determine the list using the suggestion application 132. The computer system determines the list by processing the usage data according to at least the first microservice object. The list of suggested microservice objects includes one or more of the plurality of microservice objects that follow the first microservice object according to the usage data. The suggestion process is discussed in more detail below. Jose [0062] Sensor microservices, in general, involve a hardware sensor (e.g., the sensor 111 in FIG. 1) that is related to the microservice. The hardware sensor generates sensor data, for example in response to a connection or query from the microservice to the hardware sensor. Thus, the microservices within the sensor subheader may include temperature microservice, motion microservice, GPS microservice, barcode microservice, microphone microservice, camera microservice, and RFID microservice.).
wherein determining the superset includes:
merging the loaded set and the loadable set to form the superset (Jose [0093]-[0097] disclose forming the superset of microservices within the program flow using the initial/loaded microservices in the program flow with the suggested microservices)
generate a sequence flow of a selected subset of the plurality of hardware microservices based on a user input (Jose [0057] discloses generating program flow illustrated in Fig. 2 based on user selections of the subset of hardware microservices); and
Jose lacks explicitly
wherein determining the superset includes:
discovering a loaded set of current hardware microservices loaded on the at least one hardware component, and
querying a cloud registry for a loadable set of hardware microservices further loadable on the at least one hardware component, and
for the generated sequence flow, automatically check if an output parameter of a first hardware microservice in the sequence flow matches a required input parameter of a second, subsequent hardware microservice in the sequence flow.
Sorani teaches
discovering a loaded set of current hardware microservices loaded on the at least one hardware component (Sorani [col. 9, lines 1-8] teach determine, based on the loaded HMS inventory, whether needed HMSs are already loaded on the FPGA (block 706) and, if a needed HMS has not yet been loaded, select an appropriate image to be retrieved from HMS image repository 500 (block 708) and initiate installation of the missing HMS in the HMS-FPGA via partial reconfiguration based on the selected image (710)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jose to incorporate the teachings of Sorani to “discovering a loaded set of current hardware microservices loaded on the at least one hardware component” in order to improve fault isolation, increase scalability, decrease development time, simplify maintenance, improve flexibility and is technology agnostic.
Rangasamy teaches
querying a cloud registry for a loadable set of hardware microservices further loadable on the at least one hardware component (Rangasamy [0071] teaches In an embodiment, the system receives a request for a self-service orchestration catalog (Operation 404), i.e., a catalog of self-service orchestration features that are available in the system. The request may be specific to a particular authorization level, such as a particular user, user group, user role, and/or another kind of authorization level. The request may be for a full self-service orchestration catalog, regardless of authorization level. The request may be for a catalog of self-service orchestration features available for all tenant-specific SaaS environments in the system.), and
for the generated sequence flow, automatically check if an output parameter of a first hardware microservice in the sequence flow matches a required input parameter of a second, subsequent hardware microservice in the sequence flow (Rangasamy [0143] teaches “microservices may be connected via a GUI. For example, microservices may be displayed as logical blocks within a window, frame, other element of a GUI. A user may drag and drop microservices into an area of the GUI used to build an application. The user may connect the output of one microservice into the input of another microservice using directed arrows or any other GUI element. The application builder may run verification tests to confirm that the output and inputs are compatible (e.g., by checking the datatypes, size restrictions, etc.)”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jose to incorporate the teachings of Rangasamy to “querying a cloud registry for a loadable set of hardware microservices further loadable on the at least one hardware component” in order to increase scalability and efficiency, enhance resilience and fault isolation, and increase agility and flexibility and “for the generated sequence flow, automatically check if an output parameter of a first hardware microservice in the sequence flow matches a required input parameter of a second, subsequent hardware microservice in the sequence flow” in order to efficiently only connect matching parameters and thus, prevent wasted time debugging issues with mismatched parameters.
Claims 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jose et al. (US 2017/0160880 A1) hereinafter Jose in view of Sorani et al. (US 10,754,666 B1) hereinafter Sorani and further and further in view of Rangasamy et al. (US 2020/0293337 A1) hereinafter Rangasamy and further in view of XIAO (US 2023/0103209 A1).
Regarding claim 2, Jose in view of Sorani and further in view of Rangasamy combination teach The processing unit according to claim 1,
the combination lacks explicitly
wherein the processing circuitry is further configured to store the superset in a localized persistent storage synchronized with the cloud registry
XIAO teaches
wherein the processing circuitry is further configured to store the superset in a localized persistent storage synchronized with the cloud registry (XIAO [0026] teaches synchronizing local data with the cloud storage).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination to incorporate the teachings of XIAO to “wherein the processing circuitry is further configured store the superset in a localized persistent storage synchronized with the cloud registry” in order to prevent wasted computing resource from accessing outdated data and increase efficiency accessing most up to date data from anywhere.
Claim 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jose et al. (US 2017/0160880 A1) hereinafter Jose in view of Sorani et al. (US 10,754,666 B1) hereinafter Sorani and further and further in view of Rangasamy et al. (US 2020/0293337 A1) hereinafter Rangasamy and further in view of SN (US 2021/0191706 A1).
Regarding claim 3, the combination teaches The processing unit according to claim 1, wherein the processing circuitry is further configured to:
the combination lacks explicitly
observe a status of the at least one hardware component; and
if the status of the at least one hardware component has changed redetermine a hardware microservice of the at least one hardware component.
SN teaches
observe a status of the at least one hardware component (SN [0097] teaches “The device may determine issues with the configuration, operation or performance of a service by identifying a change in a status, state or condition of a node or arc or elements represented by the node or arc.”); and
if the status of the at least one hardware component has changed redetermine a hardware microservice of the at least one hardware component (SN [0097] teaches “A user may determine issues with the configuration, operation or performance of a service by reviewing, exploring or interacting with the service graph display and any metrics. The user may change the configuration and/or parameters of the service graph. The user may change the configuration of the service. The user may change the configuration of the topology. The device may change the configuration of network elements making up the topology or the service.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination to incorporate the teachings of SN to “observe a status of the at least one hardware component; and if the status of the at least one hardware component has changed redetermine a hardware microservice of the at least one hardware component” in order to efficiently and timely correct any issues by changing to the correct services and prevent overall halt of the system.
Claims 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jose et al. (US 2017/0160880 A1) hereinafter Jose in view of Huang et al. (US 2021/0342144 A1) hereinafter Huang.
Regarding claim 4, A software module, comprising:
one or more interfaces configured to communicate with the processing unit of claim 1 (Jose [0067] discloses the application server 114 (see FIG. 1) runs the execution application 134 (see FIG. 1) to execute the program flow 600. The execution is as follows. After the start box 652, the box 653 indicates that the application server 114 runs the execution application 134 to process the program flow 600. Based on the program flow 600, the application server 114 calls the microservice 654 that corresponds to the microservice object 604 (see FIG. 6A). The box 655 indicates that after the microservice 654 has generated its results, the application server 114 provides the results of the microservice 654 as it calls the microservice 656 (corresponding to the microservice object 606 of FIG. 6A) and the microservice 658 (corresponding to the microservice object 608 of FIG. 6A). Where Fig. 1 illustrates the apps of Application Server 114 communicating through Network 108 with Microservices 110 and Sensor 111.); and
processing circuitry configured to control the one or more interfaces (Jose [0092] discloses Client Computer 116 controlling the application server 114 through user selection.) and to:
receive information about the superset of a plurality of hardware microservices of at least one hardware component (Jose [0052] discloses “The source area 202 generally displays the microservices available for the user to select. The source area 202 may display the micro services grouped together hierarchically or in an outline format. For example, similar microservices may be grouped together under a descriptive header. The user may click on a header to expand the group of microservices under that header, or may click again to collapse the group of microservices under than header. The groups may be nested within other headers. For example, Header 1 may be expanded to display Subheader 1 and Subheader 2. Subheader 1 may be expanded to display Microservices 1-2, and Subheader 2 may be expanded to display Microservices 3-12. The user can then browse the source area 202 to find relevant microservices. Each of the microservices in the source area 202 corresponds to one of the microservices (e.g., 110 in FIG. 1) that is available to the user”. [0059] discloses “The microservices listed in the source area 202 generally include all the microservices that the system (eg., the application server 114) has implemented with microservice objects (e.g., stored in the microservice objects database 120). General categories of microservices include platform layer microservices and application layer microservices. These may be considered to be the main headers”. Jose [0062] discloses the hardware microservices of a sensor);
provide information about the superset (Jose [0052] discloses “The source area 202 generally displays the microservices available for the user to select. The source area 202 may display the micro services grouped together hierarchically or in an outline format. For example, similar microservices may be grouped together under a descriptive header. The user may click on a header to expand the group of microservices under that header, or may click again to collapse the group of microservices under than header. The groups may be nested within other headers. For example, Header 1 may be expanded to display Subheader 1 and Subheader 2. Subheader 1 may be expanded to display Microservices 1-2, and Subheader 2 may be expanded to display Microservices 3-12. The user can then browse the source area 202 to find relevant microservices. Each of the microservices in the source area 202 corresponds to one of the microservices (e.g., 110 in FIG. 1) that is available to the user”.,
Jose lacks explicitly
wherein providing information about the superset includes rendering the superset as a hierarchical tree.
Huang teaches
wherein providing information about the superset includes rendering the superset as a hierarchical tree (Huang [0047] teaches displaying superset data in a hierarchical tree as illustrated in Figs. 1-2); and
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jose to incorporate the teachings of Huang to “plurality of hardware microservices of at least one hardware component” in order to enhanced data visualization, ease navigation, and provide a clearer understanding of complex relationships thus, providing context and revealing patterns that are difficult to see without a tree.
Regarding claim 5, Jose further discloses The software according to claim 4, wherein provide information about the superset and generate a subset is comprised by an exploring process (Jose [0053] discloses the source area 202 to include search box. When the user enters search terms into the search box, the system displays a list of microservices (or groups of microservices, e.g. by header) that meet the search terms.).
Claims 17-18, 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jose et al. (US 2017/0160880 A1) hereinafter Jose in view of Sorani et al. (US 10,754,666 B1) hereinafter Sorani and further and further in view of Rangasamy et al. (US 2020/0293337 A1) hereinafter Rangasamy and further in view of Huang et al. (US 2021/0342144 A1) hereinafter Huang.
Regarding claim 17, it’s directed to a method having similar limitations cited in claims 1 and 4. Thus claim 17 is also rejected under the same rationale as cited in the rejection of claims 1 and 4 above.
Regarding claim 18, The method according to claim 17, further comprising, generating a subset comprising the at least one hardware microservice (Jose [0053] and [0062] teaches displaying groups of microservices based on search terms which may be sensor microservices).
Regarding claim 23, it’s directed to a non-transitory computer-readable medium having similar limitations cited in claim 17. Thus claim 23 is also rejected under the same rationale as cited in the rejection of claim 17 above.
Claim 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jose et al. (US 2017/0160880 A1) hereinafter Jose in view of Huang et al. (US 2021/0342144 A1) hereinafter Huang and further in view of Miller et al. (US 2018/0173205 A1) hereinafter Miller.
Regarding claim 6, the combination teaches The software module according to claim 4, wherein the processing circuitry is further configured to:
the combination lacks explicitly
check if an update of the received information is available; and
if the received information has been updated receive updated information about the plurality of hardware microservices.
Miller teaches
check if an update of the received information is available (Miller [0083] “The secure update or upgrade application 328, in some embodiments, is configured to poll a cloud based service, on an intermittent basis, to determine if an update instance exists for any services or for any applications (e.g., 114, 314, 326, 328, etc.) executing at the local field agent 110 and for any applications (e.g., 116, 312, 318, 320, 324, etc.) executing at the real-time controller 112.); and
if the received information has been updated receive updated information about the plurality of hardware microservices (Miller [0083] “The secure update or upgrade application 328, in some embodiments, is configured to poll a cloud based service, on an intermittent basis, to determine if an update instance exists for any services or for any applications (e.g., 114, 314, 326, 328, etc.) executing at the local field agent 110 and for any applications (e.g., 116, 312, 318, 320, 324, etc.) executing at the real-time controller 112. To this end, upon determining an update instance exists (in some embodiments, the determination may be based on a determination of one or more new app files), the local field agent 110 can initiate transfer of the identified one or more new app files to the local field agent 110 (specifically, to a memory thereon).”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination to incorporate the teachings of Miller to “check if an update of the received information is available; and
if the received information has been updated receive updated information about the plurality of hardware microservices” in order to efficiently and continuously be up to date and prevent wasted computing resources from updating information if no updates are available.
Claims 19 is/are rejected under 35 U.S.C. 103 as being unpatentable overJose et al. (US 2017/0160880 A1) hereinafter Jose in view of Sorani et al. (US 10,754,666 B1) hereinafter Sorani and further and further in view of Rangasamy et al. (US 2020/0293337 A1) hereinafter Rangasamy and further in view of Huang et al. (US 2021/0342144 A1) hereinafter Huang and further in view of Miller et al. (US 2018/0173205 A1) hereinafter Miller.
Regarding claim 19, it’s directed to a method having similar limitations cited in claim 6. Thus claim 19 is also rejected under the same rationale as cited in the rejection of claim 6 above.
Claim 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jose et al. (US 2017/0160880 A1) hereinafter Jose in view of Huang et al. (US 2021/0342144 A1) hereinafter Huang and further in view of Li et al. (US 2018/0075158 A1) hereinafter Li.
Regarding claim 7, the combination teaches The software module according to claim 4,
the combination lacks explicitly
wherein the processing circuitry is further configured to synchronize the plurality of hardware micro- services to provide them to an external processing unit.
Li teaches
wherein the processing circuitry is further configured to synchronize the plurality of hardware micro- services to provide them to an external processing unit (Li [0030] “The server 104 may process the request including initiating a scheduler 110 to determine a sequence for calling one or more services 106. This sequence may be provided to an invoker 120, which may initiate ordered service calls 502 to one or more services 106. The one or more services 106 may provide required data 504 to the server 104. An assembler 130 may combine and filter the data and provide a result 320 to the client device 101”.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination to incorporate the teachings of Li to “wherein the processing circuitry is further configured to synchronize the plurality of hardware micro- services to provide them to an external processing unit” in order to efficiently and accurately execute the services while preventing dependency issues.
Claim 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jose et al. (US 2017/0160880 A1) hereinafter Jose in view of Sorani et al. (US 10,754,666 B1) hereinafter Sorani and further and further in view of Rangasamy et al. (US 2020/0293337 A1) hereinafter Rangasamy and further in view of Huang et al. (US 2021/0342144 A1) hereinafter Huang. and further in view of Li et al. (US 2018/0075158 A1) hereinafter Li.
Regarding claim 20, it’s directed to a method having similar limitations cited in claim 7. Thus claim 20 is also rejected under the same rationale as cited in the rejection of claim 7 above.
Claims 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jose et al. (US 2017/0160880 A1) hereinafter Jose in view of Huang et al. (US 2021/0342144 A1) hereinafter Huang and further in view of Carletti (US 2011/0041069 A1).
Regarding claim 8, the combination teaches The software module according to claim 4,
the combination lacks explicitly
wherein if a plurality of hardware microservice of the plurality of hardware microservices is selected the processing circuitry is further configured to generate a query plan for the plurality of hardware microservice.
Carletti teaches
wherein if a plurality of hardware microservice of the plurality of hardware microservices is selected the processing circuitry is further configured to generate a query plan for the plurality of hardware microservice (Carletti claim 1 “displaying a representation of each service in a graphical user interface, selecting a plurality of representations of the services in the graphical user interface, arranging the selected representations of the selected services into a graph in the graphical user interface, the graph including a set of connectors each one associating a set of preceding selected representations of preceding selected services to a set of following selected representations of following selected services, and generating an aggregated service from the graph, the aggregated service including an access point to the aggregated service, starting code for invoking each initial selected service associated with no preceding selected service in response to an invocation of the aggregated service through the access point, and synchronization code for setting the input parameters of each set of following selected services according to the output parameters of the associated preceding selected services and for invoking each set of following selected services in response to an availability of the output parameters of the associated preceding selected services”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination to incorporate the teachings of Carletti to “wherein if a plurality of hardware microservice of the plurality of hardware microservices is selected the processing circuitry is further configured to generate a query plan for the plurality of hard- ware microservice” in order to efficiently accurately process only the selected microservices and prevent wasted computing resource of processing unnecessary microservices.
Claim 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jose et al. (US 2017/0160880 A1) hereinafter Jose in view of Sorani et al. (US 10,754,666 B1) hereinafter Sorani and further and further in view of Rangasamy et al. (US 2020/0293337 A1) hereinafter Rangasamy and further in view of Carletti (US 2011/0041069 A1).
Regarding claim 11, the combination teaches The processing unit according to claim 1,
the combination lacks explicitly
wherein generate the sequence flow is comprised by a modeling process.
Carletti further teaches
wherein generate the sequence flow is comprised by a modeling process (Carletti [0060] and Fig. 7 illustrate the model of the flow).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination to incorporate the teachings of Carletti to “wherein generate the sequence flow is comprised by a modeling process.” in order to efficiently and timely permit a comprehensive understanding of the overall sequence flow and easily debug any issues.
Claim 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jose et al. (US 2017/0160880 A1) hereinafter Jose in view of Sorani et al. (US 10,754,666 B1) hereinafter Sorani and further and further in view of Rangasamy et al. (US 2020/0293337 A1) hereinafter Rangasamy and further in view of Huang et al. (US 2021/0342144 A1) hereinafter Huang and further in view of Carletti (US 2011/0041069 A1).
Regarding claim 21, it’s directed to a method having similar limitations cited in claim 8. Thus claim 21 is also rejected under the same rationale as cited in the rejection of claim 8 above.
Claim 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jose et al. (US 2017/0160880 A1) hereinafter Jose in view of Huang et al. (US 2021/0342144 A1) hereinafter Huang and further in view of Carletti (US 2011/0041069 A1) and further in view of Li et al. (US 2018/0075158 A1) hereinafter Li.
Regarding claim 9, the combination teaches The software module according to claim 8,
the combination lacks explicitly
wherein the processing circuitry is further configured to render the query plan of the plurality of hardware microservices into a hierarchical tree.
Li teaches
wherein the processing circuitry is further configured to render the query plan of the plurality of hardware microservices into a hierarchical tree (Li Figs. 4A and 4B render the plan into graph).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination to incorporate the teachings of Li to “wherein the processing circuitry is further configured to render the query plan of the plurality of hard- ware microservices into a hierarchical tree” in order to efficiently and improve understanding of the overall plan and avoid wasted user time comprehending the data.
Claim 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jose et al. (US 2017/0160880 A1) hereinafter Jose in view of Sorani et al. (US 10,754,666 B1) hereinafter Sorani and further and further in view of Rangasamy et al. (US 2020/0293337 A1) hereinafter Rangasamy and further in view of Huang et al. (US 2021/0342144 A1) hereinafter Huang and further in view of Carletti (US 2011/0041069 A1) and further in view of Li et al. (US 2018/0075158 A1) hereinafter Li.
Regarding claim 22, it’s directed to a method having similar limitations cited in claim 9. Thus claim 22 is also rejected under the same rationale as cited in the rejection of claim 9 above.
Claims 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jose et al. (US 2017/0160880 A1) hereinafter Jose in view of Sorani et al. (US 10,754,666 B1) hereinafter Sorani and further and further in view of Rangasamy et al. (US 2020/0293337 A1) hereinafter Rangasamy and further in view of Stone et al. (US 2022/0334809 A1) hereinafter Stone.
Regarding claim 13, the combination teaches The processing unit according to claim 1,
the combination lacks explicitly
wherein the processing circuitry is further configured to generate an agnostic code from the sequence flow.
Stone teaches
wherein the processing circuitry is further configured to generate an agnostic code from the sequence flow (Stone [0051] teaches “after automatically generating code corresponding to the sequence of configured components within the region of the process flow builder GUI display (e.g., tasks 906, 910) that is initially configured to support execution of the process flow by the application platform 104 and/or the application platform 136, the visual process designer 140 modifies the autogenerated code to support execution independent of the application platform 104 and/or the application platform 136.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination to incorporate the teachings of Stone to “wherein the processing circuitry is further configured to generate an agnostic code from the sequence flow” in order to increase flexibility and adaptability across different environment thus improving interoperability.
Regarding claim 14, the combination teaches The software module according to claim 13,
the combination lacks explicitly
wherein the processing circuitry is further configured to transmit the agnostic code to an external processing unit to enable the external processing to use the plurality of hardware microservices.
Stone further teaches
wherein the processing circuitry is further configured to transmit the agnostic code to an external pro- cessing unit to enable the external processing to use the plurality of hardware microservices (Stone [0059] teaches “FIG. 11 depicts an exemplary implementation of the platform transformation process 1000 of FIG. 10 by a platform translation service 1100 to transform the configured process flow and constituent web components 200, 210 from a managed software package 1104 at a resource 1102 associated with an application platform (e.g., a database 120, 134 utilized by an application platform 104, 136) to counterpart components that may be incorporated in an off-platform software package 1108 maintained at an off-platform static resource 1106, which may be realized as any sort of computing device or system coupled to a network (e.g., a web server, a database, or other computing device or data storage element on the network 110).” As illustrated in Fig. 11).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination to incorporate the teachings of Stone to “wherein the processing circuitry is further configured to transmit the agnostic code to an external processing unit to enable the external processing to use the plurality of hardware microservices” in order to increase flexibility and adaptability across different environment thus improving interoperability.
Claims 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jose et al. (US 2017/0160880 A1) hereinafter Jose in view of Sorani et al. (US 10,754,666 B1) hereinafter Sorani and further and further in view of Rangasamy et al. (US 2020/0293337 A1) hereinafter Rangasamy and further in view of Gorin et al. (US 20190245944 A1) hereinafter Gorin.
Regarding claim 15, the combination teaches The processing unit according to claim 1,
the combination lacks explicitly
wherein the processing circuitry is further configured to decode the agnostic code to a native-code type.
Gorin teaches
wherein the processing circuitry is further configured to decode the agnostic code to a native-code type (Gorin [0088] teaches “For example, such a BVR container may comprise the first encoded data and the first accessor. However, the first accessor may include a platform-independent program for decoding only a portion of the first encoded data, while a second accessor, including different/additional platform-independent code for decoding additional features of the first encoded data, that is not included in the BVR container would need to be acquired before full decoding of the first encoded data may be accomplished. Accordingly, browser extension 126 may be configured to determine whether the BVR container is such a partial-feature BVR container (e.g., whether the first encoded data comprises at least one feature unsupported by the first accessor embedded in the BVR container) and, if so, browser extension 126 may be configured to acquire a second accessor comprising second platform-independent syntax for the at least one additional feature not supported by the first accessor in the BVR container.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination to incorporate the teachings of Gorin to “wherein the processing circuitry is further configured to decode the agnostic code to a native-code type” in order to efficiently secure code, improve data integrity, and accessing sensitive data.
Regarding claim 16, the combination teaches The software module according to claim 15,
the combination lacks explicitly
wherein decode the agnostic code is comprised by a deploying process.
Gorin
wherein decode the agnostic code is comprised by a deploying process (Gorin [0088] teaches “For example, such a BVR container may comprise the first encoded data and the first accessor. However, the first accessor may include a platform-independent program for decoding only a portion of the first encoded data, while a second accessor, including different/additional platform-independent code for decoding additional features of the first encoded data, that is not included in the BVR container would need to be acquired before full decoding of the first encoded data may be accomplished. Accordingly, browser extension 126 may be configured to determine whether the BVR container is such a partial-feature BVR container (e.g., whether the first encoded data comprises at least one feature unsupported by the first accessor embedded in the BVR container) and, if so, browser extension 126 may be configured to acquire a second accessor comprising second platform-independent syntax for the at least one additional feature not supported by the first accessor in the BVR container.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination to incorporate the teachings of Gorin to “wherein decode the agnostic code is comprised by a deploying process” in order to efficiently secure code, improve data integrity, and accessing sensitive data.
Response to Arguments
Response to 101 remarks:
Applicant's arguments filed 12/23/2025 have been fully considered but they are not persuasive.
Step 2A, Prong 1
Regarding the remark that the checking limitation describes an automated process performed by processing circuitry that is fundamentally not a mental process, the examiner would like to point out that the processing circuitry is recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using generic computer, and/or mere computer components. Further, the programmatic validation of technical compatibility in which if a mismatch is detected, the system automatically takes corrective action such as selecting the missing hardware microservice needed to bridge the incompatibility or re-rendering the superset to guide the user to a valid selection is not claimed to potentially integrate the judicial exception into a practical application or amount to significantly more. Further, the claim does not require parsing technical specifications of multiple distinct microservices. The claim broadly recites checking if an output parameter of a first hardware microservice in the flow matches a required input parameter of a second, subsequent microservice in the flow. Thus, a human may mentally check that the output of a first microservice being a string matches that the subsequent microservice requiring a string input. The examiner would further like to point out that process of the machine-readable hardware abstraction metadata, performing algorithmic comparisons of complex data structures, and providing automated real-time feedback during an interactive development process is not claimed. The examiner recommends amending the claim language to claim the intent of the invention as it is currently recited at a high-level of generality.
Step 2A, Prong 2
Regarding the remark that the claimed invention provides automated intelligent validation mechanism that checks parameter compatibility the examiner would like to point out that the current broad recitation of the checking limitation is analyzed as a mental step thus, not a consideration under Step 2A Prong 2. The examiner recommends amending the claim limitation to recite checking parameter compatibility in real-time during the modeling phase and before code generation or execution.
Regarding the remark that the claims do not merely use a computer as a tool to perform an abstract idea, the examiner recommends explicitly claiming the intent of the invention as the limitations are broadly recited and the steps may be performed on a generic computer.
Step 2B
Regarding the remark that the examiner provided no evidence to support the determining, generating and validating limitations as WURC, the examiner would again like to point out that these limitations are mental steps and were not analyzed under Step 2B as illustrated in the 101 rejection. Thus, these limitations were not analyzed to be a technical improvement and no evidence is required for illustrating WURC.
For the above reasons, the 101 rejection is maintained.
Response to 103 remarks:
Applicant’s arguments with respect to claim(s) 1-23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument and/or relies on additional references to cure the combination.
Regarding the Sorani, Carletti, and Huang references, the examiner would like to point out that only particular portions of the references are being borrowed and combined with the updated references. Further, Sorani is within the same field of classification search as the instant application which is G06F8/65 and Carletti deals with coding services in a graphical manner similar to the instant application, while Huang deals with generating graphical code and has G06F8/71 classification of configuration management which includes validating parameters. Thus, the Sorani, Carletti, and Huang references have been maintained and combined with the updated references.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Noor Alkhateeb whose telephone number is (313)446-4909. The examiner can normally be reached Monday-Friday from 9:00AM ET to 5:00PM ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chat do, can be reached at telephone number (571) 272-3721. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from Patent Center. Status information for published applications may be obtained from Patent Center. Status information for unpublished applications is available through Patent Center. Should you have questions about access to Patent Center, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) Form at https://www.uspto.gov/patents/uspto-automated- interview-request-air-form.
/NOOR ALKHATEEB/Primary Examiner, Art Unit 2193