DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Examiner notes the amendments made to claim 1 and the introduction of new claim 8. Claims 2-4 stand as cancelled and claims 6 and 7 are withdrawn from further consideration as drawn to a nonelected species.
Response to Arguments
Applicant's arguments filed 11/13/2025 have been fully considered but they are not persuasive.
Examiner notes that amended claim 1 includes the new limitation of “the strain relaxing layer is completely overlapped with the plurality of columnar parts in a plan view”. When the strain relaxing layer [112 Hata] of Hata is implemented directly under the light emitting portion of the modified device of Choi in view of Noda as shown in Hata, in a plan view the strain relaxing layer [112 Hata] will be completely overlapped with the plurality of columnar parts [42 Noda] of Noda as the strain relaxing layer [112 Hata] of Hata is only formed directly under the light emitting portion. Therefore, if the strain relaxing layer is only formed directly under the light emitting portion as shown in Hata, when viewed from above, the plurality of columnar parts will completely overlap the strain relaxing layer beneath the columnar parts.
Applicant’s arguments with respect to claim(s) 1,5 and 8 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Specifically, the limitation of “the strain relaxing layer is formed of an insulating material” as recited in amended claim 1 and new claim 8.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1,5 and 8 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 has been amended to include the limitations of “and the strain relaxing layer is formed of an insulating material,
the strain relaxing layer is completely overlapped with the plurality of columnar parts in a plan view”
Examiner notes that paragraph [0034] of the specification of the claimed application discloses that the strain relacing layer [82] is, for example, an AlN layer. Further, paragraph [0034] discloses that the strain relaxing layer [82] is formed so as to not be high in resistance with respect to the electrical current from the third impurity region. This specification does not disclose any insulating properties for the strain relaxing layer aside from the potentially insulating composition of aluminum nitride.
Further, the second added limitation of “the strain relaxing layer is completely overlapped with the plurality of columnar parts in a plan view” is not disclosed in the specification or shown in any of the figures shown in the drawings filed 12/17/2021. The drawings do not include any figures showing a plan view of the device, the figures disclose the device in a cross sectional view. Therefore, the limitation of “the strain relaxing layer is completely overlapped with the plurality of columnar parts in a plan view” as disclosed in amended claim 1 is not previously shown or disclosed in the original disclosure and is therefore introduces new matter.
Claim 5 is rejected at least on its dependency to rejected claim 1.
Similarly, new claim 8 includes the limitations of “the strain relaxing layer is formed of an insulating material,
the strain relaxing layer completely overlaps with the plurality of light emitting parts in a plan view” and
“the third impurity region is larger in area than the strain relaxing layer in the plan view”
As stated above, paragraph [0034] of the specification of the claimed application discloses that the strain relacing layer [82] is, for example, an AlN layer. Further, paragraph [0034] discloses that the strain relaxing layer [82] is formed so as to not be high in resistance with respect to the electrical current from the third impurity region. This specification does not disclose any insulating properties for the strain relaxing layer aside from the potentially insulating composition of aluminum nitride.
Further, figures showing a plan view of the device are not shown in the drawings filed 12/17/2021 and the specification also does not disclose the strain relaxing layer completely overlapping with the plurality of light emitting portions in a plan view. The drawings also do not include a plan view showing the third impurity region that is larger in area than the strain relaxing layer. Figure 9 shows a third impurity region [72] that is larger in area than the strain relaxing layer [82], but this figure shows a cross sectional view and not a plan view. Paragraph [0082] discloses that the area of the third impurity region [72] is larger than the area of the stacked body [81] when viewed from the stacking direction. The specification does not disclose this same relationship between the strain relacing layer or stacked body with the third impurity region in a plan view.
Therefore, the limitations disclosed above are understood to introduce new matter in new claim 8.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 8 are is rejected under 35 U.S.C. 103 as being unpatentable over Choi et. al (hereinafter Choi) (US 4774205 A) in view of Noda et al. (hereinafter Noda) (JP 2019029516 A) (Examiner notes an attached translation will be used for the claim mapping of Noda for the remainder of the Office Action. See PTO-892 form) and further in view of Hata et al. (hereinafter Hata) (US 20120086044 A1) and Ramdani et al. (hereinafter Ramdani) (US 20020047143 A1)
Regarding claim 1, Choi discloses in Figs. 5 and 6
A light emitting device [Fig. 5] comprising:
a substrate [12’ Fig. 5] (Col. 4, line 66);
a transistor [200 Fig. 5] (Col. 4, line 66) provided at the substrate [12’ Fig. 5] (Col.4, line 66);
a light emitting element [210 Fig. 5] provided on the substrate [12’ Fig. 5] (Col. 4, line 66]; and
an interconnection [50 Fig. 5] (Col. 5, lines 20-23) provided in the substrate [12’ Fig. 5] (Col. 4, line 66), the interconnection [50 Fig. 5] being configured to electrically couple the transistor [200 Fig. 5] and the light emitting element [210 Fig. 5] to each other (Col. 5, lines 20-24), wherein
the transistor [200 Fig. 5] includes:
a first impurity region [32’ Fig. 5] (Col. 5, lines 7 and 8) provided in the substrate [12’ Fig. 5];
a second impurity region [34’ Fig. 5] provided in the substrate [12’ Fig. 5], and the second impurity region [34’ Fig. 5] is same in conductivity type as the first impurity region [32’ Fig. 5] (Col. 3, lines 49 and 50); and
a gate [30 Figs. 5 and 6] (Col. 6, line 27) provided on the substrate [12’ Fig. 5], and the gate [30 Figs. 5 and 6] is configured to control an electrical current between the first impurity region [32’ Fig. 5] and the second impurity region [34’ Fig. 5],
the light emitting element [210 Fig. 5] has a stacked body (LED 210 having a stack of layers Fig. 5)
the light emitting element [210 Fig. 5] including
a first semiconductor layer [56 Fig. 5] (Col. 5, line 13);
a second semiconductor layer [60 Fig. 5] different in conductivity type from the first semiconductor layer [56 Fig. 5] (Col. 5, line 14); and
a light emitting layer [58 Fig. 5] (Col. 5, line 14) disposed between the first semiconductor layer [56 Fig. 5] and the second semiconductor layer [60 Fig. 5] (Col. 5, line 15),
the first semiconductor layer [56 Fig. 5] is disposed between the substrate [12’ Fig. 5] and the light emitting layer [58 Fig. 5],
the interconnection [50 Fig. 5] is a third impurity region provided in the substrate [12’ Fig. 5],
the stacked body [LED 210 Fig. 5] is provided above the third impurity region 50 Fig. 5],
the third impurity region [50 Fig. 5] is same in conductivity type as the first semiconductor layer [56 Fig. 5] (Col. 5, lines 13,14 and 20),
the third impurity region [50 Fig. 5] is electrically coupled to the first semiconductor layer [54 Fig. 5] (Col. 5, lines 20-23),
the third impurity region [50 Fig. 5] is continuous with the first impurity region [32’ Fig. 5] (Col. 5, lines 20-24), and.
the third impurity region [50 Fig. 5] is larger in depth than the first impurity region [32’ Fig. 5] (Col. 5, lines 20-24),
Choi fails to disclose,
a plurality of columnar parts each including a first semiconductor layer, second semiconductor layer and light emitting layer,
a mask layer provided between adjacent two columnar parts of the plurality of columnar parts
the stacked body has a strain relaxing layer disposed between the substrate and the first semiconductor layer,
a lattice constant of the strain relaxing layer has a value between a lattice constant of the substrate and a lattice constant of the first semiconductor layer, and
when viewed from a stacking direction of the first semiconductor layer and the light emitting layer, the third impurity region is larger in area than the strain relaxing layer.
Noda discloses in Fig. 6,
a plurality of columnar parts [42] (Para. [0044]) each including a first semiconductor layer [42a] (Para. [0047]), second semiconductor layer [42c] (Para. [0047]) and light emitting layer [42b] (Para. [0047]) and,
a mask layer [43] (Para. [0054]) provided between adjacent two columnar parts [42] of the plurality of columnar parts [42] (Para. [0054])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the plurality of columnar part and mask structure of Noda in place of the light emitting structure of Choi for the purpose of achieving high-power light emission at a narrow radiation angle. (Noda Para. [0002])
Choi in view of Noda fails to disclose,
the stacked body has a strain relaxing layer disposed between the substrate and the first semiconductor layer, and the strain relaxing layer is formed of an insulating material,
the strain relaxing layer is completely overlapped with the plurality of columnar parts in a plan view,
a lattice constant of the strain relaxing layer has a value between a lattice constant of the substrate and a lattice constant of the first semiconductor layer, and
when viewed from a stacking direction of the first semiconductor layer and the light emitting layer, the third impurity region is larger in area than the strain relaxing layer.
Hata discloses in Fig. 14,
a strain relaxing layer [112] (Para. [0044,0045]) disposed between a substrate [102] (Para. [0040]) and a first semiconductor layer [112] (Para. [0053]),
the strain relaxing layer [112] completely overlapped with the light emitting portion [122,124] (Paras. [0052,0111] (See Figs. 20 and 21 (Para. [0111]) (layers [122 and 124] disclosed as formed so as to be in contact with the corresponding layer [112]. Therefore, if the layers [122 and 124] are grown in contact with layer [112] (Para. [0060]), the layers [122,124] will completely overlap the underlying layer [112].)
a lattice constant of the strain relaxing layer [112] has a value between a lattice constant of the substrate [102] (Para, [0044-0046]) and a lattice constant of the first semiconductor layer [122] (Para. [0046,0047,0053])
when viewed from a stacking direction of the first semiconductor layer [122] a third impurity region [404] is larger in area than the strain relaxing layer [112].
Examiner notes that paragraph [0045] discloses the layer [12] being lattice-matched to substrate [102]. Further, paragraph [0046] discloses the composition for the layer [112] can be changed in regard to different concentrations of materials in the layer. Therefore, the lattice constant can be manipulated by changing the respective material concentrations of layer [112] to reduce lattice mismatch between substrate [102] and the III-V semiconductor layer [12] (Para. [0053])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the strain relaxing layer of Hata completely overlapped by the light emitting portion above the strain relaxing layer as shown by Hata between the substrate and first semiconductor layer of the modified device of Choi for the purpose of lattice matching the materials used and reducing defects due to lattice mismatch and for having the strain relaxing properties under the entire area of the light emitting portion. (Hata. Para. [0045])
Choi in view of Noda and Hata fails to disclose,
The strain relaxing layer is formed of an insulating material
Ramdani discloses in Fig. 1,
a strain relaxing layer [28] (Para. [0016]) formed of an insulating material (Para. [0018])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the material composition of the strain relaxing layer of Ramdani as the material of the strain relaxing layer of the modified device of Choi for the purpose of selectively insulating the device.
Regarding claim 8, Choi discloses in Figs. 5 and 6,
A light emitting device [Fig. 5] comprising:
a substrate [12’ Fig. 5] (Col.4, line 66);
a transistor [200 Fig. 5] (Col. 4, line 66); and
a light emitting part [210 Fig. 5] (Col.4, line 66), wherein
the transistor [200 Fig. 5] includes:
a first impurity region [32’ Fig. 5] (Col. 5, lines 7 and 8) being disposed in the substrate [12’ Fig. 5];
a second impurity region [34’ Fig. 5] being disposed in the substrate [12’ Fig. 5], and the second impurity region [34’ Fig. 5] is same in conductivity type as the first impurity region [32’ Fig. 5] (Col. 3, lines 49 and 50);
and
a gate [30 Figs. 5 and 6] (Col. 6, line 27) being configured to control an electrical current between the first impurity region [32’ Fig. 5] and the second impurity region [34’ Fig. 5] (Col. 5, lines 50-58),
the light emitting part [210 Fig. 5] including:
a first semiconductor layer [56 Fig. 5] (Col. 5, line 13);
a second semiconductor layer [60 Fig. 5] different in conductivity type from the first semiconductor layer [56 Fig. 5] (Col. 5, line 14); and
a light emitting layer [58 Fig. 5] (Col. 5, line 14) being disposed between the first semiconductor layer [56 Fig. 5] and the second semiconductor layer [60 Fig. 5] (Col. 5, line 15),
the first semiconductor layer [56 Fig. 5] is disposed between the substrate [12’ Fig. 5] and the light emitting layer [58 Fig. 5],
a third impurity region [50 Fig. 5] (Col. 5, lines 20-23) disposed in the substrate [12’ Fig. 5] (Col. 4, line 66) is continuous with the first impurity region [32’ Fig. 5] (Col. 5, lines 20-24) , and the third impurity region [50 Fig. 5] is electrically coupled to the first semiconductor layer [54 Fig. 5] (Col. 5, lines 20-24),
the light emitting part [210 Fig. 5] is disposed above the third impurity region [50 Fig. 5],
Choi fails to disclose,
a plurality of light emitting parts
each of the plurality of light emitting parts include:
a first semiconductor layer;
a second semiconductor layer different in conductivity type from the first semiconductor layer; and
a light emitting layer being disposed between the first semiconductor layer and the second semiconductor layer,
the plurality of light emitting parts are disposed above the third impurity region,
a strain relaxing layer is disposed between the substrate and the first semiconductor layer, and the strain relaxing layer is formed of an insulating material,
the strain relaxing layer completely overlaps with the plurality of light emitting parts in a plan view,
a lattice constant of the strain relaxing layer has a value between a lattice constant of the substrate and a lattice constant of the first semiconductor layer, and
the third impurity region is larger in area than the strain relaxing layer in the plan view.
Noda discloses in Fig. 6,
a plurality of columnar parts [42] (Para. [0044]) each including a first semiconductor layer [42a] (Para. [0047]), second semiconductor layer [42c] (Para. [0047]) and light emitting layer [42b] (Para. [0047]) and,
a mask layer [43] (Para. [0054]) provided between adjacent two columnar parts [42] of the plurality of columnar parts [42] (Para. [0054])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the plurality of columnar part and mask structure of Noda in place of the light emitting structure of Choi for the purpose of achieving high-power light emission at a narrow radiation angle. (Noda Para. [0002])
Choi in view of Noda fails to disclose,
a strain relaxing layer is disposed between the substrate and the first semiconductor layer, and the strain relaxing layer is formed of an insulating material,
the strain relaxing layer completely overlaps with the plurality of light emitting parts in a plan view,
a lattice constant of the strain relaxing layer has a value between a lattice constant of the substrate and a lattice constant of the first semiconductor layer, and
the third impurity region is larger in area than the strain relaxing layer in the plan view.
Hata discloses in Fig. 14,
a strain relaxing layer [112] (Para. [0044,0045]) disposed between a substrate [102] (Para. [0040]) and a first semiconductor layer [112] (Para. [0053]),
the strain relaxing layer [112] completely overlaps with a light emitting portion [122,124] (Paras. [0052,0111] (See Figs. 20 and 21 (Para. [0111]) (layers [122 and 124] disclosed as formed so as to be in contact with the corresponding layer [112]. Therefore, if the layers [122 and 124] are grown in contact with layer [112] (Para. [0060]), the layers [122,124] will completely overlap the underlying layer [112].)
a lattice constant of the strain relaxing layer [112] has a value between a lattice constant of the substrate [102] (Para, [0044-0046]) and a lattice constant of the first semiconductor layer [122] (Para. [0046,0047,0053])
when viewed in a plan view above the device, a third impurity region [404] is larger in area than the strain relaxing layer [112]. (Impurity region [404] wider than layer [112], therefore extending farther in area than [112])
Examiner notes that paragraph [0045] discloses the layer [12] being lattice-matched to substrate [102]. Further, paragraph [0046] discloses the composition for the layer [112] can be changed in regard to different concentrations of materials in the layer. Therefore, the lattice constant can be manipulated by changing the respective material concentrations of layer [112] to reduce lattice mismatch between substrate [102] and the III-V semiconductor layer [12] (Para. [0053])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the strain relaxing layer of Hata completely overlapped by the light emitting portion above the strain relaxing layer as shown by Hata between the substrate and first semiconductor layer of the modified device of Choi for the purpose of lattice matching the materials used and reducing defects due to lattice mismatch and for having the strain relaxing properties under the entire area of the light emitting portion. (Hata. Para. [0045])
Choi in view of Noda and Hata fails to disclose,
the strain relaxing layer is formed of an insulating material
Ramdani discloses in Fig. 1,
a strain relaxing layer [28] (Para. [0016]) formed of an insulating material (Para. [0018])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the material composition of the strain relaxing layer of Ramdani as the material of the strain relaxing layer of the modified device of Choi for the purpose of selectively insulating the device.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Noda, Hata and Ramdani as applied to claim 1 above, and further in view of Jinjoo et al. (hereinafter Jinjoo) (US 11527642 B2) supported by “High-Speed InP-Based Heterojunction Bipolar Transistors” (See PTO-892 form).
Regarding claim 5, Choi in view of Noda and Hata discloses the device outlined in the rejection of claim 1 above but fails to disclose,
a passivation film configured to cover the transistor
Jinjoo discloses in Fig. 1,
a passivation film [450] configured to cover a transistor [400] (Col. 7, Lines 22-
28)
It would have been obvious to one of ordinary skill in the art before the effective
filing date of the present invention to incorporate the teachings of a passivation layer
disclosed in Jinjoo et al. into the modified device of Choi et al. in view of Lu et al. for the
purpose of providing protection of the transistor under the passivation layer (High-
Speed InP-Based Heterojunction Bipolar Transistors Page 120, Right Column, Lines
23-26).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Examiner particularly notes Cai et al. (US 20160276807 A1) which discloses a transistor electrically connected to a light emitting stack which includes a seed layer directly below a buffer layer between the substrate and light emission stack. (See PTO-892 form.)
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUNTER J NELSON whose telephone number is (571)270-5318. The examiner can normally be reached Mon-Fri. 8:30am-5:00 ET.
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/H.J.N./Examiner, Art Unit 2828 /TOD T VAN ROY/Primary Examiner, Art Unit 2828