Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
Acknowledgment is made of the amendment filed November 11th, 2025 (“A...”), in which: claims 11 and 16 are amended; no claims are cancelled; no new claims are added; and rejections of the claims are traversed. Claims 1 – 20 are currently pending an Office Action on the merits as follows.
Acknowledgment is made of the amendment filed November 11th, 2025 (“A...”), in which claims 16 is amended in response to the rejection of claims 16 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention wherein there was insufficient antecedent basis for “the pillar”. The amendment is such that rejection of claims 16 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention is rendered moot. Examiner withdraws the rejection of claims 16 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Response to Arguments
Applicant’s arguments filed November 11th, 2025 have been fully considered but are not persuasive.
Applicant argues on pages 6 – 7 of the instant Remarks:
The rejection of claim 11 under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Yada (US 11049568 B1) was “legally incorrect” because claim 11 recites, “a pillar extending through the plate line, the bias gate, and the word line, a material of the pillar consisting of a semiconductor material”. Applicant argues that the phrase “consisting of” in claim 11 indicates a closed list that excludes non-recited features. Examiner indeed acknowledges that the phrase “consisting of” indicates a closed list that excludes non-recited features. However, examiner understands the following statements to be distinct:
“a pillar extending through the plate line, the bias gate, and the word line, a material of the pillar consisting of a semiconductor material”
“a pillar extending through the plate line, the bias gate, and the word line, the pillar consisting of a semiconductor material”
Examiner understands statement (i) to mean the pillar includes a material, and the material is consisting of a semiconductor material; whereas statement (ii) means the pillar is consisting of a semiconductor material. Regarding the former statement found in claim 11, examiner asserts that statement (i) it does not exclude the pillar from including other materials. Therefore, examiner is not persuaded that the rejection of claim 11 under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Yada (US 11049568 B1) was legally incorrect as indicated by applicant on pg. 7 of the instant Remarks.
Further, regarding claims 1 and 16, applicant argues on pages 7 – 8 of the instant Remarks:
The interpretation of Harada et al. (US 20220415901 A1) is factually incorrect because a pinch-off point is not a bottom select gate. Examiner agrees that it is factually incorrect to equate a pinch-off point to a bottom select gate for at least the reasons stated by the applicant on page 8 of the instant Remarks. Regardless, the rejection is not rendered moot by applicant’s arguments because examiner did not equate a pinch-off point to a bottom select gate. Rather, examiner’s position, as outlined in the Office Action (CTNF) mailed 09/10/2025, is that Harada’s first gate conductor layer 5a has distinct portions that permit different functions, wherein these distinct functions arise from the overall structure of the disclosed device. One distinct functions includes the function of a plate line, and another distinct function includes the function of a select gate. The examiner’s position is that a first portion of Harada’s first gate conductor layer 5a is analogous to that of a bottom select gate, and a second portion of Harada’s first gate conductor layer 5a is analogous to a plate line. Further, the examiner’s position is that the disclosed pinch-off point corresponds to/coincides to/is directly adjacent to a first portion of Harada’s first gate conductor layer 5a, i.e., a bottom select gate. Thus, examiner’s reference to the pinch-off point is to cite/point out the distinct function of the first gate conductor layer 5a in this area of the device, not that the pinch-off point is the first gate conductor, a plate line, or a bottom select gate. Additionally, the relative thicknesses, taken along the long side of the channel region 8, are shown in Fig. 3A which shows the second thickness (of the plate line) is greater than each of the first (of the bottom select gate) and third thicknesses (of the bottom select gate). Therefore, the examiner is not persuaded by applicant’s arguments.
Applicant’s arguments filed November 11th, 2025 with respect to claims 11 – 15 have been fully considered but are moot in view of the new grounds of rejection.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Examiner has reviewed the instant drawings and has concluded there are no figures that include both a bias gate and a bottom select gate. Therefore, a figure including a bias gate and a bottom select gate, let alone the claimed feature wherein the bias gate is formed above the bottom select gate (claim 11 states the plate line is formed above the bottom select gate and the bias gate is formed above the plate line), must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Rejections
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35
U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim(s) 11 – 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yada (US 11049568 B1), further in view of Lee et al. (US 20210193661 A1).
Regarding independent claim 11, Yada teaches a memory structure, comprising:
a bottom select gate (Fig. 22; first source-select-gate electrically conductive layer 146S1 may be interpreted as a bottom select gate. See col. 31; lines 41 – 46 for relationship between Figs. 21 and 22. Yada teaches in col. 35; lines 46 – 56 some disclosure of the first source-select-gate electrically conductive layer 146S1) having a first thickness (See thickness of first source-select-gate shown in Fig. 22);
a staircase structure (Fig. 21; lateral offset of layers in staircase region 200. See col 10; line 43), comprising:
a plate line (Fig. 22; source contact layer 114) ... having a second thickness (See thickness of source contact layer 114 shown in Fig. 22);
a bias gate (Fig. 22; second source-select-gate electrically conductive later 146S2 is connected to the control circuit 156. Yada teaches in col. 34; lines 12 – 28 that the control circuit 156 supplies a gate bias voltage, such that the examiner is interpreting 146S2 to be a bias gate) formed above the plate line (Fig. 22); and
a word line (Fig. 22; conductive layer 146. See col. 32; lines 33 – 37) formed above the bias gate and the plate line (Fig. 22) and having a third thickness (See thickness of conductive layer 146 shown in Fig. 22), wherein the second thickness is greater than each of the first and third thicknesses (See relative thicknesses in Fig. 22);
a pillar (Fig. 21; opening fill structure 58. See col. 32; lines 39 – 42) extending through the plate line, the bias gate, and the word line (Figs. 21 and 22), a material of the pillar consisting of a semiconductor material (Yada teaches in col. 21; lines 32 – 46 that the pillar comprises multiple layers, e.g., semiconductor channel 60 and 50, of which includes material considered to be a material of the pillar consisting of a semiconductor material, e.g., semiconductor channel 60 is taught in col. 20; line 12 – 17 to consist of semiconductor material, wherein semiconductor channel 60 is considered by the examiner to be a material);
a source structure (Fig. 22; source-level semiconductor layer 112) formed under the pillar (Figs. 21 and 22);
a drain cap (Fig. 22; drain contact via structure 88) formed above the pillar (Fig. 22); and
a bit line (Fig. 21; bit line 98) formed above the drain cap (Fig. 21).
However, Yada remains silent regarding the feature wherein:
a plate line ... formed above the bottom select gate and ...
However, in the same field of endeavor, Lee teaches a memory structure, comprising:
… a bottom select gate (Fig. 35; selection gate pattern 168) ...
a plate line (Fig. 35; first gate pattern 114) formed above the bottom select gate (See Fig. 35) ...
Examiner asserts that it would be obvious to alter Yada’s memory structure such that the plate line is formed above the bottom select gate, as disclosed by Lee, in order to simplify the processes for forming conductive gate patterns (discussed by Lee in at least [0100]) .
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Yada’s memory structure to include a plate line formed above the bottom select gate, as disclosed by Lee, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Lee’s selection gate pattern 168 is comparable to Yada’s first source-select-gate electrically conductive layer 146S1 because they both function as select gates. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Yada’s memory structure to include a plate line formed above the bottom select gate, as disclosed by Lee, with the predictable result of forming a memory structure through a simplified procedure.
Regarding dependent Claim 12, Yada, further in view of Lee, teach the memory structure of claim 11, wherein:
the pillar comprises a floating body extending in a vertical direction and having a pillar structure.
Yada teaches that the charge storage layer 54 may include floating gates (col. 19; lines 35 – 40). Further, Yada shows in Fig. 22 that the charge storage layer 54, included in the pillar, extends in a vertical direction and has a pillar structure.
Regarding dependent Claim 13, Yada, further in view of Lee, teach the memory structure of claim 12, wherein:
each of the plate line, the bias gate, and the word line surrounds a sidewall of the floating body (Fig. 22).
Regarding dependent Claim 14, Yada, further in view of Lee, teach the memory structure of claim 12, wherein:
the bias gate surrounds an upper portion of the pillar structure (Fig. 22).
Examiner is interpreting an upper portion of the pillar structure to be the portion of the pillar structure above the source-level insulating layer 117, as shown in Fig. 22.
Regarding dependent Claim 15, Yada, further in view of Lee, teach the memory structure of claim 11, further comprising:
a gate dielectric layer (Fig. 22; insulating layer 132) formed in contact with a sidewall of the bias gate (Fig. 22) and a sidewall of the pillar (Fig. 22).
Claim(s) 1 – 5, 8 – 10, 16, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20210193661 A1), further in view of Luo et al. (US 10580795 B1), and Harada et al. (US 20220415901 A1).
Regarding independent claim 1, Lee teaches a memory structure, comprising:
… a bottom select gate (Fig. 35; selection gate pattern 168) having a first thickness (Fig. 35);
a plate line (Fig. 35; first gate pattern 114) formed above the bottom select gate (See Fig. 35) and having a second thickness (Fig. 35); and
a word line (Fig. 35; second gate pattern 118) formed above the plate line (See Fig. 35) and having a third thickness (Fig. 35), …
a pillar (Fig. 35; channel 134 of channel structure 138) extending through the bottom select gate, the plate line, and the word line (See Fig. 35);
a source structure (Fig. 35; common source region 102) formed under the pillar (See Fig. 35); …
a drain cap (Fig. 35; drain region 136 of channel structure 138) formed above the pillar (See Fig. 35); and
a bit line (Fig. 35; bit line 152) formed above the drain cap (See Fig. 35).
However, in the embodiment relied upon for the above rejections, Lee remains silent on:
a staircase structure, comprising: …
a first, second, and third thickness for the bottom select gate, plate line, and word line, respectively, … wherein the second thickness is greater than each of the first and third thicknesses; …
… a conductive line formed under the source structure; …
However, Lee does disclose a staircase structure for another embodiment in their disclosure shown in Fig. 36. Fig. 36 shows that each successive metal layer, e.g., first and second gate patterns 114 and 118, in a vertical direction away from the substrate is laterally offset from a metal layer below it, i.e., a staircase structure. Combining the staircase structure of Fig. 36 with the embodiment shown in Fig. 35 would yield a memory structure comprising a staircase structure (Fig. 36; lateral offset of layers), comprising the elements arranged with the same structure shown in Fig. 35.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Lee’s memory structure shown in Fig. 35 to include a staircase structure as shown in Fig. 36, because such a modification is the result of combining prior art elements according to known methods to yield predictable results. More specifically, Lee’s memory structure shown in Fig. 35 as modified by a staircase structure shown in Fig. 36 can yield a predictable result of exposing the metal layers in the stack so connection elements may be attached, since the lateral offset creates easily accessible portions of the metal layers. Since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, one of ordinary skill in the art would have recognized that the results of the combination were predictable before the effective filing date of the instant invention.
Regarding a conductive line formed under the source structure, in the same field of endeavor, Luo teaches (col. 7; lines 45 – 57) a memory device with a source tier 118, a conductive routing tier 120, and a conductive interconnect tier 122 in Fig. 1A. The source tier 118 includes a source structure 124, and the conductive routing tier 120 includes conductive routing structures 134, interpreted to be conductive lines. Additionally, the conductive routing tier 120 is taught to be under the source tier 118, such that Luo discloses a conductive line formed under the source structure.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Lee’s memory device structure to include Luo’s conductive routing structure, i.e., a conductive line, under the source structure, because such a modification is the result of combining prior art elements according to known methods to yield predictable results. More specifically, Lee’s memory device as modified by Lou’s conductive line formed under the source structure can yield a predictable result of electrically connecting to additional structures and/or devices (Luo: col 9; lines 58 – 59) while using minimal space since the lines are formed under the memory device. Since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, one of ordinary skill in the art would have recognized that the results of the combination were predictable before the effective filing date of the instant invention.
Further, in the same field of endeavor, Harada teaches a similar memory structure wherein a memory structure (Fig. 3A) a plate line (Fig. 3A; first gate conductor layer 5a has the function of plate line and a bottom select gate, specifically at the pinch-off point 13 where there is a high carrier concentration; which is analogous to higher charge carrier concentration zone 222 in Fig. 2 of the instant application) and a word line (Fig. 3A; second gate conductor layer 5b). Examiner points to Harada’s teaching in [0077] which states that the first gate conductor layer 5a may be divided into two or more portions, which are operated synchronously or asynchronously as conductive electrodes for plate lines. Thus, the examiner asserts that it would be obvious to form a conductive portion/electrode divided from the other portion of the plate line abut the pinch-off point 13; which may be considered as a bottom select gate. Further, Harada’s bottom select gate, plate line, and word line each have thickness, i.e., a first through a third thickness, respectively, wherein the first thickness would be the thickness of the pinch-off point 13. Further, Harada teaches that the second thickness of the plate line (i.e., the portion not abut pinch-off point 13) is greater than the other thicknesses. Thus, Harada discloses a memory device wherein the second thickness is greater than each of the first and third thicknesses. Therefore, examiner asserts that it would be obvious to modify the thicknesses of Lee’s bottom select gate, plate line, and word line such that the thickness of the plate line is greater than the thickness of both the bottom select gate and the word line.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the Lee’s first thickness of the bottom select gate, second thickness of the plate line, and third thickness of the world line to include Harada’s teaching wherein the second thickness is greater than each of the first and third thicknesses, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Harada’s bottom select gate, plate line, and word line structures are comparable to Lee’s bottom select gate, plate line, and word line structures because these conductive structures function to select and drive memory cells in a memory structure. Therefore, it is within the capabilities of one of ordinary skill in the art to modify the Lee’s first thickness of the bottom select gate, second thickness of the plate line, and third thickness of the world line to include Harada’s teaching wherein the second thickness is greater than each of the first and third thicknesses with the predictable result of powering a memory cell.
Regarding dependent Claim 2, Lee, further in view of Luo and Harada, teach the memory structure of claim 1, wherein:
the pillar extends in a vertical direction (Lee: Figs. 26 and 20A show channel 134 extending in a direction orthogonal to the plane defined by a first and a second direction).
Regarding dependent Claim 3, Lee, further in view of Luo and Harada, teach the memory structure of claim 2, wherein:
each of the bottom select gate, the plate line, and the word line surrounds a sidewall of the pillar (Lee: Fig. 35).
Regarding dependent Claim 4, Lee, further in view of Luo and Harada, teach teaches the memory structure of claim 2, wherein:
the bottom select gate surrounds a lower portion (Lee: Fig. 35; portion of channel 134 below first gate pattern 114) of the pillar (Lee: Figs. 35).
Regarding dependent Claim 5, Lee, further in view of Luo and Harada, teach teaches the memory structure of claim 1, further comprising:
a gate dielectric layer (Lee: Fig. 35; gate insulation layer pattern 132) in contact with a sidewall of the bottom select gate and a sidewall of the pillar (Lee: Fig. 35).
Regarding dependent Claim 8, Lee, further in view of Luo and Harada, teach the memory structure of claim 1, wherein:
the bottom select gate comprises tungsten or cobalt (Lee: See [0143] – [144]).
Regarding dependent Claim 9, Lee, further in view of Luo and Harada, teach the memory structure of claim 1, wherein:
the plate line is formed with a lateral offset with respect to the bottom select gate.
Fig. 36 of Lee shows that each successive metal layer, e.g., first and second gate patterns 114 and 118, in a vertical direction away from the substrate is laterally offset from a metal layer below it.
Regarding dependent Claim 10, Lee, further in view of Luo and Harada, teach the memory structure of claim 1, further comprising:
a bottom select gate contact electrically couple to the bottom select gate.
Lee teaches in [0158] a first contact plug 180 electrically connected to the selection gate pattern.
Regarding independent claim 16, Lee teaches a method for forming a memory device, comprising:
… disposing a bottom select gate (Fig. 12; selection gate layer 108. See [0093]) having a first thickness (Fig. 12);
disposing a plate line above the bottom select gate (Fig. 16; first gate layer 114 disposed above selection gate layer 108a) and having a second thickness (Fig. 16); and
disposing a word line above the plate line (Fig. 18; second gate layer 118 disposed above first gate layer 114) and having a third thickness (Fig. 18), …
forming an opening (Fig. 22; preliminary channel hole 128) through the word line, the plate line, and the bottom select gate (Fig. 22);
forming a source structure at a bottom of the opening (Fig. 23; forming channel hole 130 such that source structure 102 is formed to be the bottom of the opening) …;
disposing a semiconductor material (Fig. 24; channel 134 is formed in the channel hole 130) in the opening and on the source structure to form a pillar;
forming a drain cap (Fig. 26; drain region 136); and
forming a bit line (Fig. 35; bit line 152) above the drain cap.
However, in the embodiment relied upon for the above rejections, Lee remains silent on:
forming a staircase structure (Fig. 36), comprising: …
a first, second, and third thickness for the bottom select gate, plate line, and word line, respectively, … wherein the second thickness is greater than each of the first and third thicknesses; …
forming a source structure at a bottom of the opening … by adding material to the bottom of the opening …
However, Lee does disclose forming a staircase structure for another embodiment in their disclosure shown in Fig. 36. Fig. 36 shows that each successive metal layer, e.g., first and second gate patterns 114 and 118, in a vertical direction away from the substrate is laterally offset from a metal layer below it, i.e., forming a staircase structure. Combining the staircase structure of Fig. 36 with the embodiment formed in Figs. 12 – 26 and shown in Fig. 35 would yield a method for forming a memory structure comprising forming a staircase structure (Fig. 36; lateral offset of layers), comprising the elements arranged with the same structure shown in Fig. 35 and formed in Figs. 12 – 26.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Lee’s method for forming a memory structure shown in Figs.12 – 26 and 35 to include forming a staircase structure as shown in Fig. 36, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Lee’s method for forming a memory structure shown in Figs. 12 – 26 and 35 as modified by forming a staircase structure shown in Fig. 36 can yield a predictable result of exposing the metal layers in the stack so connection elements may be attached, since the lateral offset creates easily accessible portions of the metal layers. Since the claimed invention is merely a combination of old methods for forming elements, and in the combination each element merely would have performed the same function as it did separately, one of ordinary skill in the art would have recognized that the results of the combination were predictable before the effective filing date of the instant invention.
Regarding the formation of a source structure at a bottom of the opening by adding material to the bottom of the opening, in the same field of endeavor, Luo teaches a source structure formed in dielectric material, wherein the source structure is made from metal (col. 8; lines 21 – 45). Since the dielectric material 125 is insulative, and cannot be chemically changed into the material of the source structure, the only way the source structure may be formed is by adding the material of the source structure. Considering Luo’s source tier 118 to be equivalent to Lee’s source structure, then Lee’s source structure may be modified in the same way as Luo’s; wherein metal is formed in Lee’s source structure which aligns with the conductive pillars, and thus being formed in a bottom of Lee’s opening.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Lee’s source structure to include Luo’s source structure, because such a modification is based on the use of known techniques to improve similar devices in the same way. Luo’s source tier is comparable to Lee’s source structure because they both function as a source terminal for the cells in the array. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Lee’s source structure to include Luo’s source structure with the predictable result of creating a source structure by adding material to the bottom of the opening wherein the pillar will be formed.
Further, in the same field of endeavor, Harada teaches a similar memory structure wherein a memory structure (Fig. 3A) a plate line (Fig. 3A; first gate conductor layer 5a has the function of plate line and a bottom select gate, specifically at the pinch-off point 13 where there is a high carrier concentration; which is analogous to higher charge carrier concentration zone 222 in Fig. 2 of the instant application) and a word line (Fig. 3A; second gate conductor layer 5b). Examiner points to Harada’s teaching in [0077] which states that the first gate conductor layer 5a may be divided into two or more portions, which are operated synchronously or asynchronously as conductive electrodes for plate lines. Thus, the examiner asserts that it would be obvious to form a conductive portion/electrode divided from the other portion of the plate line abut the pinch-off point 13; which may be considered as a bottom select gate. Further, Harada’s bottom select gate, plate line, and word line each have thickness, i.e., a first through a third thickness, respectively, wherein the first thickness would be the thickness of the pinch-off point 13. Further, Harada teaches that the second thickness of the plate line (i.e., the portion not abut pinch-off point 13) is greater than the other thicknesses. Thus, Harada discloses a memory device wherein the second thickness is greater than each of the first and third thicknesses. Therefore, examiner asserts that it would be obvious to modify the thicknesses of Lee’s bottom select gate, plate line, and word line such that the thickness of the plate line is greater than the thickness of both the bottom select gate and the word line.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the Lee’s first thickness of the bottom select gate, second thickness of the plate line, and third thickness of the world line to include Harada’s teaching wherein the second thickness is greater than each of the first and third thicknesses, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Harada’s bottom select gate, plate line, and word line structures are comparable to Lee’s bottom select gate, plate line, and word line structures because these conductive structures function to select and drive memory cells in a memory structure. Therefore, it is within the capabilities of one of ordinary skill in the art to modify the Lee’s first thickness of the bottom select gate, second thickness of the plate line, and third thickness of the world line to include Harada’s teaching wherein the second thickness is greater than each of the first and third thicknesses with the predictable result of powering a memory cell.
Regarding dependent Claim 18, Lee, further in view of Luo and Harada, teach the method of claim 16, wherein:
disposing the bottom select gate comprises disposing a conductive layer comprising tungsten or cobalt.
Lee teaches in [0143] – [144] a method for forming the memory structure shown in Fig. 35 where the bottom select gate is formed in a way where the bottom select gate comprises tungsten. This would be a result from an alternate method, different from that relied upon for the rejection of claim 16 which states forming a memory structure by disposing a bottom select gate.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Lee’s method for forming a selection gate pattern shown in Figs.12 to include a modified process for forming the selection gate pattern as disclosed in [0143] – [144], because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, an alternate process for forming the selection gate pattern as disclosed in [0143] – [144] is comparable to forming a selection gate pattern shown in Figs.12 because the end result is the memory structure shown in Figs. 26 and 35. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Lee’s method for forming a selection gate pattern shown in Figs.12 to be modified by a method disclosed in [0143] – [144] with the predictable result of forming a selection gate pattern that includes tungsten.
Claim(s) 6, 7, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20210193661 A1), further in view of Luo et al. (US 10580795 B1), Harada et al. (US 20220415901 A1), and Rhie et al. (US 20160233224 A1).
Regarding dependent Claim 6, Lee, further in view of Luo and Harada, teach the memory structure of claim 1, wherein:
the drain cap (Lee teaches in [0054] that the drain region 136 may include doped polysilicon) and the source structure (Lee teaches in [0031] - [0032] that the common source region 102 may be formed of n-doped silicon material) …
However, Lee remains silent on:
the drain cap … comprise a silicon material doped with n-type dopants.
However, in the same field of endeavor, Rhie teaches in [0032] forming source/drain regions with n-type doping. This step is necessitated by pilar material being doped with a p-type dopant, similar to the instant invention.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Lee’s drain cap to include n-type impurities, as disclosed by Rhie, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Rhie’s drain region is doped with an impurity, comparable to Lee' doped drain region. However, due to Rhie’s doping techniques of the channel structure, omitted by Lee, it necessitated Rhie’s drain region to be doped with n-type impurities. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Lee’s channel region to be doped with a p-type impurity and for the drain region to include n-type impurity, as disclosed by Rhie, with the predictable result of forming a p-n junction.
Regarding dependent Claim 7, Lee, further in view of Luo and Harada, teach the memory structure of claim 1; however, Lee remains silent on a memory structure wherein:
the pillar comprises a silicon material doped with p-type dopants.
However, in the same field of endeavor, Rhie teaches string bodies, i.e., pillars, made of semiconductor material, such as polysilicon, doped with p-type semiconductor material (Rhie: [0044]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Lee’s semiconductor material to be doped with p-type impurities, as disclosed by Rhie. See reasoning under rejection of claim 6.
Regarding dependent Claim 17, Lee, further in view of Luo and Harada, teach the method of claim 16; however, Lee remains silent on a method further comprising:
doping the semiconductor material with a p-type dopant.
However, in the same field of endeavor, Rhie teaches string bodies, i.e., pillars, made of semiconductor material, such as polysilicon, doped with p-type semiconductor material (Rhie: [0044]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Lee’s semiconductor material to be doped with p-type impurities, as disclosed by Rhie, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Rhie’s semiconductor material, e.g., polysilicon, used for forming a pillar is similar to Lee’s semiconductor material for forming a pillar; However, Rhie’s discloses doping the semiconductor material, omitted by Lee, with p-type impurities. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Lee’s channel region to be doped with a p-type impurity with the predictable result of forming a p-n junction with the doped n-type drain cap.
Claim(s) 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20210193661 A1), further in view of Luo et al. (US 10580795 B1), Harada et al. (US 20220415901 A1), and Serov et al. (US 20160071861 A1).
Regarding dependent Claim 19, Lee, further in view of Luo and Harada, teach the method of claim 16; however, Lee remains silent on the methods further comprising:
laterally etching back the bottom select gate through the opening.
However, in the same field of endeavor, Serov teaches a conductive material, sacrificial layer 42, used to form a select gate (See [0133] of Serov); wherein Fig. 5B shows it being etched back through an opening. This technique could be applied to the teachings of Lee, yielding: laterally etching back the bottom select gate through the opening.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Lee’s method of forming a memory device to include laterally etching back conductive layers in a memory stack, as disclosed by Serov, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Serov’s etching method is comparable to Lee’s because through the opening in which a pillar is formed, an insulating layer is need in both disclosures to insulate conductive material from the pillar to be formed. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Lee’s method of forming a memory device to include laterally etching back conductive layers in a memory stack, as disclosed by Serov, with the predictable result of energy efficiency.
Regarding dependent Claim 20, Lee, further in view of Luo, Harada, and Serov, teach the method of claim 19, further comprising:
disposing a gate dielectric layer (Lee: Fig. 23; gate insulation layer 132) on a sidewall of the etched-back bottom select gate.
Conclusion
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to the applicant's disclosure:
US 20230046352 A1 – considered for similar memory cell structure shown in Fig. 5B.
US 20090242968 A1, US 20150109862 A1, US 20120003831 A1, US 20180040629 A1, US 11411078 B2, US 12082413 B2, US 20110121403 A1, US 20140070295 A1 – were all considered for their similar structural features disclosed therein.
US 20190305085 A1 – teaches doping techniques of the various layers and components of a memory device
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARIO A AUTORE whose telephone number is (571)270-0059. The examiner can normally be reached Monday - Friday, 8 am - 5 pm.
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MARIO A. AUTORE JR.
Examiner
Art Unit 2897
/MARIO ANDRES AUTORE JR/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897