Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Response to Arguments
Applicant's arguments filed 11/26/25 have been fully considered but they are not persuasive.
In re pgs. 3-5 the applicant argues Kapoor discloses computational hardware but fails to teach processing content as set forth in claim 2.
In response the claims 2, 4-5 do not actually specify processing any content/data at all. They are apparatus claims that merely specify having the ability to so perform or the capability to process content (engine to process content) and Kapoor discloses engine to process content (“the application accelerator 504 is a cryptographic acceleration engine for encrypting and decrypting data. The application 512 may be designed to utilize the application accelerator 504. Alternatively, the application processing unit 502 may automatically utilize the application accelerator 504. In an example, the application accelerator 504 may comprise an FPGA”).
The claims specify A dynamic random access memory (DRAM) comprising a programmable memory comprising engine “to” process content; said programmable memory integrated within a bank of the DRAM. The claim specifies a first memory (DRAM) comprising a second memory comprising [an] engine that has the ability to so perform processing. Had the claim specified the 1st or 2nd memory actually processes data that would be like saying a sponge that can hold water actually washes dishes by itself.
The applicant’s disclosure specifies the memories (The programmable
intelligent search memory of my invention may be embodied as independent PRISM memory integrated circuits working with or may also be embodied within microprocessors, multi-core processors, network processors, TCP Offload Engines, pg. 8). Memories hold data and do not store engines in the memory locations. Processors which can be called engines, process data. The applicant’s devices that process data are the PRISMs (programmable memories) that are controlled by processors and may interact with DRAMs. A DRAM (Dynamic Random Access Memory) module does not comprise a processor; it's a separate component that stores data for the processor (CPU) to use and the claims never positively claim processing any data.
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Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 4, 5 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Kapoor (US 2008/0133517) in view of MUELLER GERHARD (DE 69829618 T2).
Kapoor discloses:
2, 4, 5. A dynamic random-access memory (DRAM) (RAM maybe DRAM, “The RAM 510 may be any embodiment of RAM, including SRAM, DRAM, Flash RAM, and so forth”, 0227) comprising a programmable memory (“The compiler may compile this input into an output that is directed at and/or suitable for programming and/or instructing any and all of the computational hardware of the flow processing facility 102. In embodiments and without limitation, such hardware may comprise one or more of a digital signal processor; an FPGA; a particular brand, model, or series of central processing unit; an ASIC; and so forth”, 0193; “Providing an accelerated execution of the critical region, this critical section may be dynamically programmed into the FPGA”, 0225; “associated memory space may be divided into sixteen regions of equal size. Each region may then be programmed to use one of three node sizes. The node sizes (in this example) are 64 entries, 128 entries, and 256 entries. The alignment of the nodes in each region may also be programmable.”, 0250) comprising engine “to” process content (“the application accelerator 504 is a cryptographic acceleration engine for encrypting and decrypting data. The application 512 may be designed to utilize the application accelerator 504. Alternatively, the application processing unit 502 may automatically utilize the application accelerator 504. In an example, the application accelerator 504 may comprise an FPGA”); said programmable memory integrated within a bank of the DRAM (bank of RAMs, “there may be two concurrently addressed RAMs”, 0247; “associated memory space may be divided into sixteen regions of equal size. Each region may then be programmed to use one of three node sizes. The node sizes (in this example) are 64 entries, 128 entries, and 256 entries. The alignment of the nodes in each region may also be programmable.”, 0250).
However, Kapoor fails to particularly refer to the plurality of RAMs as a bank of DRAMs.
MUELLER GERHARD (DE 69829618 T2) teaches a bank of DRAMs (“2 FIG. 12 shows a prior art multi-bank DRAM configuration that enables independent operation of each memory bank (herein the term "bank" refers to a memory array that can operate substantially independently, ie, that can be written while from another bank read and vice versa). ”).
It would have been obvious to combine the references before the effective filing date because they are in the same field of endeavor and Kapoor teaches it is well-known to use a plurality of RAMs that can be DRAMs. Doing so allows for each bank to be independently operated.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID R VINCENT whose telephone number is (571)272-3080. The examiner can normally be reached ~Mon-Fri 12-8:30.
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/DAVID R VINCENT/Primary Examiner, Art Unit 2123