DETAILED CORRESPONDENCE
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment, received 09/11/2025, has been entered. Claims 1, 6, and 12 have been amended. Claims 1-18 are currently pending in this application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 4-7, and 10-18 are rejected under 35 U.S.C. 103 as being anticipated by Lee (KR-20150029228-A) (see enclosed translation for citations) in view of Kwon (US-20140099525-A1).
PNG
media_image1.png
564
532
media_image1.png
Greyscale
Regarding claim 1,
Lee teaches a solid-state battery comprising [0069]: an electrode stacked body (Fig. 5 A, B) including:
a plurality of electrode layers (Fig. 5B, 532b’, 531b, 532b, 522b’; [0051])
alternately stacked (see Fig. 5B, 532b’, 531b, 532b, 522b’; [0051]) with a solid electrolyte layer (Fig. 5B, 533b, 533b’; [0069] [0072]); interposed therebetween (Fig. 5B, 533b, 533b’; [0072]);
the electrode stacked body having a length direction (Fig. 5b, direction orthogonal to both the plane of the figure and to the length direction) orthogonal to a stacking direction (Fig. 5b, vertical direction) of the electrode stacked body (Fig. 5b, 500b), a width direction (Fig. 5B, horizontal direction)orthogonal to the stacking direction (wherein the horizontal direction is orthogonal to the vertical direction) and the length direction (see Fig. 5b, 90 degrees to direction in/out the plane of the figure) of the electrode stacked body (Fig. 5b, 550b),
opposed lengthwise end surfaces (Fig. 5b, surfaces exposed in plane of Fig. and necessarily exposed oppositely) facing each other in the length direction (Fig. 5b, wherein the end surfaces of a rectangular structure face each other in the direction orthogonal to the plane of the figure), and widthwise end surfaces (Fig. 5b, surfaces along left and right sides of the figure) facing each other in the width direction (Fig. 5b, wherein left and right-side surfaces are facing each other),
wherein, in a sectional view of the electrode stacked body along the width direction (Fig. 5b, see sectional view along width direction), at least one of opposed widthwise end surfaces of each of the electrode layers is spaced from a respective widthwise end surface of the electrode stacked body (see annotated Fig. 5B, wherein at least one of opposed left and right end surfaces of each electrode layer is spaced from a respective end surface of the electrode stacked body),
and a first clearance from the at least one widthwise end surface of an uppermost electrode layer of the plurality of electrode layers to the respective end surface of the electrode stacked body in an upper portion and from the at least one widthwise end surface of a lowermost electrode layer of the plurality of electrode layers to the respective widthwise end surface of the electrode stacked body in a lower portion in a stacking direction of the electrode stacked body (see annotated Fig. 5B, “first clearance” in uppermost and lowermost end portions) is larger than a second clearance from the at least one widthwise end surface of a central electrode layer of the plurality of electrode layers to the respective widthwise end surface of the electrode stacked body in a central portion in the stacking direction of the electrode stacked body (see annotated Fig. 5B, wherein the “second clearance” is less that the “first clearance”).
However, Lee fails to teach wherein, in a sectional view of the electrode stacked body along the length direction, a first lengthwise end surface of a first set of the plurality of electrode layers is exposed from a first lengthwise end surface of the opposed lengthwise end surfaces, and a second lengthwise end surface of a second set of the plurality of electrode layers is exposed from a second lengthwise end surface of the opposed lengthwise
PNG
media_image2.png
385
690
media_image2.png
Greyscale
end surfaces.
Kwon teaches wherein, in a sectional view (annotated Fig. 24, see gray line demarcating a cross-section for reference) of the electrode stacked body 100 along the length direction (annotated Fig. 24, wherein the cross-section is parallel to a length direction along the right surface of electrode body 100), a first lengthwise end surface (see annotated Fig. 24, first end surface of plurality of electrode layers) of a first set (Fig. 24, bottom unit cell which contains bottom set of electrode layers [0094] with largest area; [0013], [0090]) of the plurality of electrode layers [0094] is exposed from (wherein “exposed from” is interpreted wherein as one component positioned or revealed in a manner that makes it visible or accessible, extending out of or appearing from a base component) a first lengthwise end surface (annotated Fig. 24, first end surface of electrode body) of the opposed lengthwise end surfaces (annotated Fig. 24, first and second end surfaces of electrode body), and a second lengthwise end surface (annotated Fig. 24, second end surface of plurality of electrode layers) of a second set of the plurality of electrode layers (annotated Fig. 24, middle unit cell which contains a set of electrode layers [0013], [0090], [0094]) is exposed from (wherein “exposed from” is interpreted wherein as one component positioned or revealed in a manner that makes it visible or accessible, extending out of or appearing from a base component) a second lengthwise end surface (annotated Fig. 24, right end surface of upper unit cell, “second end surface of electrode body”) of the opposed lengthwise end surfaces (annotated Fig. 24, first and second end surfaces of electrode body).
It would be obvious to one of ordinary skill in the art before the effective filing date of the present invention to modify the electrodes to have a clearance in the lengthwise direction, such that there are multiple sets of unit cells exposed from each other, as Kwon teaches that varying electrode geometry mitigates dead space [0008-0009] maximizing capacity [0009], wherein unit cells with different areas are described to form an advantageous stepped structure [0009] [0068] in two dimensions (see Fig. 24). Further, Lee similarly teaches that structural offsets enables increased capacity for mobile device to reduce dead space [0014], such that it would be obvious to one of ordinary skill in the art before the effective filing date of the present invention to apply the offsets of Lee in a second dimension, as demonstrated by Kwon (see Fig. 24; see [0009]), in order to further reduce dead space in mobile devices. The use of a known technique to improve similar devices (methods or products) in the same way is likely to be obvious (see MPEP § 2143, C.).
Regarding claim 4,
Lee in view of Kwon teaches the solid-state battery according to claim 1 (see rejection of claim 1 above), but fails to teach wherein a width W1 of the uppermost electrode layer and a width W2 of the lowermost electrode layer are 50% to 90% of a width W0 of the electrode stacked body. While not to scale, Fig. 5B depicts the widths of the electrode taking up 50% to 90% of the width of the electrode stacked body (see Fig. 5B, electrode body near first clearance), such that, absent a showing of criticality or unexpected results, it would be obvious to one of ordinary skill in the art before the effective filing date of the present invention to have wherein a width W1 of the uppermost electrode layer and a width W2 of the lowermost electrode layer are 50% to 90% of a width W0 of the electrode stacked body in order to minimize the dead space in the cell and increase the battery capacity.
Regarding claim 5,
Lee in view of Kwon teaches the solid-state battery according to claim 1 (see rejection of claim 1 above), but fails to teach wherein a width W1 of the uppermost electrode layer and a width W2 of the lowermost electrode layer are 70% to 90% of a width W0 of the electrode stacked body. While not to scale, Fig. 5B depicts the widths of the electrode taking up 70% to 90% of the width of the electrode stacked body (see Fig. 5B, width of electrode near the first clearances takes up over 3 quarters the width of the electrode near the second clearance), such that, absent a showing of criticality or unexpected results, it would be obvious to one of ordinary skill in the art before the effective filing date of the present invention to have wherein a width W1 of the uppermost electrode layer and a width W2 of the lowermost electrode layer are 70% to 90% of a width W0 of the electrode stacked body in order to minimize the dead space in the cell and increase the battery capacity.
Regarding claim 6,
Lee in view of Kwon teaches the solid-state battery according to claim 1 (see rejection of claim 1 above), wherein, in the sectional view of the electrode stacked body, both opposed widthwise end surfaces of each of the electrode layers are spaced from the respective widthwise end surfaces of the electrode stacked body (annotated Fig. 5B, “first clearance” and “second clearance” where both opposed widthwise end surfaces of each of the electrode layers are spaced from the respective end surfaces of the electrode stacked body)
Regarding claim 7,
Lee in view of Kwon teaches the solid-state battery according to claim 1 (see rejection of claim 1 above), wherein the uppermost electrode layer (Fig. 5B, 532b’), and a second electrode layer of the plurality of electrode layers (Fig. 5B, 531b) are in the upper portion in the stacking direction (uppermost region of Fig. 5B), a lowermost electrode layer and a third electrode layer of the plurality of electrode layers are in the lower portion in the stacking direction (Fig. 5B, 532b and 531b), the second electrode layer and the third electrode layer have the first clearance (annotated Fig. 5B, wherein the “first clearance” is the same for 532b’, 532b, and 531b on both sides).
Regarding claim 10,
Lee in view of Kwon teaches the solid-state battery according to claim 7 (see rejection of claim 7 above), wherein a width W1 of the uppermost electrode layer and the second electrode layer, and a width W2 of the lowermost electrode layer and the third electrode layer, are 50% to 90% of a width WO of the electrode stacked body (see rejection of claim 4 above)
Regarding claim 11,
Lee in view of Kwon teaches the solid-state battery according to claim 7 (see rejection of claim 7 above), wherein a width W1 of the uppermost electrode layer and the second electrode layer, and a width W2 of the lowermost electrode layer and the third electrode layer, are 70% to 90% of a width WO of the electrode stacked body (see rejection of claim 5 above)
Regarding claim 12,
Lee in view of Kwon teaches solid-state battery according to claim 7 (see rejection of claim 7 above), wherein, in the sectional view of the electrode stacked body, both opposed widthwise end surfaces of each of the electrode layers are spaced from the respective widthwise end surfaces of the electrode stacked body (see rejection of claim 6 above).
Regarding claim 13,
Lee in view of Kwon teaches the solid-state battery according to claim 1 (see rejection of claim 1 above), wherein clearances of the plurality of electrode layers gradually increase from the central electrode layer in the central portion toward each of the uppermost layer and the lowermost layer in the stacking direction of the electrode stacked body (see Fig. 15, wherein the “first clearance” of the uppermost layer and the corresponding clearance of the lowermost layer is gradually larger than the “second clearance” of the central portion).
Regarding claim 15,
Lee in view of Kwon teaches the solid-state battery according to claim 1 (see rejection of claim 1 above), wherein the uppermost electrode layer and the lowermost electrode layer are positive electrode layers (Fig. 7, uppermost 20 and a symmetrically stacked lowermost 20; [0052], “positive electrodes 20”).
Regarding claim 16,
Lee in view of Kwon teaches a mobile device ([0005], “mobile devices”) comprising the solid-state battery according to claim 1 (see rejection of claim 1 above).
Regarding claim 17,
Lee in view of Kwon teaches an electric vehicle ([0032], “electric vehicle”) comprising the solid-state battery according to claim 1 (see rejection of claim 1 above).
Regarding claim 18,
Lee teaches the solid-state battery according to claim 1 (see rejection of claim 1 above), but fails to teach wherein a thickness in the stacking direction of each of the uppermost electrode layer of the electrode stacked body is larger than a thickness of the central electrode layer of the electrode stacked body. Kwon teaches wherein a thickness in the stacking direction of each of the uppermost electrode layer of the electrode stacked body is larger than a thickness of the central electrode layer of the electrode stacked body (Fig. 1, wherein the thickness of the uppermost electrode layer is larger than a thickness of the central electrode layer. It would be obvious to one of ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Kwon, wherein a thickness in the stacking direction of each of the uppermost electrode layer of the electrode stacked body is larger than a thickness of the central electrode layer of the electrode stacked body, in order to better enable the volume of the solid-state battery to remain slim (see Fig. 1 and [0054], for varied thicknesses, and [0109] of Kwon, wherein the stepped structure has a thicker upper layer and realizes a slim profile).
Claims 2-3, 8-9, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (KR20150029228A) (refer to enclosed translations for citations) in view of Takero (JP 2015069775 A) (see Office Action mailed 09/26/2024 for citations).
Regarding claim 2,
Lee teaches the solid-state battery according to claim 1 (see rejection of claim 1 above), but fails to teach wherein the second clearance is 60% to 90% of the first clearance. Takero teaches wherein a stepped portion of a solid-state battery electrode stack increases the separation between electrodes such that short is better prevented ([007-010], “Therefore, in the stepped portion, the distance between the end face of the positive electrode layer and the end face of the negative electrode layer increases by the amount of positional deviation. Therefore, it is possible to prevent the end face of the positive electrode layer not covered with the solid electrolyte layer and the end face of the negative electrode layer from coming into contact with each other via the outside of the end face of the solid electrolyte layer, or from being short-circuited.”). Thus, the amount of clearance, aka distance between end faces of the positive and negative electrode layer, can be considered a result effective variable for preventing short-circuit. One of ordinary skill in the art would also understand that too much of a clearance reduces overall electrode material and overall capacity. Thus, it would be obvious to one of ordinary skill in the art before the effective filing date of the present invention to optimize, by routine experimentation, the amount of the first and second clearance such that the chances of short circuit are reduced while still maintaining an ideal amount of capacity for the solid-state battery.
Regarding claim 3,
Lee teaches the solid-state battery according to claim 1 (see rejection of claim 1 above), but fails to teach wherein the second clearance is 80% to 90% of the first clearance. Takero teaches wherein a stepped portion of a solid-state battery electrode stack increases the separation between electrodes such that short is better prevented ([007-010], “Therefore, in the stepped portion, the distance between the end face of the positive electrode layer and the end face of the negative electrode layer increases by the amount of positional deviation. Therefore, it is possible to prevent the end face of the positive electrode layer not covered with the solid electrolyte layer and the end face of the negative electrode layer from coming into contact with each other via the outside of the end face of the solid electrolyte layer, or from being short-circuited.”). Thus, the amount of clearance, aka distance between end faces of the positive and negative electrode layer, can be considered a result effective variable for preventing short-circuit. One of ordinary skill in the art would also understand that too much of a clearance reduces overall electrode material and overall capacity. Thus, it would be obvious to one of ordinary skill in the art before the effective filing date of the present invention to optimize, by routine experimentation, the amount of the first and second clearance such that the chances of short circuit are reduced while still maintaining an ideal amount of capacity for the solid-state battery.
Regarding claim 8,
Modified Lee teaches the solid-state battery according to claim 7 (see rejection of claim 7 above), wherein the second clearance is 60% to 90% of the first clearance (see rejection of claim 2 above).
Regarding claim 9,
Modified Lee teaches the solid-state battery according to claim 7 (see rejection of claim 7 above), wherein the second clearance is 80% to 90% of the first clearance (see rejection of claim 3 above).
Regarding claim 14,
Lee teaches the solid-state battery according to claim 1 (see rejection of claim of 1 above), but fails to teach wherein the first clearance of the uppermost electrode layer and the lowermost electrode layer are larger than clearances of all electrode layers of the plurality of electrode layers other than the uppermost electrode layer and the lowermost electrode layer. Takero teaches wherein the first clearance (Fig. 1A, lateral offset between 12 and 2; [0041]) of the uppermost electrode layer (Fig. 1A, 12; [0041]) is larger than clearances of all electrode layers (Fig. 1, wherein offset is largest at top for uppermost electrode 12) other than the uppermost electrode layer (see Fig. 1, 12). It would be obvious to one of ordinary skill in the art before the effective filing date of the present invention to have the uppermost electrode layer have the largest offset as Takero teaches that this allows the solid electrolyte layer to project out, functioning as a shielding wall, and better preventing contact between 12 and 13 thus better preventing short-circuit (see Takero; [0041]). Accordingly, it would be obvious to one of ordinary skill in the art before the effective filing date of the present invention to modify the unit cells of Lee such that the first clearance of the uppermost electrode layer and the lowermost electrode layer are larger than clearances of all electrode layers of the plurality of electrode layers other than the uppermost electrode layer and the lowermost electrode layer; as Takero teaches this as a known technique for preventing short-circuit at the narrow end of a stepped structure [0041]. The use of a known technique to improve similar devices (methods or products) in the same way is likely to be obvious. (see MPEP § 2143, C.).
Response to Arguments
Applicant’s arguments, see “Remarks”, filed 09/11/2025, have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kwon (US20140099525A1).
Applicant argues that the clearances of Lee are along a length rather than a width. However, this is not persuasive, as the claim defines the length direction as orthogonal to the stacking direction. As shown in Fig. 5B, the central electrode layers extend further laterally than uppermost and lowermost electrode layers in a direction orthogonal to the stacking direction (wherein the stacking direction is along the vertical direction in Fig. 5B). The particular designation of “width” does not distinguish the claimed structure.
Applicant argues that none of the prior art remedy the deficiencies in Lee. However, this is not persuasive, as discussed above, Lee is relevant to teaching the claimed “clearance” (see rejection of claim 1 above).
Applicant argues that all other claims should be allowable based off an allowable claim 1. However, this is not persuasive, as the rejection on claim 1 has been sustained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: KR 20150029228 A (cited in IDS) relevant to another embodiment of symmetrical stacking with larger end portion clearances (see Fig. 6).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL WYROUGH whose telephone number is (571)272-4806. The examiner can normally be reached on Monday-Friday 10am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIFFANY LEGETTE can be reached on (571) 270-7078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PAUL CHRISTIAN ST WYROUGH/Examiner, Art Unit 1728
/TIFFANY LEGETTE/Supervisory Patent Examiner, Art Unit 1723
Prosecution Insights