DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/24/2026 has been entered.
Election/Restrictions
Newly submitted claims 13 and 15 are directed to a nonelected species embodiment II exclusively directed to a second protective film 52 in place of a space 51 as shown in Fig. 15 in the Requirement for Restriction dated 09/28/2024. As such, claims 13 and 15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species embodiment.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 6-7 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kawashima et al. (US 2023/0187529 A1; hereinafter “Kawashima”).
Regarding claim 1, referring to Fig. 1B and related text, Kawashima teaches a semiconductor device comprising: a substrate (200) (paragraph 109); a nitride semiconductor layer (220) formed on the substrate (paragraph 110); a source electrode (204) and a drain electrode (205) formed in the nitride semiconductor layer, the source electrode and the drain electrode being arranged side by side in a first direction (a x-direction) parallel to a first main surface of the substrate (a top surface of 200) (paragraphs 115-116); a gate electrode (206) formed on the nitride semiconductor layer, the gate electrode being positioned between the source electrode and the drain electrode (paragraph 117); a first protective film (208B) formed on the nitride semiconductor layer, and that the first protective film covering the source electrode, the drain electrode, and the gate electrode (paragraph 168); a source field plate (209) formed on the first protective film, the source field plate being electrically connected to the source electrode, the source field plate being positioned between the gate electrode and the drain electrode in a plan view (a top-down view of Fig. 1B) in a direction (a y-direction) perpendicular to the first main surface (paragraphs 119 and 145); and a dielectric-breakdown inhibition portion (a portion of 203B embedded in 208B between 209 and 205) including a part (a center part of the portion of 203B) positioned between an end of the source field plate on the drain electrode side (an end portion of 209 facing 205) and an end of the drain electrode on the source field plate side (an end portion of 205 facing 209) in a sectional view in a second direction (a direction of front and back from Fig. 1B, which is perpendicular to the x-direction) parallel to the first main surface and perpendicular to the first direction (See an annotated Fig. 1B below and paragraph 168), wherein the dielectric-breakdown inhibition portion includes a space (a portion of 203B embedded in 208B between 209 and 205) formed inside the first protective film (paragraph Fig. 1B), and wherein the space and a portion of the first protective film (a center portion of 208B above the portion of 203B) are positioned between a side of the drain electrode that faces the gate electrode (a left-side of 205 facing 206) and a side of the gate electrode that faces the drain electrode (a right-side of 206 facing 205) (Fig. 1B).
Kawashima teaches each and every limitation of semiconductor device including the dielectric-breakdown inhibition portion (a portion of 203B embedded in 208B between 209 and 205) as recited in claim 1 identically. Furthermore, claim 1 does not recite any feature to distinguish over Kawashima teaching the semiconductor device identically. As such, the claimed property or function, “the dielectric-breakdown inhibition portion being configured to inhibit dielectric breakdown of the first protective film”, is presumed to be inherent: Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 195 USPQ 430, 433 (CCPA 1977) and MPEP 2112.01.
PNG
media_image1.png
1189
1747
media_image1.png
Greyscale
Regarding claim 6, Kawashima teaches wherein the dielectric- breakdown inhibition portion includes a part that is positioned on, among line segments that connect a point in the source field plate and a point in the drain electrode, a shortest line segment in the sectional view (Fig. 1B).
Regarding claim 7, Kawashima teaches wherein, in the sectional view, the drain electrode has a first side (a left-side of 205) positioned on the side of the source field plate, the first side being in contact with the first protective film, the first side being perpendicular to the first direction, and the dielectric-breakdown inhibition portion is disposed to cross a region between, among points in the source field plate, a point closest to the drain electrode and the first side (Fig. 1B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 8-9, 12, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over You et al. (US2023/0369424 A1; hereinafter “You”) in view of Kawashima.
Regarding claim 1, referring to Figs. 1A-1B and related text, You teaches a semiconductor device comprising: a substrate (102) (paragraph 27); a nitride semiconductor layer (104 and 106) formed on the substrate (paragraphs 29-30); a source electrode (126) and a drain electrode (128) formed on the nitride semiconductor layer, the source electrode and the drain electrode being arranged side by side in a first direction (D2) parallel to a first main surface of the substrate (a top surface of 102) (paragraphs 26 and 42-43); a gate electrode (110) formed on the nitride semiconductor layer, the gate electrode being positioned between the source electrode and the drain electrode (paragraph 31); a first protective film (120) formed on the nitride semiconductor layer, and that the first protective film covering the source electrode, the drain electrode, and the gate electrode (paragraphs 36-37); a source field plate (130) formed on the first protective film, the source field plate being electrically connected to the source electrode, the source field plate being positioned between the gate electrode and the drain electrode in a plan view (Fig. 1A and a top-down view of Fig. 1B) in a direction perpendicular to the first main surface (paragraphs 46-50); and a dielectric-breakdown inhibition portion (122) including a part (a right-side portion of 122) positioned between an end of the source field plate on the drain electrode side (an end portion of 130 facing 128) and an end of the drain electrode on the source field plate side (an end portion of 128 facing 130) in a sectional view in a second direction (D1) parallel to the first main surface and perpendicular to the first direction, the dielectric-breakdown inhibition portion being configured to inhibit dielectric breakdown of the first protective film (paragraphs 36, 38-39, and 51), wherein the dielectric-breakdown inhibition portion includes a space (122 as an air gap embedded in 120) formed inside the first protective film (paragraph 36), and wherein the space and a portion of the first protective film (a portion of 120 surrounding 122) are positioned between a side of the drain electrode that faces the gate electrode (a left-side of 128 facing 110) and a side of the gate electrode that faces the drain electrode (a right-side of 110 facing 128) (Fig. 1B).
You does not explicitly teach that the source electrode and the drain electrode are formed in the nitride semiconductor layer since You teaches the source electrode (126) and the drain electrode (128) are formed on the nitride semiconductor layer (104 and 106) as discussed above (Fig. 1B) [underlying for clarity]. Nevertheless, it is well known in the art to provide the source electrode and the drain electrode either on the nitride semiconductor layer or in the nitride semiconductor layer in the power semiconductor device based on its design choice. This is evidenced by Kawashima teaching a semiconductor device (10), comprising: a source electrode (204) and a drain electrode (205) formed in a nitride semiconductor layer (220) (Figs. 1A-1B and paragraphs 107-116). Therefore, it would have been obvious to one of ordinary skill in the art to combine the teaching of You with that of Kawashima in order to provide the source electrode and the drain electrode in a desired configuration as a design choice for the semiconductor device.
Regarding claim 8, while You does not explicitly teach the dimension of the dielectric-breakdown inhibition portion, it would have been obvious to one of ordinary skill in the art to adjust the dimension of the dielectric-breakdown inhibition portion (122) from You as a routine experimentation for obtaining the optimal size, including the claimed dimension of 10 nm or more, for achieving its high breakdown electric field.
Regarding claim 9, referring to Figs. 1A-1B and related text, You teaches a semiconductor device comprising: a substrate (102) (paragraph 27); a nitride semiconductor layer (104 and 106) formed on the substrate (paragraphs 29-30); a source electrode (126) and a drain electrode (128) formed on the nitride semiconductor layer, the source electrode and the drain electrode being arranged side by side in a first direction (D2) parallel to a first main surface of the substrate (a top surface of 102) (paragraphs 26 and 42-43); a gate electrode (110) formed on the nitride semiconductor layer, the gate electrode being positioned between the source electrode and the drain electrode (paragraph 31); a Si nitride film (120 formed of silicon nitride) formed on the nitride semiconductor layer, the Si nitride film covering the source electrode, the drain electrode, and the gate electrode (paragraphs 36-37 and 41); a source field plate (130) formed on the Si nitride film, the source filed plate being electrically connected to the source electrode, the source filed plate being positioned between the gate electrode and the drain electrode in (Fig. 1A and a top-down view of Fig. 1B) in a direction perpendicular to the first main surface (paragraphs 46-50); and a space (122) formed inside the first protective film, the space including a part (a right-side portion of 122) positioned between an end of the source field plate on the drain electrode side (an end portion of 130 facing 128) and an end of the drain electrode on the source field plate side (an end portion of 128 facing 130) in a sectional view in a second direction (D1) parallel to the first main surface and perpendicular to the first direction (paragraphs 36, 38-39, and 51), and wherein the space and a portion of the first protective film (a portion of 120 surrounding 122) are positioned between a side of the drain electrode that faces the gate electrode (a left-side of 128 facing 110) and a side of the gate electrode that faces the drain electrode (a right-side of 110 facing 128) (Fig. 1B).
You does not explicitly teach that 1) the source electrode and the drain electrode are formed in the nitride semiconductor layer and 2) a dimension of the space in the first direction is 50 nm or more, and a dimension of the space in the direction perpendicular to the first main surface is 100 nm or more.
Regarding 1) the source electrode and the drain electrode are formed in the nitride semiconductor layer, You teaches the source electrode (126) and the drain electrode (128) are formed on the nitride semiconductor layer (104 and 106) as discussed above (Fig. 1B) [underlying for clarity] and it is well known in the art to provide the source electrode and the drain electrode either on the nitride semiconductor layer or in the nitride semiconductor layer in the power semiconductor device based on its design choice. This is evidenced by Kawashima teaching a semiconductor device (10), comprising: a source electrode (204) and a drain electrode (205) formed in a nitride semiconductor layer (220) (Figs. 1A-1B and paragraphs 107-116). Therefore, it would have been obvious to one of ordinary skill in the art to combine the teaching of You with that of Kawashima in order to provide the source electrode and the drain electrode in a desired configuration as a design choice for the semiconductor device.
Regarding 2) a dimension of the space in the first direction is 50 nm or more, and a dimension of the space in the direction perpendicular to the first main surface is 100 nm or more, it would have been obvious to one of ordinary skill in the art to adjust the dimension of the space (122) from You as a routine experimentation for obtaining the optimal size, including the claimed dimension of the space as discussed above, for achieving its high breakdown electric field. It has held that discovering an optimum or workable ranges involves only routine skill in the art. Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation. In re Aller, 105 USPQ 233.
Regarding claim 12, You teaches wherein the space is an air gap (122 as an air gap) or is filled with an insulating material (paragraph 36).
Regarding claim 14, You teaches wherein the space is an air gap (122 as an air gap) or is filled with an insulating material (paragraph 36).
Response to Arguments
Applicant’s arguments with respect to amended and newly submitted claims have been considered but are moot in view of new ground of rejection as set forth above in this Office Action.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL B WHALEN whose telephone number is (571)270-3418. The examiner can normally be reached on M-F: 8AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DANIEL WHALEN/Primary Examiner, Art Unit 2893