DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Specification Objections
Applicant has amended the specification at issue and the previous objections have therefore been withdrawn.
35 USC 112(f)
Applicant has amended claims such that 35 USC 112(f) is no longer invoked for the claim limitations recited in non-final mailed 9/5/2025.
35 USC 101
Applicant's arguments filed 11/25/2025 have been fully considered but they are not persuasive.
Applicant asserts the claim is more than a mathematical algorithm by including “a hardware device” and “as part of executing the instruction (commenced on a processor)” to integrate the claimed aspects into a practical application. Examiner respectfully disagrees. The hardware device and single instruction are recited at a high level of generality such that it is no more than reciting “apply it” to the plurality of operations, as the claim language does not integrate single instruction processing with the mathematical algorithm and merely recites that the mathematical algorithm is applied/executed by a single instruction. Therefore, the claim is still directed to a mathematical algorithm without significantly more.
Applicant asserts that, by using a single instruction, performance within a computer is improved by reducing the number of processing cycles and utilizing fewer system resources, and therefore the claim is directed to an improvement to the computer itself. Examiner respectfully disagrees. It is not clear that the improvements of the claimed invention are a result of performing the operations by a single instruction, as the claim is silent to overall instruction processing, such as fetching and decoding stages, and only recites processing the mathematical operations, or merely the execution stage. As discussed above, the claim is still directed to a mathematical algorithm without significantly more, and thus any improvement of the claimed invention is interpreted as a consequence of executing the mathematical algorithm as disclosed in Applicant’s paragraphs [0010], [0018].
Applicant further asserts the claims do not recite an abstract idea, per se, and is more than an abstract idea, and the additional elements integrate any recited judicial exception into a practical application in remarks pgs. 15-16. Examiner respectfully disagrees for the reasons discussed above that the additional elements are mere instructions to apply the exceptions and thus the claim is still directed to a mathematical algorithm without significantly more.
Applicant further asserts that the applicant is not claiming a mathematical algorithm that would preempt others from performing a conversion. Examiner respectfully disagrees because “while preemption is the concern underlying the judicial exception, it is not a standalone test for determining eligibility… instead questions of preemption are inherent in and resolved by the two-part framework from Alice Corp. and Mayo”, and Examiner has considered the claimed invention as a whole by the application of the Alice framework, and the claimed invention is directed to the mathematical algorithm of converting data from one format to another format without significantly more.
Applicant further asserts that at least one or more of the additional elements of the claims combined are unconventional and not well-understood, routine, conventional activity. Examiner respectfully disagrees. The 101 Step 2A analysis concluded that only “wherein the hardware device is to provide the converted result… to be used in processing within the computing environment”, which is transmitting data and is recognized by the courts as well-understood, routine, conventional activity MPEP 2106.05(d)(II)
Prior Art Rejections
Applicant properly invoked common ownership for 35 USC 102(b)(2)(C) for Schwarz et al. (US 20220276867 A1) filed 11/25/2025, and the prior art rejections relating to Schwarz are therefore withdrawn.
Applicant's arguments filed 11/25/2025 have been fully considered but they are not persuasive.
Applicant asserts Harthcock fails to teach “wherein the converting… as part of executing the instruction” and teaches away from the limitation by citing paragraph 20 of Harthcock, “such conversion can actually be free, in terms of clock cycles and explicit instructions”. Examiner respectfully disagrees. Harthcock [0020] discloses “the conversion of IEEE 754-2008 H=20 decimal character sequences to IEEE 754 binary format is automatic, if desired” (emphasis added). Thus, Harthcock merely suggests one may choose to skip explicit conversion instructions, and does not require one to forgo explicit conversion instructions. Furthermore, as the teachings of Harthcock allows conversion to be integrated into other instructions, Harthcock suggests performing all the operations of conversion may be executed by a single explicit instruction.
In regards to teaching away, the argument is insufficient to overcome the rejection of claim because “"Arguments that the alleged anticipatory prior art is ‘nonanalogous art’ or ‘teaches away from the invention’ or is not recognized as solving the problem solved by the claimed invention, [are] not ‘germane’ to a rejection under section 102."” See MPEP 2131.05.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-25 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding claim 1, at Step 1, the claim is directed to a system, which is a statutory category of invention (machine).
At Step 2A Prong 1, Examiner notes that the claims are directed towards an abstract idea. The claim language has been reproduced below:
A computer system for facilitating processing within a computing environment, the computer system comprising: a hardware device comprising one or more circuits to perform a plurality of operations to convert an input value directly from one format to another format (mental process, mathematical process), the hardware device to perform the plurality of operations based on execution of an instruction commenced on a processor, the plurality of operations comprising:
converting one part of the input value to provide a converted value (mental process, mathematical process);
performing one or more arithmetic operations on another part of the input value to provide an intermediate value (mental process, mathematical process);
and using the converted value and the intermediate value to provide a converted result in the another format (mental process, mathematical process), wherein the converting, the performing the one or more arithmetic operations and the using are performed as part of executing the instruction;
and wherein the hardware device is to provide the converted result in the another format to be used in processing within the computing environment.
At Step 2A Prong 2, the additional elements are bolded above. The additional elements do not integrate the abstract ideas into a practical application because the computer elements, which are recited at a high level of generality, provide conventional computer functions that do not impose any meaningful limits on practicing the abstract ideas. See MPEP 2106.05(f). The limitation “based on execution of an instruction” or “part of executing the instruction” are merely instructions to apply an exception. See MPEP 2106.05(f). The limitation “the hardware device is to provide…” is merely an insignificant extra-solution activity of data outputting. Even when viewed in combination, these additional elements do not integrate the recited judicial exception into a practical application and the claim is directed to the judicial exception.
At Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception. As set forth in the step 2A prong 2 analysis, the functions of data outputting/transmitting is recognized by the courts as well-understood routine and conventional. See MPEP 2106.05(d)(II). Even when considered in combination, these additional elements represent mere instructions to apply an exception and insignificant extra-solution activity, which do not provide an inventive concept. The Examiner would like to note Gottschalk v. Benson, which relate to claims reciting a process for converting binary-coded-decimal to binary.
Regarding claim 2, it is directed to the mathematical concept and/or mental process of
wherein the converting and the performing are repeated one or more times on one or more next input values to provide the converted result.
Under Step 2A Prong 2, the claim recites additional element “a next input value of the one or more next input values being provided based on the performing the one or more arithmetic operations on the another part of a previous input value”. The additional element does not integrate the abstract ideas into a practical application because providing the next input values are an insignificant extra-solution activity of data outputting and do not impose any meaningful limits on practicing the abstract idea.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 3, under Step 2A Prong 2, the claim recites additional element “one format is a hexadecimal floating point format and the another format is a binary coded decimal format, and wherein the one part of the input value is an integer part of the input value and the another part of the input value is a fraction part of the input value.”. The additional element does not integrate the abstract ideas into a practical application because defining the data formats is generally linking the use of the judicial exception to a particular field of use (See Parker v. Flook) and do not impose any meaningful limits on practicing the abstract idea.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 4, it is directed to the mathematical concept and/or mental process of
multiply the fraction part by a select value to provide the intermediate value, the multiply being an arithmetic operation of the one or more arithmetic operations performed on the another part of the input value.
Under Step 2A Prong 2, the claim recites additional element “multiplication circuit”. The additional element does not integrate the abstract ideas into a practical application because the multiplication component is recited at a high level of generality and do not impose any meaningful limits on practicing the abstract idea.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 5, it is directed to the mathematical concept and/or mental process of
perform the converting the one part, the converting comprising converting one or more hexadecimal integers of the input value to one or more decimal integers, and… to accumulate the one or more decimal integers, and wherein the multiply, the converting the one or more hexadecimal integers and the accumulate are performed at least substantially in parallel.
Under Step 2A Prong 2, the claim recites additional element “at least one circuit”. The additional element does not integrate the abstract ideas into a practical application because the at least one component is recited at a high level of generality and do not impose any meaningful limits on practicing the abstract idea.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 6, it is directed to the mathematical concept and/or mental process of
perform accuracy checking to determine whether the multiply is operating correctly.
Under Step 2A Prong 2, the claim recites additional element “checking circuit”. The additional element does not integrate the abstract ideas into a practical application because the checking component is recited at a high level of generality and do not impose any meaningful limits on practicing the abstract idea.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 7, it is directed to the mathematical concept and/or mental process of
generating a residue value of the integer part and the fraction part; subtracting a calculated residue of the integer part from the residue value to obtain an intermediate residue value; multiplying the intermediate residue value by a select residue value to obtain a product; multiplying the fraction part by the select value to obtain an intermediate fraction value; generating another residue value of a next input, the next input being based on the intermediate fraction value; and comparing the product with the another residue value to determine whether the multiply is operating correctly.
Under Step 2A Prong 2, the claim does not recite additional elements.
Under Step 2B, the claim elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 8, it is directed to the mathematical concept and/or mental process of
perform the converting the one part, the converting comprising converting one or more hexadecimal integers of the input value to one or more decimal integers, and… to accumulate the one or more decimal integers, and wherein the hardware device further comprises at least one checking component to perform accuracy checking to determine whether the converting the one or more hexadecimal integers and the accumulate are operating correctly.
Under Step 2A Prong 2, the claim recites additional element “at least one circuit”. The additional element does not integrate the abstract ideas into a practical application because the at least one component is recited at a high level of generality and do not impose any meaningful limits on practicing the abstract idea.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 9, it is directed to the mathematical concept and/or mental process of
generating a digit-wise residue of one or more converted digits of the one or more hexadecimal integers and accumulating digit-wise residues to obtain an accumulated digit-wise residue value; calculating an accumulated residue value based on the one or more decimal integers obtained using the converting the one or more hexadecimal integers and the accumulate; and comparing the accumulated digit-wise residue value and the accumulated residue value to determine whether the converting the one or more hexadecimal integers and the accumulate are operating correctly.
Under Step 2A Prong 2, the claim does not recite additional elements.
Under Step 2B, the claim elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 10, it is directed to the mathematical concept and/or mental process of
and wherein the performing the one or more arithmetic operations is performed on the multiple parts.
Under Step 2A Prong 2, the claim recites additional element “wherein the another part of the input value is split into multiple parts, the multiple parts including a fraction part and at least one correction part, the at least one correction part to be used to provide the converted result.”. The additional elements do not integrate the abstract ideas into a practical application because they are generally linking the use of the judicial exception to a particular field of use (See Parker v. Flook) and do not impose any meaningful limits on practicing the abstract idea.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 11, it is directed to the mathematical concept and/or mental process of
wherein the converting and the performing are repeated one or more times on one or more next input values to provide the converted result, and accumulate one or more correction terms obtained from performing the one or more arithmetic operations on one or more correction parts..
Under Step 2A Prong 2, the claim recites additional elements “, a next input value of the one or more next input values being provided based on the performing the one or more arithmetic operations on at least the fraction part of the multiple parts of a previous input value”, and “multiplication circuit, the multiplication circuit comprising a feedback path”. The additional elements do not integrate the abstract ideas into a practical application because providing the next input values are an insignificant extra-solution activity of data outputting, and the multiplication component with feedback path (for accumulation) is recited at a high level of generality and do not impose any meaningful limits on practicing the abstract idea.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 12, it is directed to the mathematical concept and/or mental process of
multiply the fraction part by a select value to provide the intermediate value, the multiply being an arithmetic operation of the one or more arithmetic operations performed on the another part of the input value.
Under Step 2A Prong 2, the claim recites additional element “multiplication tree”. The additional element does not integrate the abstract ideas into a practical application because the multiplication tree is recited at a high level of generality and do not impose any meaningful limits on practicing the abstract idea.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 13, it is directed to the mathematical concept and/or mental process of
the performing the one or more arithmetic operations includes performing a multiply of each multiple part by a select value, and to perform accuracy checking to determine whether the multiply is operating correctly.
Under Step 2A Prong 2, the claim recites additional element “checking circuit”. The additional element does not integrate the abstract ideas into a practical application because the checking component is recited at a high level of generality and do not impose any meaningful limits on practicing the abstract idea.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 14, at Step 1, the claim is directed to a system, which is a statutory category of invention (machine).
At Step 2A Prong 1, Examiner notes that the claims are directed towards an abstract idea. The claim language has been reproduced below:
A computer system for facilitating processing within a computing environment, the computer system comprising:
a hardware device comprising one or more circuits to perform a plurality of operations to convert an input value directly from one format to another format (mental process, mathematical process), the hardware device to perform the plurality of operations within the hardware device based on and as part of execution of an instruction commenced on a processor, the plurality of operations comprising:
splitting the input value into, at least, a fraction part and a fraction correction part (mental process, mathematical process);
performing arithmetic operations on the fraction part and the fraction correction part to provide a next input value and an updated fraction correction part (mental process, mathematical process);
repeating the splitting and the performing at least once to obtain an intermediate converted result (mental process, mathematical process), wherein the next input value is the input value, and wherein the performing arithmetic operations further includes performing an arithmetic operation on one or more previous updated fraction correction parts to provide one or more further updated fraction correction parts (mental process, mathematical process);
accumulating the one or more further updated fraction correction parts and the updated fraction correction part based on a last splitting to obtain a correction value (mental process, mathematical process);
and generating a converted result using the intermediate converted result and the correction value (mental process, mathematical process).
At Step 2A Prong 2, the additional elements are bolded above. The additional elements do not integrate the abstract ideas into a practical application because the computer elements, which are recited at a high level of generality, provide conventional computer functions that do not impose any meaningful limits on practicing the abstract ideas. See MPEP 2106.05(f). The limitation “based on execution of an instruction” or “part of executing the instruction” are merely instructions to apply an exception. See MPEP 2106.05(f). Even when viewed in combination, these additional elements do not integrate the recited judicial exception into a practical application and the claim is directed to the judicial exception.
At Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception. As set forth in the step 2A prong 2 analysis, the functions of data outputting/transmitting is recognized by the courts as well-understood routine and conventional. See MPEP 2106.05(d)(II). Even when considered in combination, these additional elements represent mere instructions to apply an exception and insignificant extra-solution activity, which do not provide an inventive concept. The Examiner would like to note Gottschalk v. Benson, which relate to claims reciting a process for converting binary-coded-decimal to binary.
Regarding claim 15, it is directed to the mathematical concept and/or mental process of
performing a multiply of the fraction part by a select value and at least one multiply of the fraction correction part by the select value of each iteration used to generate the converted result,
calculating a residue fraction value based on the fraction part of a current input value and a residue correction value based on a fraction correction part of a previous input value;
obtaining an intermediate residue value based on the residue fraction value and the residue correction value;
multiplying the intermediate residue value by a select residue value to obtain a product;
multiplying one portion of the fraction part of the current input value by the select value to obtain a next fraction part of a next input value;
determining a select correction term based at least on the fraction part of the current input value;
determining another residue value based on a residue of the select correction term and a residue of the next fraction part;
and comparing the product with the another residue value to determine whether the multiply is operating correctly.
Under Step 2A Prong 2, the claim recites additional element “the hardware device comprises at least one checking circuit”. The additional element does not integrate the abstract ideas into a practical application because the checking component is recited at a high level of generality and do not impose any meaningful limits on practicing the abstract idea.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claims 16-20, the claims are directed to a computer-implemented method that implements the same or similar features as the computer system of claims 1-2, 6, 8, 10, respectively, and are therefore rejected for at least the same reasons therein.
Regarding claims 21-22, the claims are directed to a computer system that implements the same or similar features as the computer system of claims 8-9, respectively, and are therefore rejected for at least the same reasons therein.
Regarding claims 23-25, the claims are directed to a computer system that implements the same or similar features as the computer system of claims 10-12, respectively, and are therefore rejected for at least the same reasons therein.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 14, 16-17, 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Harthcock (US 20210049011 A1, hereinafter “Harthcock”) provided in the IDS filed on 09/05/2024.
As per claim 1, Harthcock teaches A computer system for facilitating processing within a computing environment, the computer system comprising: a hardware device comprising one or more circuits to perform a plurality of operations to convert an input value directly from one format to another format, the hardware device to perform the plurality of operations based on execution of an instruction commenced on a processor (Harthcock: Fig. 22A-22B; [0388] of note the convertToDecimalCharacter operator), the plurality of operations comprising:
converting one part of the input value to provide a converted value (Harthcock: Fig. 31 element 9340; [0441]);
performing one or more arithmetic operations on another part of the input value to provide an intermediate value (Harthcock: Fig. 31 element 9350; [0442]);
and using the converted value and the intermediate value to provide a converted result in the another format, wherein the converting, the performing the one or more arithmetic operations and the using are performed within the hardware device and as part of executing the instruction (Harthcock: Fig. 30 element 9240; [0439], [0472]);
and wherein the hardware device is to provide the converted result in the another format to be used in processing within the computing environment (Harthcock: [0018], “the disclosed universal floating-point ISA has the ability, in hardware, to compute directly with dual decimal character sequences”).
As per claim 2, Harthcock further teaches The computer system of claim 1, wherein the converting and the performing are repeated one or more times on one or more next input values to provide the converted result, a next input value of the one or more next input values being provided based on the performing the one or more arithmetic operations on the another part of a previous input value (Hartchcock: [0381] operandA and operandB may be the decimal format; Fig. 45; [0503], the fused multiply-add allows repeated operations to be performed on values of the converted format).
As per claim 14, Harthcock teaches A computer system for facilitating processing within a computing environment, the computer system comprising: a hardware device comprising one or more circuits to perform a plurality of operations to convert an input value directly from one format to another format, the hardware device to perform the plurality of operations within the hardware device based on and as part of execution of an instruction commenced on a processor (Harthcock: Fig. 22A-22B; [0388] of note the convertToDecimalCharacter operator), the plurality of operations comprising:
splitting the input value into, at least, a fraction part and a fraction correction part (Harthcock: Fig. 34A elements 9010 and 9040; [0454]-[0456] element 9010 corresponding to the fraction part and element 9040 corresponding to the fraction correction part);
performing arithmetic operations on the fraction part and the fraction correction part to provide a next input value and an updated fraction correction part (Harthcock: Fig. 34A; [0454]-[0456]);
repeating the splitting and the performing at least once to obtain an intermediate converted result, wherein the next input value is the input value, and wherein the performing arithmetic operations further includes performing an arithmetic operation on one or more previous updated fraction correction parts to provide one or more further updated fraction correction parts (Harthcock: Fig. 34A; [0454]-[0456], the process is repeated by shifting the mantissa and splitting the shifted mantissa into the two parts, then accumulating to corresponding parts);
accumulating the one or more further updated fraction correction parts and the updated fraction correction part based on a last splitting to obtain a correction value (Harthcock: Fig. 34A; [0456], of note the sum of all chaff in the column above);
and generating a converted result using the intermediate converted result and the correction value (Harthcock: Fig. 34A; [0456], of note the addition of elements 9050 and 9060 to get the final result).
As per claims 16-17, the claim is directed to a computer-implemented method that implements the same or similar features as the computer system of claims 1-2, respectively, and is therefore rejected for at least the same reasons therein.
As per claim 20, Harthcock further teaches The computer-implemented method of claim 16, wherein the another part of the input value is split into multiple parts, and wherein the performing the one or more arithmetic operations is performed on the multiple parts (Harthcock: Fig. 34B; [0457], the fraction part is split into “second 22 digits” and chaff bits which both have arithmetic operations performed on).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Harthcock in view of Brown (US 3098994 A).
As per claim 18, Harthcock teaches The computer-implemented method of claim 16.
Harthcock does not teach wherein the one or more arithmetic operations includes one or more multiply operations, and wherein the computer-implemented method further comprises performing accuracy checking to determine whether the one or more multiply operations are operating correctly.
Brown teaches wherein the one or more arithmetic operations includes one or more multiply operations, and wherein the computer-implemented method further comprises performing accuracy checking to determine whether the one or more multiply operations are operating correctly (Brown: Fig. 1 element 26; col 7 lines 53-60).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the binaryToDecimal Character Engine of Harthcock with the conversion check arithmetic unit of Brown. One would have been motivated to combine these references because both references disclose multiplier circuitry, and Brown allows verifying operations with high error rates (Brown: col1 lines 30-33).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Harthcock in view of Carlough et al. (US 20100306632 A1, hereinafter “Carlough”).
As per claim 19, Harthcock teaches The computer-implemented method of claim 16.
Harthcock does not teach further comprising performing accuracy checking to determine whether the converting is operating correctly.
Carlough teaches further comprising performing accuracy checking to determine whether the converting is operating correctly (Carlough: Fig. 4 [0039]).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the binaryToDecimal Character Engine of Harthcock with the conversion error detection of Carlough. One would have been motivated to combine these references because both references disclose data type conversion circuitry, and Carlough reduces the area and power needed to provide erorr detection (Carlough: [0026]).
Allowable Subject Matter
Claims 3-13, 15, 21-25 would be allowable if rewritten to overcome the rejections under 35 U.S.C. 101 set forth in this Office Action and to include all of the limitations of the base claim and any intervening claims. The reasons for the indication of allowable subject matter were discussed in non-final action filed 9/5/2025.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/P.N.L./
Phat LeExaminer, Art Unit 2182 (571) 272-0546
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182