DETAILED ACTION
This Office Action is in response to the Request for Continued Examination filed 01 December 2025. Claims 1-4, 6-17, 19-23 are pending in this application. Claims 5 and 18 have been cancelled. Claims 8-17, 19-20, 22-23 have been allowed.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01 December 2025 has been entered.
Claim Rejections - 35 USC § 112
Applicant’s amendments filed with the RCE on 01 December 2025 address the previous 112a issues. Therefore, the previous 112a issues have been withdrawn. However, new rejections under 112a and 112b are provided below.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 21 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, because the specification, while being enabling for Claim 1, from which Claim 21 depends, and the limitations of Claim 21, it does not reasonably provide enablement for the combination of the limitation “a channel region … extending vertically from a top surface of the bottom source drain region to a bottom surface of the top source drain region” (from Claim 1) and the limitation “a first width of the channel region measured in a first horizontal plane aligned with the top source drain region is greater than a second width of the channel region measured in a second horizontal plane aligned with the gate region” (From Claim 21). The specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make the invention commensurate in scope with these claims.
Claim 21 combines two separate embodiments of the invention (as shown in Figs. 9 and 16). These two embodiments are made by separate processes, and they are not combined in the applicant’s disclosure. Specifically, the embodiment of Fig. 9 has “a channel region … extending vertically from a top surface of the bottom source drain region to a bottom surface of the top source drain region” but fails to have “a first width of the channel region measured in a first horizontal plane aligned with the top source drain region is greater than a second width of the channel region measured in a second horizontal plane aligned with the gate region”, Both are required for Claim 21 (through its dependency on Claim 1).
The embodiment of Fig. 16 has “a first width of the channel region measured in a first horizontal plane aligned with the top source drain region is greater than a second width of the channel region measured in a second horizontal plane aligned with the gate region” due the gate dielectric protruding into the channel layer, but fails to have “a channel region … extending vertically from a top surface of the bottom source drain region to a bottom surface of the top source drain region”.
Since the Applicant fails to show an embodiment that combines both features or a suggestion on how these two embodiments could be combined to form the claimed invention, the specification is not enabling.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Based on the limitations in Claim 3 (a bottom gate spacer between and physically separating the gate region from the bottom source drain region; and a top gate spacer between and physically separating the gate region from the top source drain region) the gate region, as claimed in Claim 1 cannot be interpreted to include the bottom or top gate spacers, as they separate the gate region from the source/drain regions.
However, Applicant’s Claim 6 claims “wherein a height of the gate dielectric is substantially equal to a height of the gate region.” Applicant’s disclosure shows that the height of the gate dielectric is substantially equal to a height of a bottom gate spacer 110, a gate 112, and a top gate spacer 114. (See Fig. 6)
It is unclear how the gate region can be interpreted as not including the gate spacers as required by Claim 3, and also have the same height as the gate dielectric as required by Claim 6 based on Applicant’ disclosure.
The present application discloses that the gate region includes the gates spacers ([0040] Specifically, the gate region 108 includes a bottom gate spacer 110, a gate 112, and a top gate spacer 114). Therefore, Claim 3 is interpreted as if reciting:
“wherein the gate region comprises a bottom gate spacer, a gate, and a top gate spacer;
and the bottom gate spacer is between and physically separating the gate [[region]] from the bottom source drain region; and the top gate spacer is between and physically separating the gate [[region]] from the top source drain region.”
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1, 3-4, 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida (2023/0034575 A1) (previously cited) and further in view of Chieh Lee et. al (US 2023/0269931 A1) (previously cited).
Regarding Claim 1, Yoshida discloses a semiconductor structure (Device of Fig. 2) comprising:
a bottom source drain region ([0030] the first electrode layer 102 is a drain electrode, Fig. 2);
a gate region ([0029] the gate electrode layer 104, Fig. 2) disposed above ([0029] the gate electrode layer 104 is disposed on the first electrode layer 102, Fig. 2) and insulated from the bottom source drain region (102) ([0030] the first insulating layer 112 is disposed between the gate electrode layer 104 and the first electrode layer 102, Fig. 2);
a top source drain region ([0030] the second electrode layer 106 is a source electrode, Fig. 2) disposed above ([0029 the second electrode layer 106 is disposed on the gate electrode layer 104, Fig. 2) and insulated from the gate region (104) ([0039] the second insulating layer 114 is disposed between the gate electrode layer 104 and the second electrode layer 106.);
and a channel region (an oxide semiconductor layer 108, Fig. 2) adjacent to the gate region (104) ([0030] The oxide semiconductor layer 108 penetrates through the gate electrode layer 104, Fig. 2) and extending vertically from a top surface (TS in Annotated Figure 2 below) of the bottom source drain region (102) to a bottom surface (BS in Annotated Figure 2 below) of the top source drain region (106). (See Annotated Fig. 2, oxide semiconductor 108 extends from the top surface TS of the bottom S/D region 102, to the bottom surface BS of the top S/D region 106)
a gate dielectric ([0030] gate dielectric layer 110, Fig 2) separating the gate region (104, 112, 114) from the channel region (108) (The gate dielectric layer 110 is disposed between the gate electrode layer 104 and the oxide semiconductor layer 108, Fig. 2), the gate dielectric (110) extends vertically from a top surface (TS) of the bottom source drain region (102) to a bottom surface (BS) of the top source drain region (106). (Fig.2 shows 110 extending from the top surface (TS) of the drain electrode (102) to the bottom surface (BS) of the source electrode (106))
Wherein the channel region (108) directly contacts a bottom surface, a sidewall, and a top gate surface of the gate dielectric (110). (See Annotated Fig. 2-B below)
Claim Interpretation Note 1: Claims 1 claims the limitation “wherein the channel region directly contacts a bottom surface, a sidewall, and a top surface of the gate dielectric”. In order to be consistent with the disclosure in the application, this limitation is interpreted to include arrangements where the channel contacts the top (or bottom) portion of the sidewall (the top or bottom corners) of the gate dielectric without extending onto the top surface of the gate dielectric. By contacting the corner of the sidewall and the top or bottom surface, the channel also contacts the top or bottom surface.
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However, Yoshida fails to disclose that the bottom source drain region is arranged above front-end-of-line circuitry.
Chieh Lee discloses disclose that the bottom source drain region (a second source/drain contact of the two source/drain contacts (referred to as a via contact 72 hereinafter)) is arranged above front-end-of-line circuitry. ([0022] For example, oxide semiconductors such as indium gallium zinc oxide (IGZO) may be used to form some parts (e.g., the channel layer) of the TFTs. By utilizing such semiconductor material, the fabrication of the TFTs may be integrated in a back end of line (BEOL) portion of a semiconductor fabrication process, instead of a front end of line (FEOL) portion of the semiconductor fabrication process.[0023] By utilizing such semiconductor material, the fabrication of the TFTs may be integrated in a back end of line (BEOL) portion of a semiconductor fabrication process, instead of a front end of line (FEOL) portion of the semiconductor fabrication process.)
Chieh Lee discloses that chip area in the FEOL is considered more valuable than that in the BEOL and moving the fabrication of TFTs to the BEOL may save valuable chip area in the FEOL for certain devices. ([0024]) It would have been obvious to one of ordinary skill in the art at the time of filing to create TFTs as part of the back end of line portion of the semiconductor device by using the materials of Chieh LEE. This would save room on the FEOL portion of the semiconductor device.
Regarding Claim 3, Yoshida further discloses (as shown in Fig. 2) a bottom gate spacer ([0029] a first insulating layer 112) between and physically separating the gate region (104) from the bottom source drain region (102); ([0030] the first insulating layer 112 is disposed between the gate electrode layer 104 and the first electrode layer 102)
and a top gate spacer ([0029] a second insulating layer 114) between and physically separating the gate region (104) from the top source drain region (106). ([0030] the second insulating layer 114 is disposed between the gate electrode layer 104 and the second electrode layer 106)
Regarding Claim 4, Yoshida further discloses (as shown in Fig. 2) wherein a width of the bottom source drain region ([0029] first electrode layer 102) is greater than a width of the gate region (104, 112, 114) and wherein the width of the gate region (104) is greater than a width of the top source drain region ([0029] second electrode layer 106). . ([0031] In the first embodiment, the profile of the cross section of the semiconductor device is step-shaped…For example, an electrode contact 116 connects to the first electrode layer 102, an electrode contact 118 connects to the gate electrode layer 104, and an electrode contact 120 connects to the second electrode layer 106. Those electrode contacts 116, 118 and 120 can be formed together using the same steps) (See Fig. 2)
Regarding Claim 6, Yoshida further discloses (as shown in Fig. 2) wherein a height of the gate dielectric (110) is substantially equal to a height of the gate region (104, 112, 114). (See Fig. 2, show both the gate region (104, 112, 114) and the gate dielectric (110) extending from the planar top surface of the bottom source/drain 102 to the bottom planar surface of the top source drain region 106)
Regarding Claim 7, Chieh Lee further discloses (as shown in Fig. 2) wherein the channel region ([0028] channel layer 40) comprises indium oxide, indium tin oxide, indium gallium zinc oxide, indium aluminum zinc oxide, amorphous silicon, polysilicon, or some combination thereof. ([0031] For each of the transistors, the channel layer may be an N-type channel and include an oxide semiconductor material such as, but not limited to, indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In.sub.2O.sub.3), tin dioxide (SnO.sub.2), indium zinc oxide (IZO), indium tin oxide (InSnO), and the like)
It would have been obvious based on the teachings of Chieh Lee to make the channel layer out of a material such as indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In.sub.2O.sub.3), tin dioxide (SnO.sub.2), indium zinc oxide (IZO), indium tin oxide (InSnO), and the like). Chieh Lee teaches that utilizing these semiconductor materials allows the fabrication of the TFT to be done in the BEOL portion of the device ([0023]) Therefore it would have been obvious to make the channel out of any one of the materials in Chieh Lee, such as indium gallium zinc oxide (IGZO), in order to allow the transistor to be fabricated as part of the BEOL.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida in view of Chieh Lee as applied to Claim 1 above, and further in view of Fan et. al (US 10020381 B1) (previously cited)
Regarding Claim 2, Yoshida further discloses (as shown in Fig. 2) a bottom contact (116, Fig. 2) connected to the bottom source drain region (102), a top contact (120, Fig. 2) connected to the top source drain region (106), and a gate contact (118, Fig. 2) connected to the gate region (104). ([0007] the semiconductor device further comprises electrode contacts connecting to the first electrode layer, the gate electrode layer, and the second electrode layer, respectively.)
However, Yoshida in view of Chieh Lee fails to disclose that the bottom contact is embedded into the bottom source drain region, the top contact is embedded into the top source drain region, and the gate contact is embedded into the gate region.
Both Yoshida and Fan are directed to vertical transistor devices. Fan discloses that embedding the contact rails advantageously allows for the bottom S/D resistance to be reduced without increasing the bottom S/D-to-gate parasitic capacitance. (Col. 4 Line 26-28). It would have been obvious to one of ordinary skill in the art at the time of filing to apply the known technique of embedding the contacts in Fan to the top contact, bottom contact, and gate contact of Yoshida in order to reduce the S/D resistance.
Allowable Subject Matter
Claims 9-20, 22-23 allowed.
Regarding Claim 8, the prior art is missing “a trench isolator between and physically separating a first portion of the single gate region from a second portion of the single gate region, wherein sidewalls of the trench isolator directly contact a sidewall of the first portion of the single gate region and a sidewall of the second portion of the single gate region”. Therefore, Claim 8 contains limitations not in the prior art and is allowed.
Regarding Claims 9-14, 22; Claims 9-14, 22 depend from Claim 8 and is allowed for the same reasons.
Regarding Claim 15, the closest prior art is Yoshida in view of Chieh Lee.
Yoshida discloses a semiconductor structure (Device of Fig. 2) comprising: a bottom source drain region ([0030] the first electrode layer 102 is a drain electrode, Fig. 2) ;
a single gate region ([0029] the gate electrode layer 104, Fig. 2) disposed above ([0029] the gate electrode layer 104 is disposed on the first electrode layer 102, Fig. 2) and insulated from the bottom source drain region (102) ([0030] the first insulating layer 112 is disposed between the gate electrode layer 104 and the first electrode layer 102, Fig. 2);
a top source drain region ([0030] the second electrode layer 106 is a source electrode, Fig. 2) disposed above ([0029 the second electrode layer 106 is disposed on the gate electrode layer 104, Fig. 2) and insulated from the gate region (104) ([0039] the second insulating layer 114 is disposed between the gate electrode layer 104 and the second electrode layer 106.);
a channel region (an oxide semiconductor layer 108, Fig. 2), the channel region extending vertically from a top surface (TS in Annotated Figure 2 below) of the bottom source drain region (102) to a bottom surface (BS in Annotated Figure 2 below) of the top source drain region (106).
a bottom gate spacer directly below the single gate region insulating the single gate region from the bottom source drain region; and a top gate spacer above the single gate region insulating the single gate region from the top source drain region,
a bottom gate spacer ([0029] a first insulating layer 112) directly below the single gate region (104) insulating the single gate region (104) from the bottom source drain region (102); ([0030] the first insulating layer 112 is disposed between the gate electrode layer 104 and the first electrode layer 102)
and a top gate spacer ([0029] a second insulating layer 114) directly below the single gate region (104) insulating the single gate region (104) from the top source drain region (106). ([0030] the second insulating layer 114 is disposed between the gate electrode layer 104 and the second electrode layer 106)
wherein the bottom gate spacer (112), the single gate region (104), and the top gate spacer (114) have substantially equal widths. (See Fig. 2)
However, Yoshida fails to disclose that the bottom source drain region is arranged above front-end-of-line circuitry, and that the channel region surrounds the gate region.
Chieh Lee discloses disclose that the bottom source drain region (a second source/drain contact of the two source/drain contacts (referred to as a via contact 72 hereinafter)) is arranged above front-end-of-line circuitry. ([0022] For example, oxide semiconductors such as indium gallium zinc oxide (IGZO) may be used to form some parts (e.g., the channel layer) of the TFTs. By utilizing such semiconductor material, the fabrication of the TFTs may be integrated in a back end of line (BEOL) portion of a semiconductor fabrication process, instead of a front end of line (FEOL) portion of the semiconductor fabrication process.[0023] By utilizing such semiconductor material, the fabrication of the TFTs may be integrated in a back end of line (BEOL) portion of a semiconductor fabrication process, instead of a front end of line (FEOL) portion of the semiconductor fabrication process.)
Chieh Lee discloses that chip area in the FEOL is considered more valuable than that in the BEOL and moving the fabrication of TFTs to the BEOL may save valuable chip area in the FEOL for certain devices. ([0024]) It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to create TFTs as part of the back end of line portion of the semiconductor device by using the materials of Chieh LEE. This would save room on the FEOL portion of the semiconductor device.
Chieh Lee further discloses that the channel region ([0028] a channel layer 40, Fig. 26) surrounds the gate region ([0028] a gate electrode 30, Fig. 26)
It would have been obvious to one of ordinary skill in the art at the time of filing to pattern a channel to surround the gate region. One of ordinary skill would recognize that patterning the channel around the gate would allow the transistor structure to be made smaller and thereby increase the density of the device. (As noted in Chen et. al. US 2022/0399339 A1, the doped layer 104 and the channel layer 106 respectively surround the gate 108…Thereby, the transistor structure 100 can be a channel-all-around (CAA) transistor and can effectively reduce the footprint of the transistor device to increase the density of the device. [0054])
However, the structure of the channel-all-around device in Chieh Lee is substantially different than the structure of applicant’s Claim. Specifically, the channel all-around device in Chieh Lee has the gate electrode (30) penetrate into the device, passing through the top dielectric layer 112, meaning the spacers are not above and below the gate and the source/drain structures are on the sides of the gate instead of above and below. It would not have been obvious to alter the structure of Yoshida based on the structure of the channel-all-around device in Chieh Lee in order to form the structure claimed. Therefore, Claim 15 is allowed.
Regarding Claims 16-17, 19-20, 23; Claims 16-17, 19-20, 23 depend from Claim 15 and are allowed for the same reasons.
Conclusion
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/J.J.G./ Examiner, Art Unit 2893 /Britt Hanley/Supervisory Patent Examiner, Art Unit 2893