DETAILED ACTION
This office action addresses Applicant’s response filed on 17 January 2026. Claims 1, 4, 7, 9-11, 14, and 17-21 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4, 7, 10, 11, 14, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fang (US 8,037,379) in view of Atishay (“SEARS: A Statistical Error and Redundancy Analysis Simulator”), and Lee (US 2019/0096505).
Regarding claim 1, Fang discloses a simulation method, comprising: acquiring redundancy design configuration (RDC) data and historical test data of products, the RDC data comprising repair schemes, wherein the historical test data is the historical test data in a design cycle (Fig. 1, items 18 and 20; Fig. 3 items 104-106; Fig. 5 step 142; col. 11, lines 7-16); allocating the repair schemes to failure cells in the historical test data according to a preset repair algorithm (RA), and acquiring a corresponding simulation repair result (col. 5, lines 5-12); and obtaining a yield of the products based on the simulation repair result and the historical test data (Fig. 6, item 180; Figs. 8A-9); wherein the obtaining a yield of the products based on the simulation repair result and the historical test data comprises: repairing, based on test data of an ith set of chips in the historical test data and the RDC data, the ith set of chips to obtain a simulation repair result for the ith set of chips, the simulation repair result for the ith set of chips comprising an unrepairable chip count in the ith set of chips, and i having an initial value of 1 and being a positive integer; calculating a sum of a chip count in an (i-1)th set of chips and a chip count in the ith set of chips to obtain a TCC; calculating a sum of an unrepairable chip count in the (i-1)th set of chips and the unrepairable chip count in the ith set of chips to obtain a TUCC; assigning i+1 to i, and returning to the step of performing simulation repair on the ith set of chips, based on test data of the ith set of chips in the historical test data and the RDC data, until an assigned i is greater than a chipset count in the historical test data; and obtaining the yield of the products based on the TCC and the TUCC (Fig. 6, items 156 and 168-180; col. 8, lines 50-54).
Fang does not appear to explicitly disclose the simulation repair result for the ith set of chips further comprises sizes of chips in the ith set of chips, and the method further comprises: obtaining, based on yields of the products in various RDC data, RDC data meeting requirements in the various RDC data; or obtaining, based on yields of the products in various RDC data and the sizes of the chips, RDC data meeting requirements in the various RDC data. Atishay discloses these limitations (p. 121, col. 1, § B chip size (row, column) and # of spare rows and columns; Fig. 10). Furthermore, if Fang is found to be unclear regarding acquiring redundancy design configuration (RDC) data and historical test data of products, the RDC data comprising repair schemes, wherein the historical test data is the historical test data in a design cycle, Atishay discloses the same (Abstract; p. 117, col. 2, 2nd to last paragraph). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Fang and Atishay, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of evaluating yield of different redundancy configurations. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Fang discloses simulating post-repair memory yields under varying conditions. Atishay teaches that one of the varying conditions is configuration of redundant resources. The teachings of Atishay are directly applicable to Fang in the same way, so that Fang would similarly simulate post-repair memory yields for different redundant resource configurations, in order to evaluate the effectiveness or suitability of the various configurations.
Regarding claim 4, Fang discloses that the products comprise chips, and the method further comprises: storing a total chip count (TCC), a total unrepairable chip count (TUCC) and a simulation yield of the products (Fig. 6 items 156 and 180; Fig. 8A-B; col. 8, lines 50-54; yield is by definition a percentage of good/usable chips out of total chips).
Regarding claim 7, Fang discloses determining whether simulation is ended, and acquiring, when no, updated data, and obtaining a yield of the products under new data based on the updated data and the historical test data (Fig. 6, items 168-178), but does not appear to explicitly disclose that the updated data is updated RDC data. Atishay discloses determining whether simulation is ended, and acquiring, when no, updated RDC data, and obtaining a yield of the products under new RDC data based on the updated RDC data and the historical test data (p. 121, §C and Fig. 10). Motivation to combine remains consistent with claim 1.
Regarding claim 10, Fang discloses that an extension direction of each of the row standby circuits is consistent with that of a word line; and an extension direction of each of the column standby circuits is consistent with that of a bit line (col. 7, lines 13-15).
Claims 11 and 14 are directed to a simulation apparatus comprising a processor and storage apparatus for performing the methods of claims 1 and 4, and are rejected under the same reasoning. Fang discloses a simulation apparatus comprising a processor and storage apparatus for performing the claimed methods (Fig. 3; col. 12, lines 1-12).
Regarding claim 17, Fang discloses a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and the computer program is executed by a processor to implement steps of the method according to claim 1 (Fig. 3; col. 12, lines 1-12; see also rejection of claim 1).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fang in view of Atishay and Joshi (US 2010/0131259).
Regarding claim 9, Fang does not appear to explicitly disclose that when the yield of the products is greater than or equal to a threshold, the products meet the requirements; Joshi discloses the same (¶42). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Fang, Atishay, and Joshi, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of developing designs that meet requirements. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Fang discloses simulating post-repair yields of memory devices. Joshi teaches that yields are compared to desired yield thresholds to determine if yields are acceptable. The teachings of Joshi are directly applicable to Fang in the same way, so that Fang would similarly compare the simulated yields to desired thresholds to determine if the yields are acceptable, or if modifications are required.
Claim(s) 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fang in view of Atishay and Mullins (US 2003/0005353).
Regarding claims 18 and 20, Fang discloses that the historical test data comprises repair range information, subregion information, and address information of the failure cells (Fig. 1; Fig. 6, item 162; col. 6, lines 23-42). If Fang is found to be unclear regarding repair ranges, subregion information, and address information of the failure cells, Mullins also discloses the same (¶¶40, 55, 56). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Fang, Atishay, and Mullins, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of simulating repairs in accordance with available redundant resources for memory regions. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Fang discloses simulating repairs of memories with failed cells using redundant resources. Mullins teaches that redundant resources are available for repairs in specific corresponding regions based on memory design. The teachings of Mullins are directly applicable to Fang in the same way, so that Fang’s repair simulation would accurately simulate repairs using the availability of redundant resources in particular regions of memory.
Claim(s) 19 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fang in view of Atishay and Lee (US 2019/0096505).
Regarding claims 19 and 21, Fang discloses that the repair schemes each comprise a count of allocable row standby circuits and corresponding position data as well as a count of allocable column standby circuits and corresponding position data in a preset subregion, and the preset RA comprises a repair rule, and the allocating the repair schemes to failure cells in the historical test data according to a preset RA (Fig. 1; col. 5, lines 5-12), and acquiring a corresponding simulation repair result comprises: acquiring position data of the failure cells in the products (Fig. 1; Fig. 6, item 162; col. 6, lines 23-42); allocating row standby circuits and column standby circuits according to the position data of the failure cells and the repair rule (col. 5, lines 5-12); and acquiring a count and position data of failure cells out of repair ranges of allocated row standby circuits and allocated column standby circuits to generate the corresponding simulation repair result (col. 5, lines 28-33).
If Fang is found to be unclear regarding counts of allocable row/column standby circuits and allocating row standby circuits and column standby circuits according to the position data of the failure cells and the repair rule, Atishay discloses that the repair schemes each comprise a count of allocable row standby circuits and corresponding position data as well as a count of allocable column standby circuits and corresponding position data in a preset subregion, and the preset RA comprises a repair rule, and the allocating the repair schemes to failure cells in the historical test data according to a preset RA (p. 117, Fig. 1; p. 121, Figs. 9 and 10), and acquiring a corresponding simulation repair result comprises: acquiring position data of the failure cells in the products (p. 120, Fig. 6); allocating row standby circuits and column standby circuits according to the position data of the failure cells and the repair rule (p. 117, Fig. 1; p. 121, Fig. 9); and acquiring a count and position data of failure cells out of repair ranges of allocated row standby circuits and allocated column standby circuits to generate the corresponding simulation repair result (p. 120, Fig. 6; p. 121, section A). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Fang and Atishay, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of simulating repairs based on defect positions and configurations of redundant resources. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Fang discloses simulations of repairs using redundant resources, but may be found to be unclear regarding the details of the repair simulation. Atishay teaches the repair simulation allocating redundant resources to failed cells based on the locations of defects and the number and configuration of redundant resources. The teachings of Atishay are directly applicable to Fang in the same way, so that Fang’s repair simulation would similarly simulate repairs by allocating redundant resources according to failure locations and configuration of redundant resources, in order to more accurately determine repair statistics.
If Fang and Atishay are found to be unclear regarding repair ranges and acquiring position data of failure cells out of repair ranges of allocated row standby circuits and allocated column standby circuits to generate the corresponding simulation repair result, Lee discloses the same (Fig. 15; ¶¶82, 84). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Fang, Atishay, and Lee, because doing so would have involved merely the routine combination of known elements according to known techniques, or the use of a known technique to improve similar devices in the same way to achieve the predictable results of determining out-of-range unrepairable failure cells during repair simulation. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Fang discloses simulations of repairs using redundant resources, but may be found to be unclear regarding the details of the repair simulation. Lee provides additional detail for determining out-of-range unrepairable cells during repair simulation. The teachings of Lee are directly applicable to Fang in the same way, so that Fang would similarly determine out-of-range unrepairable cells during repair simulation in order to accurately determine whether all failures are repairable.
Response to Arguments
Applicant's arguments filed 17 January 2026 have been fully considered but they are not persuasive.
Applicant asserts that Fang and Atishay fail to disclose that the historical test data is the historical test data in a design cycle. Remarks 10. The examiner disagrees. Fang explicitly states that the process of determining post-repair yields, illustrated in Fig. 6, occurs within “an exemplary procedure for selecting an optimum design to make the most economical choices among a variety of options, taking into consideration the impact that memory repair has on the resulting product” (col. 11, lines 7-11; emphasis added). As discussed throughout Fang, the failure and repair simulations are performed on an existing design to determine optimal changes (see also col. 2, lines 21-35). Atishay similarly discloses that failure and repair simulation is to predict wafer yield for different designs before manufacturing a memory device (Abstract; p. 117, col. 2, second to last paragraph). Performing yield analysis on test data of designs in order to determine appropriate changes clearly constitutes a “design cycle”, contrary to Applicant’s assertions.
Applicant further asserts that Fang and Atishay fail to disclose the limitations from original claims 6 and 8, but does not provide any explanation or reasoning for why the cited portions of Fang and Atishay fail to disclose those features. With regard to “obtaining a yield of the products based on the simulation repair result and the historical test data” and “obtaining RDC data meeting requirements in the various RDC data are explicitly disclosed by both Fang and Atishay; in both Fang and Atishay, the yield analysis is based on simulated repairs and faults from historical test data, and the RDCs that produce working devices are determined. Applicant’s description of what the claimed invention does, “allocates the repair schemes from the acquired RDC data to the failure cells in the acquired historical test data according to the preset RA, acquires the corresponding simulation repair result, and obtains the yield of the products based on the simulation repair result and the historical test data”, is exactly what both Fang (Fig. 6) and Atishay (p. 121 and Fig. 10) do, and both Fang and Atishay provide Applicant’s asserted advantages, as discussed above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARIC LIN whose telephone number is (571)270-3090. The examiner can normally be reached M-F 07:30-17:00 ET.
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8 May 2026
/ARIC LIN/ Examiner, Art Unit 2851
/JACK CHIANG/ Supervisory Patent Examiner, Art Unit 2851
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