DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 13-14, 16, 18, 21 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al., hereinafter Wang (US 2018/0130760 A1) and in further view of Vanfleteren et al, hereinafter Vanfleteren (US 7,759,167 B2).
Re claim 1: Wang teaches (1A-1D). An assembly used for integrated circuit manufacturing, comprising: a substrate (CP); a release layer (DB) disposed over the substrate (CP); a plurality of components (110) disposed over the release layer (DB), wherein the plurality of components (110) each comprise an active face (SA) in contact with the release layer (DB); and an embedding material layer (120/130 hereinafter EML) encapsulating (as shown in fig. 1D) the plurality of components (110).
Wang is silent to teach wherein the release layer comprises a light activated digital release material and a thickness of at most about 5 um;
and wherein a spacing between adjacent components of the plurality of components is at most about 20 um;
Vanfleteren teaches (fig.1 and 7-8) wherein the release layer (PI) comprises a light activated digital release material (photodefinable polyimide, col.11 lines 58-64) and a thickness of at most about 5 um (col.7 lines 37-38);
and wherein a spacing (5) between adjacent components (4) of the plurality of components (4) is at most about 20 um (fig.7 shows the top PI layer being 20 um therefore the spacing 5 between components 4 is much smaller than 20 um);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the release layer material and spacing between components as taught by Vanfleteren in the release layer and device of Wang in order to have the predictable result of improving flatness of the package for better stacking capabilities in chip packages (col 11 line 62 – col 12 line 22 of Vanfleteren).
Re claim 2: Wang teaches the assembly of Claim 1, wherein each of the active faces (SA) of the components (110) do not substantially contact (as shown in 1D) the embedding material (EML).
Re claim 3: Wang teaches the assembly of Claim 1, wherein the embedding material layer (EML) comprises a plurality of embedding material sublayers (EML consists of 130 and 120) wherein the plurality of embedding material sublayers comprise a first embedding material sublayer (120) and a second embedding material sublayer (130).
Re claim 13: Wang teaches the assembly of Claim 1, wherein the substrate (CP) comprises pores (the substrate can be composed of ceramic which is commonly known to be porous, p.17).
Re claim 14: Wang teaches (fig. 1A-1D and p.17-23) A process of fabricating (p.17-23) the assembly of Claim 1, comprising: depositing (p.17) the plurality of components (110) onto the release layer (DB), wherein the release layer (DB) is disposed over the substrate (CP); and encasing (p.19) the plurality of components (110) with the embedding material layer (EML).
Re claim 16: Wang in view of Vanfleteren teaches a process (fig 1D-1F, p.25-26 of Wang) of integrating an assembly into an integrated circuit, comprising: separating (peeling process mentioned in p.25 of Wang) the release layer (DB of Wang would be the same material as PI of Vanfleteren as as mentioned in claim 1) from the plurality of components (110 of Wang) encapsulated (as shown in fig,1D of Wang) by the embedding material layer (120 and 130 hereinafter EML of Wang) of the assembly of Claim 1 to form a laminate (120/130/110 as shown in 1E of Wang); wherein separating (col.10, lines 43-56 of Vanfleteren) comprises irradiating and heating the release layer (DB of Wang) ; and depositing an interconnect material (140 of Wang) over each of the exposed surfaces (SA of Wang) of the plurality of components (110 of Wang) to form a wired laminate (110,120,130 and 140 together hereinafter WL of Wang).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the removal method of the release layer as taught by Vanfleteren in the device of Wang in order to have the predictable result of improving the spacing/hole quality and reducing debris caused during removal of the release layer. (col.10 lines 43-56 of Vanfleteren)
Re claim 18: Wang teaches (1F) A laminate (110/120/130) for integrating into a circuit device, comprising: a plurality of components (110) each comprising a plurality of encapsulated surfaces (SB and SC, hereinafter ES, is encapsulated by 120 and 130) and an exposed surface (SA); and an embedding material (120 and 130, hereinafter EML) encapsulating the plurality of encapsulated surfaces (ES) of the plurality of components (110) wherein each of the exposed surfaces (SA) comprises a pad (although not mentioned, interconnect layer 140 is placed on SA and there seems to be pads which are commonly known to be used to connect an interconnect layer as shown in figure below).
; wherein each of the exposed surfaces (SA) are substantially coplanar with each other (as shown in fig.1D)
Wang is silent to explicitly teach wherein each of the exposed surfaces (SA) are substantially coplanar with each other (as shown in fig.1D) and comprise a discontinuity of at most about 1 um (fig.7 shows the entire PI layer is 20 um so it can be inferred the exposed surface (tops of 4) are around 1 um).
Vanfleteren teaches (fig.1 and 7-8) wherein each of the exposed surfaces (top of 4) are substantially coplanar with each other (as shown in fig.1) and comprise a discontinuity (as shown in fig.1) of at most about 1 um (.
Re claim 21: Wang teaches the laminate of Claim 18, further comprising interconnect materials (140) disposed over each of the exposed surfaces (SA).
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Re claim 25: Wang teaches the assembly of Claim 3, wherein the first embedding material sublayer (120 of EML) comprises a thermal conductivity comparable to silicon (120 can be Silicone par.19), and wherein the second embedding material sublayer comprises a CTE comparable to silicon (130 can be polysiloxane, par.22).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al., hereinafter Wang (US 2018/0130760 A1) in view of Vanfleteren et al, hereinafter Vanfleteren (US 7,759,167 B2) and in further view of Hohlfeld et al, hereinafter Hohlfeld (US 2014/0197551 A1).
Re claim 26: Wang teaches the assembly of Claim 1,
Wang and Vanfleteren are silent to teach wherein the embedding material layer does not comprise a polymer material.
Hohlfeld teaches the embedding material layer (12) does not comprise a polymer material (can be ceramic or glass, par.14)
It would have been obvious to one of ordinary skill in the art to have the embedding material layer of Wang comprise of ceramic or glass as taught by Hohlfeld instead of polymers since ceramic and glass is commonly known to be used as an encapsulant to provide better thermal stability, electrical insulation and mechanical resistance compared to polymers and ultimately improve the performance of the semiconductor device.
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Wang and Vanfleteren as applied to claim 1 above, and further in view of Meitl (US 2018/0323178 A1).
Re claim 11: Wang in view of Vanfleteren is silent as to explicitly teaching the assembly of Claim 1, wherein the release layer comprises an undercut region positioned between the release layer and at least one component of the plurality of components.
Wang in view of Meitl teaches (fig.2H of Meitl) the assembly of Claim 1, wherein the release layer (DB of Wang) comprises an undercut region (gaps 32 of Meitl would be under DB of Wang) positioned between the release layer (DB of Wang) and at least one component of the plurality of components (110 of Wang).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to etch the release layer of Wang to form a gap as taught by Meitl in order to have the predictable result of better control during the transfer process of the component and reflect or absorb any shock wave during manufacturing and ultimately mitigate any damage to the device (p.150-152 of Meitl).
Re claim 12: Wang in view of Vanfleteren in view of Meitl teaches the assembly of Claim 11, wherein the undercut region (32 of Meitl) comprises a deposited material (60 can be dielectric material such as SiO, p.144 of Meitl, and would be within undercut area 32 of Meitl in device of Wang).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the deposited material 60 of Meitl in the device of Wang in order to have the predictable result of protecting the plurality of components and mitigate damage to a completed device (p.150 of Meitl).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Vanfleteren as applied to claim 14 above, and further in view of Sheats (US 2007/0040258 A1).
Re claim 15: Wang in view of Vanfleteren is silent as to explicitly teaching the process of Claim 14, wherein encasing the plurality of components with the embedding material layer is performed by a spray process.
Wang and Vanfleteren in view of Sheats teaches the process of Claim 14, wherein encasing the plurality of components (110 of Wang) with the embedding material layer (EML of Wang) is performed by a spray process (p.31 of Sheats).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the embedding material layer of Wang by spray coating as mentioned in Sheats since it is a well-known technique to ensure proper adhesion and coverage to the release layer and ultimately improve contact reliability against thermal recycling in the device (p.31-33 of Sheats)
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Vanfleteren as applied in claim 16 above.
Re claim 17: Wang in view of Vanfleteren is silent to teach the process of Claim 16, further comprising placing the wired laminate (WL) into a device and electrically connecting the wired laminate (WL) to the device.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recognize the wired laminate would be put into a device and electrically connected since it is part of a chip package and chip packages are known to be in most common devices such as mobile devices.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICKY VERDES whose telephone number is (703)756-1401. The examiner can normally be reached Monday - Friday 07:30 - 03:30 PM.
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/RICKY VERDES/
Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898