DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is Final and is in response to the claims filed 07/24/2026. Claims 1-30 are currently pending, of which claims 1-4, 6-8, 13-19, 21-23, 26-30 are currently rejected. Claims 5, 9-11, 12, 20, and 24-25 are objected.
Response to Arguments
Applicants arguments filed on 07/24/2026 have been fully considered.
35 U.S.C. 112(b): Rejections under 35 U.S.C. 112(b) have been withdrawn necessitated by amendments.
35 U.S.C. 103: Applicants arguments regarding the 35 U.S.C. rejection of claim 2 have been considered, but they are not persuasive.
Applicant argues in page 11 that Ould-Ahmed-Vall does not teach the broadcast circuitry of claim 2. Specifically, Applicant argues:
The opcode 3102 indicates that a processor is to form a new tile 3103 from Tile A and from Tile B, each stored in a buffer 2705. See id. To form the new tile 3103, selection circuitry 2733 selects columns from Tile A and from Tile B based on, respectively, the source location field 3104 and the source location field 3106. See id. Thus, the cited portions of Ould-Ahmed-Vall describe an opcode for forming a new tile from existing tiles. The opcode identifies, to selection circuitry, the columns of the existing tiles from which to select to form the new tile. The cited portions of Ould-Ahmed-Vall fail to disclose that, for each unit of a tile, the selection circuitry broadcasts the unit to respective distinct inputs of multiple inputs of multiply-accumulate circuitry (MAC). Therefore, the cited portions of Ould-Ahmed-Vall do not disclose that "the processor further comprises broadcast circuitry configured to, for each element of the multiple elements [of the first input sub-vector value], provide the element to a respective distinct input of multiple inputs of the MAC," as in claim 2.
Examiner respectfully disagrees. Ould-Ahmed-Vall teaches a selection circuitry that selects a logical tile from both tiles A and B to form an input matrix that is input to the FMA Grid. There is no limitation in claim 2 that requires all elements of each tile to be provided to a MAC (FMA Grid). Claim 2 states “for each element of the multiple elements, provide the element to a respective distinct input of multiple inputs of the MAC.” There is no limitation that states that the multiple elements have to consist of all elements in both tiles. Hence, Ould-Ahmed-Vall in view of Muller teach claim 2. However, See new 35 U.S.C. 103 rejection below necessitated by amendments.
Applicant additionally argues in page 13 that Muller does not teach the broadcast circuitry of claim 2. Specifically, Applicant argues:
Thus, the cited portions of Muller describe a rotation operation performed on elements of an output register. The cited portions of Muller do not disclose that, for each element of an input sub-vector value, broadcast circuitry provides the element to a respective distinct input of multiple inputs of a MAC. Therefore, the cited portions of Muller do not disclose that "the processor further comprises broadcast circuitry configured to, for each element of the multiple elements [of the first input sub-vector value], provide the element to a respective distinct input of multiple inputs of the MAC," as in claim 2.
Examiner respectfully disagrees. Examiner did not rely on Muller for the rejection of claim 2. Instead, Examiner relied on Ould-Ahmed-Vall in view of Muller. However, See new 35 U.S.C. 103 rejection below necessitated by amendments.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
The following limitations invoke 35 U.S.C. 112(f) because they use the words means and are not
modified by sufficient structure, material, or acts for performing the claimed function:
Claim 29:
means for rotating a first plurality of sub-vector values in a rotation vector register of a rotation vector register file
means for reading the first input sub-vector value from the dedicated portion of the rotation vector register
means for receiving first input data at multiply-accumulate circuitry (MAC) from the rotation vector register file
means for receiving second input data at the MAC from a source vector register of a second vector register file
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
The corresponding structure as described in the specification is identified as follow:
The “means for rotating a first plurality of sub-vector values in a rotation vector register of a rotation vector register file” is disclosed in ¶0183 as “one or more of the rotators 172A-172M, the rotation circuitry 142, the rotation VR file 140, the one or more processors 190, the device 102, the system 100 of FIG. 1A, the processor 2406, the one or more processors 2410, the device 2400, one or more other circuits or components configured to rotate data in a rotation vector register of a rotation vector register file, or any combination thereof.”
The “means for reading the first input sub-vector value from the dedicated portion of the rotation vector register” is disclosed in ¶0058 as “the selection circuitry 146 is configured to read data from a dedicated portion of each of the rotation VRs 144A-144N and is not configured to read data from remaining portions of each of the rotation VRs 144A-144N.”
The “means for receiving first input data at multiply-accumulate circuitry (MAC) from the rotation vector register file” is disclosed in ¶0184 as “one or more of the inputs 407A-H of the MAC 160, the one or more processors 190, the device 102, the system 100 of FIG. 1A, the processor 2406, the one or more processors 2410, the device 2400, one or more other circuits or components configured to receive input data at the MAC from the rotation vector register file, or any combination thereof.”
The “means for receiving second input data at the MAC from a source vector register of a second vector register file” is disclosed in ¶0185 as “one or more of the inputs 409A-H of the MAC 160, the one or more processors 190, the device 102, the system 100 of FIG. 1A, the processor 2406, the one or more processors 2410, the device 2400, one or more other circuits or components configured to receive input data at the MAC from the source vector register, or any combination thereof.”
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4, 6, 13-16, 18-19, 21, and 26-27, 29-30 are rejected under 35 U.S.C. 103 as being unpatentable over OULD-AHMED-VALL (U.S. Patent Application Publication No.: US 20220206989 A1), hereinafter “Ould-Ahmed-Vall”, in view of MULLER, HENDKIK LAMBERTUS (WIPO International Application No.: WO 2021160300 A1) (cited in IDS on 08/03/2023), hereinafter “Muller”.
Regarding Claim 1, Ould-Ahmed-Vall teaches:
A device comprising a processor (Fig. 32) that includes:
…
a [register inside the shifter circuitry] configured to store a first plurality of sub-vector values corresponding to a first vector stored in a memory (Fig. 32, e.g., Shifter circuitry 3235 contains tile data T1(b) (register) received from data buffers),
a [shifter circuitry inside a P.E. Grid] configured to rotate the first plurality of sub-vector values in the rotation vector register (Fig. 32, e.g., Shifter circuitry 3235 contains tile data T1(b) (register); ¶0232, e.g., shifter circuitry 3235 shifts data to generate new matrix);
selection circuitry configured to read the first input sub-vector value from the dedicated portion … (Fig. 31, e.g., selection circuitry inputs data from logical tile into input matrix);
a second vector register file including a source vector register (Fig. 32, e.g., Data Buffers (registers) 3205 (second vector register file) stores data in Tiles T0-T2 (source vector register)); and
multiply-accumulate circuitry (MAC) [including shifter circuitry (rotation vector register file)] configured to receive, via the selection circuitry, first input data that includes the first input sub-vector value and to receive second input data from the source vector register (¶0226, e.g., P.E. Grid 3209 performs multiply add operation; ¶0074, e.g., matrix C can be used for multiply accumulate operations; Fig. 32, e.g., P.E. Grid 3209 (MAC) receives matrix A and C (second input data) from Data Buffers 3205 (source vector register) and B (first input data) from shifter circuitry 3235. Selection circuitry 3233 provides data to shifter circuitry).
Ould-Ahmed-Vall does not teach a multiply-accumulate circuitry (MAC) being a separate component from a rotation vector register file.
However, in the same field of endeavor, Muller teaches an output register rA that rotates vector data by shifting vector data in a circular manner implemented as a separate component outside of MAC architecture. See Muller: Fig. 4a.
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to modify the shifter circuitry implemented inside the P.E. Grid as taught by Ould-Ahmed-Vall to be implemented outside the MAC architecture as taught by Muller. One would have been motivated to combine these references because both references disclose shifting vector data inside registers, and Muller enhances the model of Ould-Ahmed-Vall by allowing for the P.E. Grid to be a separate component from the shifting circuitry for preventing single point of failures and allowing for load balancing using separate components.
Further, Ould-Ahmed-Vall does not teach:
a rotation vector register file comprising:
a rotation vector register configured to store a first plurality of sub-vector values corresponding to a first vector stored in a memory,
rotation circuitry configured to rotate data the first plurality of sub-vector values in the rotation vector register to position a first input sub-vector value of the first plurality of sub-vector values in a dedicated portion of the rotation vector register, and
selection circuitry configured to read the first input sub-vector value from the dedicated portion of the rotation vector register;
However, Muller teaches:
a rotation vector register configured to store a first plurality of sub-vector values corresponding to a first vector stored in a memory (Fig. 4A, e.g., shows register file 106 using output register rA storing vector data corresponding to vector values stored in memory 107; Page 14, Lines 12-15),
rotation circuitry configured to rotate data the first plurality of sub-vector values in the rotation vector register to position a first input sub-vector value of the first plurality of sub-vector values in a dedicated portion of the rotation vector register (Fig. 4A, e.g., shows register rA rotating vector values, where the left-most position (dedicated portion) contains vector value (first input sub-vector value) is used for accumulation; Page 14, Lines 12-15),
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to substitute the shifter circuitry taught by Ould-Ahmed-Vall with the register file taught by Muller. One would have been motivated to combine these references because both references disclose shifting vector data inside registers, and Muller enhances the model of Ould-Ahmed-Vall by allowing for a sequence of instructions to be handled when multiple passes need to be made, for example, when the matrix-vector multiplication is larger than the size supported. See Muller Page 2 Lines 20-24.
Ould-Ahmed-Vall in view of Muller discloses the claimed invention except for the selection circuity being inside the register file. It would have been obvious to one having ordinary skill in the art at the time the invention was made to include the selection circuitry taught by Ould-Ahmed-Vall inside the register file taught by Muller, since it has been held that forming in one piece an article, which has formerly been formed in two pieces and put together, involves only routine skill in the art. Howard v. Detroit Stove Works, 150 U.S. 164 (1893). The term “integral” is sufficiently broad to embrace constructions united by such means as fastening and welding. In re Hotte, 177 USPQ 326, 328 (CCPA 1973). The selection circuitry being inside the register file would not affect the function of the selection circuitry, as it would continue providing input data to the P.E. Grid.
Regarding Claim 3, Ould-Ahmed-Vall in view of Muller teach:
The device of claim 1, wherein the second vector register file includes an accumulate vector register, and wherein the MAC is configured to:
generate an output based on the first input data and the second input data; and
store the output in the accumulate vector register (Ould-Ahmed-Vall: Fig. 32, e.g., T2 (C) (accumulate vector register) stores updated C value, resulting from C+=AxB).
Regarding Claim 4, Ould-Ahmed-Vall in view of Muller teach:
The device of claim 1, wherein the second input data includes a second input sub-vector value (Ould-Ahmed-Vall: Fig. 31, e.g., shows Tiles A and B including selected elements in Logical tile (first and second sub-vector values)),
wherein the second vector register file includes an accumulate vector register, and wherein the MAC is configured to:
generate a first output sub-vector value based on the first input sub-vector value and the second input sub-vector value; and store the first output sub-vector value in the accumulate vector register (Ould-Ahmed-Vall: Fig. 32, e.g., T2 (C) (accumulate vector register) stores updated C value, resulting from C+=AxB).
Regarding Claim 6, Ould-Ahmed-Vall in view of Muller teach:
The device of claim 1, wherein the rotation circuitry is configured to rotate the first plurality of sub-vector values by a rotation amount (Muller: Fig. 4A, e.g., shows register file 106 using output register rA rotating data by one shift left; Page 14, Lines 12-15).
The motivation to combine provided with respect to claim 1 applies equally to claim 6.
Regarding Claim 13, Ould-Ahmed-Vall in view of Muller teach:
The device of claim 1, wherein the processor is configured to execute a multiply accumulate instruction to:
process the first input data and the second input data at the MAC (Ould-Ahmed-Vall: Fig. 32, e.g., P.E. Grid performs C+=AxB); and
rotate the first input sub-vector value in the rotation vector register to position a second input sub-vector value of the first plurality of sub-vector values in the dedicated portion of the rotation vector register. (Ould-Ahmed-Vall: ¶0232, e.g., shifter circuitry 3235 shifts data to generate new matrix).
Regarding Claim 14, Ould-Ahmed-Vall in view of Muller teach:
The device of claim 13, wherein the data is rotated in the rotation vector register after the first input data is retrieved from the rotation vector register file (Ould-Ahmed-Vall: ¶0217, e.g., multiple iterations are performed, hence data rotation would happen in every iteration (after data from previous cycle is retrieved)).
Regarding Claim 15, Ould-Ahmed-Vall in view of Muller teach:
The device of claim 1, wherein the processor is integrated into at least one of a mobile device, a headset device, a wearable electronic device, a wireless speaker and voice activated device, a camera device, an extended reality headset, or a vehicle (¶0354, e.g., processor may be incorporated into cell phones).
Regarding Claims 16, 18-19, 21, and 26, they are method claims practiced by the apparatus of claims 1, 3-4, 6, and 13, respectively. They are rejected for the same reasons as claims 1, 3-4, 6, and 13.
Regarding Claims 27, it is a media claim practiced by the apparatus of claim 1. It is rejected for the same reasons as claim 1.
Regarding Claims 29-30, they are means plus function claims practiced by the apparatus of claims 1 and 15, respectively. They are rejected for the same reasons as claims 1 and 15.
Claims 2, 17 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Ould-Ahmed-Vall in view of Muller, in view of Tatsumura et al. (U.S. Patent Application No.: US 20190278610 A1), hereinafter “Tatsumura”.
Regarding Claim 2, Ould-Ahmed-Vall in view of Muller teach:
The device of claim 1, wherein the first input sub-vector value has multiple elements (Muller: Fig. 4A, e.g., shows register rA storing multiple elements)
… for each element of the multiple elements, provide the element to a respective distinct input of multiple inputs of the MAC (Ould-Ahmed-Vall: Fig. 6, e.g., shows input data going to each FMA; Fig. 32, e.g., shows P.E. (FMA) Grid performing C+=AxB; Muller: Fig. 4A, e.g., shows register rA storing multiple elements).
Ould-Ahmed-Vall in view of Muller do not teach:
wherein the processor further comprises broadcast circuitry configured to, for each element of the multiple elements, provide the element to a respective distinct input of multiple inputs of the MAC.
However, Tatsumura teaches using a broadcast wire to input data from a memory to MAC operation modules. Tatsumura explains “One of the Pc memory blocks (the memory blocks Xmem0 to XmemPc−1: referring to FIG. 5) included in the Xmem memory is connected by a “broadcast wire” to the Pr MAC operation modules (the MAC operation modules MAC0 to MACPr−1). For example, the x0 data that is read from the memory block Xmem0 is supplied to all of the Pr MAC operation modules.” (See Tatsumura: ¶0096 and Fig. 5)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to modify the register file and the P.E. Grid as taught by Ould-Ahmed-Vall in view of Muller to be connected by a broadcast wire to provide inputs for MAC operations as taught by Tatsumura. One would have been motivated to combine these references because both references disclose performing MAC operations using data stored in memory, and Tatsumura enhances the model of Ould-Ahmed-Vall in view of Muller by allowing for data transferring between register file and P.E. Grid.
Regarding Claim 17, it is a method claim practiced by the apparatus of claim 2. It is rejected for the same reasons as claim 2.
Regarding Claim 28, it is a media claim practiced by the apparatus of claim 2. It is rejected for the same reasons as claim 2.
Claims 7-8 and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Ould-Ahmed-Vall in view of Muller, in view of Chilappagari et al. (U.S. Patent Application No.: US 20210406030 A1), hereinafter “Chilappagari”.
Regarding Claim 7, Ould-Ahmed-Vall in view of Muller teach the device of claim 1, Ould-Ahmed-Vall in view of Muller do not teach:
wherein the rotation vector register file is configured to rotate the data by a rotation amount.
However, Chilappagari teaches:
wherein the rotation vector register file is configured to rotate the data by a rotation amount (¶0028, e.g., control logic specifies amount of shift).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the Control logic to select shift amount as taught by Chilappagari with the system comprising a matrix operations accelerator as taught by Ould-Ahmed-Vall in view of Muller. One would have been motivated to combine these references because both references disclose shifting vector data inside registers, and Chilappagari enhances the model of Ould-Ahmed-Vall in view of Muller by allowing for shifting amount to be dynamically selected.
Regarding Claim 8, Ould-Ahmed-Vall in view of Muller in view of Chilappagari teach:
The device of claim 6, wherein the rotation amount is based on an opcode of a multiply accumulate instruction, a parameter of the multiply accumulate instruction, or both (Chilappagari: ¶0103, e.g., amount of shift is received as an input parameter).
The motivation to combine provided with respect to claim 7 applies equally to claim 8.
Regarding Claims 22-23, they are method claims practiced by the apparatus of claims 7-8, respectively. They are rejected for the same reasons as claims 7-8.
Allowable Subject Matter
Claims 5, 9-11, 12, 20, and 24-25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 5, 9-11, 12, 20, and 24-25 would be allowable for the reasons stated in non-final rejection on 05/18/2026.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CARLOS H DE LA GARZA whose telephone number is (571)272-0474. The examiner can normally be reached Monday-Friday 9:30AM-6PM.
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/C.H.D./
Carlos H. De La GarzaExaminer, Art Unit 2182 (571)272-0474
/EMILY E LAROCQUE/Primary Examiner, Art Unit 2182
