DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is non-final and is in response to the claims filed 05/02/2022. Claims 1-30 are currently pending, of which claims 1-4, 6-8, 13-19, 21-23, 26-30 are currently rejected. Claims 5, 9-11, 12, 20, and 24-25 are objected.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
The following limitations invoke 35 U.S.C. 112(f) because they use the words means and are not
modified by sufficient structure, material, or acts for performing the claimed function:
Claim 29:
means for rotating data in a rotation vector register of a rotation vector register file
means for receiving first input data at multiply-accumulate circuitry (MAC) from the rotation vector register file
means for receiving second input data at the MAC from a source vector register of a second vector register file
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
The corresponding structure as described in the specification is identified as follow:
The “means for rotating data in a rotation vector register of a rotation vector register file” is disclosed in ¶0183 as “one or more of the rotators 172A-172M, the rotation circuitry 142, the rotation VR file 140, the one or more processors 190, the device 102, the system 100 of FIG. 1A, the processor 2406, the one or more processors 2410, the device 2400, one or more other circuits or components configured to rotate data in a rotation vector register of a rotation vector register file, or any combination thereof.”
The “means for receiving first input data at multiply-accumulate circuitry (MAC) from the rotation vector register file” is disclosed in ¶0184 as “one or more of the inputs 407A-H of the MAC 160, the one or more processors 190, the device 102, the system 100 of FIG. 1A, the processor 2406, the one or more processors 2410, the device 2400, one or more other circuits or components configured to receive input data at the MAC from the rotation vector register file, or any combination thereof.”
The “means for receiving second input data at the MAC from a source vector register of a second vector register file” is disclosed in ¶0185 as “one or more of the inputs 409A-H of the MAC 160, the one or more processors 190, the device 102, the system 100 of FIG. 1A, the processor 2406, the one or more processors 2410, the device 2400, one or more other circuits or components configured to receive input data at the MAC from the source vector register, or any combination thereof.”
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8 and 23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites the limitation “wherein the rotation amount is based on an opcode of a multiply accumulate instruction or a parameter of the multiply accumulate instruction.” It is unclear if Applicant intends for the rotation amount to be based on either an opcode, or a parameter, or both. Examiner interprets this limitation as being either or of the opcode or the parameter for purposes of prior art rejections.
Claim 23 recites the same limitation as claim 8. It is rejected for at least the same reasons therein.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, 13-19, 21, and 26-30 are rejected under 35 U.S.C. 103 as being unpatentable over OULD-AHMED-VALL (U.S. Patent Application Publication No.: US 20220206989 A1), hereinafter “Ould-Ahmed-Vall”, in view of MULLER, HENDKIK LAMBERTUS (WIPO International Application No.: WO 2021160300 A1) (cited in IDS on 08/03/2023), hereinafter “Muller”.
Regarding Claim 1, Ould-Ahmed-Vall teaches:
A device comprising a processor (Fig. 32) that includes:
a [shifter circuitry inside a P.E. Grid] comprising a rotation vector register, [shifter circuitry] configured to rotate data in the rotation vector register (Fig. 32, e.g., Shifter circuitry 3235 contains tile data T1(b) (register); ¶0232, e.g., shifter circuitry 3235 shifts data to generate new matrix);
a second vector register file including a source vector register (Fig. 32, e.g., Data Buffers (registers) 3205 (second vector register file) stores data in Tiles T0-T2 (source vector register)); and
multiply-accumulate circuitry (MAC) [including shifter circuitry (rotation vector register file)] configured to receive first input data from the rotation vector register file and second input data from the source vector register (¶0226, e.g., P.E. Grid 3209 performs multiply add operation; ¶0074, e.g., matrix C can be used for multiply accumulate operations; Fig. 32, e.g., P.E. Grid 3209 (MAC) receives matrix A and C (second input data) from Data Buffers 3205 (source vector register) and B (first input data) from shifter circuitry 3235 (rotation vector register file)).
Ould-Ahmed-Vall also does not teach a multiply-accumulate circuitry (MAC) being a separate component from a rotation vector register file.
However, in the same field of endeavor, Muller teaches an output register rA that rotates vector data by shifting vector data in a circular manner implemented as a separate component outside of MAC architecture. See Muller: Fig. 4a.
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to modify the shifter circuitry implemented inside the P.E. Grid as taught by Ould-Ahmed-Vall to be implemented outside the MAC architecture as taught by Muller. One would have been motivated to combine these references because both references disclose shifting vector data inside registers, and Muller enhances the model of Ould-Ahmed-Vall by allowing for the P.E. Grid to be a separate component from the shifting circuitry for preventing single point of failures and allowing for load balancing using separate components.
Further, Ould-Ahmed-Vall does not teach:
a rotation vector register file comprising a rotation vector register, the rotation vector register file configured to rotate data in the rotation vector register;
However, Muller teaches:
a rotation vector register file comprising a rotation vector register, the rotation vector register file configured to rotate data in the rotation vector register (Fig. 4A, e.g., shows register file 106 using output register rA rotating data; Page 14, Lines 12-15);
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to substitute the shifter circuitry taught by Ould-Ahmed-Vall with the register file taught by Muller. One would have been motivated to combine these references because both references disclose shifting vector data inside registers, and Muller enhances the model of Ould-Ahmed-Vall by allowing for a sequence of instructions to be handled when multiple passes need to be made, for example, when the matrix-vector multiplication is larger than the size supported. See Muller Page 2 Lines 20-24.
Regarding Claim 2, Ould-Ahmed-Vall in view of Muller teach:
The device of claim 1, wherein the first input data includes a sub-vector value of the rotation vector register, wherein the sub-vector value has multiple elements (Ould-Ahmed-Vall: Fig. 31, e.g., shows Tile B including selected elements in Logical tile (subset of elements)), and
wherein the processor further comprises broadcast circuitry configured to, for each element of the multiple elements, provide the element to a respective distinct input of multiple inputs of the MAC (Ould-Ahmed-Vall: Fig. 31, e.g., Selection circuitry 2733 (broadcast circuitry) provides inputs from Tiles A and B into Input matrix 2818).
Regarding Claim 3, Ould-Ahmed-Vall in view of Muller teach:
The device of claim 1, wherein the second vector register file includes an accumulate vector register, and wherein the MAC is configured to:
generate an output based on the first input data and the second input data; and
store the output in the accumulate vector register (Ould-Ahmed-Vall: Fig. 32, e.g., T2 (C) (accumulate vector register) stores updated C value, resulting from C+=AxB).
Regarding Claim 4, Ould-Ahmed-Vall in view of Muller teach:
The device of claim 1, wherein the first input data includes a first input sub- vector value, wherein the second input data includes a second input sub-vector value (Ould-Ahmed-Vall: Fig. 31, e.g., shows Tiles A and B including selected elements in Logical tile (first and second sub-vector values)),
wherein the second vector register file includes an accumulate vector register, and wherein the MAC is configured to:
generate a first output sub-vector value based on the first input sub-vector value and the second input sub-vector value; and store the first output sub-vector value in the accumulate vector register (Ould-Ahmed-Vall: Fig. 32, e.g., T2 (C) (accumulate vector register) stores updated C value, resulting from C+=AxB).
Regarding Claim 6, Ould-Ahmed-Vall in view of Muller teach:
The device of claim 1, wherein the rotation vector register file is configured to rotate the data by a rotation amount (Muller: Fig. 4A, e.g., shows register file 106 using output register rA rotating data by one shift left; Page 14, Lines 12-15).
The motivation to combine provided with respect to claim 1 applies equally to claim 6.
Regarding Claim 13, Ould-Ahmed-Vall in view of Muller teach:
The device of claim 1, wherein the processor is configured to execute a multiply accumulate instruction to:
retrieve the first input data from the rotation vector register file;
retrieve the second input data from the source vector register (Ould-Ahmed-Vall: Fig. 32, e.g., P.E. Grid 3209 (MAC) receives matrix A and C (second input data) from Data Buffers 3205 (source vector register) and B (first input data) from shifter circuitry 3235 (rotation vector register file));
process the first input data and the second input data at the MAC (Ould-Ahmed-Vall: Fig. 32, e.g., P.E. Grid performs C+=AxB); and
rotate the data in the rotation vector register (Ould-Ahmed-Vall: ¶0232, e.g., shifter circuitry 3235 shifts data to generate new matrix).
Regarding Claim 14, Ould-Ahmed-Vall in view of Muller teach:
The device of claim 13, wherein the data is rotated in the rotation vector register after the first input data is retrieved from the rotation vector register file (Ould-Ahmed-Vall: ¶0217, e.g., multiple iterations are performed, hence data rotation would happen in every iteration (after data from previous cycle is retrieved)).
Regarding Claim 15, Ould-Ahmed-Vall in view of Muller teach:
The device of claim 1, wherein the processor is integrated into at least one of a mobile device, a headset device, a wearable electronic device, a wireless speaker and voice activated device, a camera device, an extended reality headset, or a vehicle (¶0354, e.g., processor may be incorporated into cell phones).
Regarding Claims 16-19, 21, and 26, they are method claims practiced by the apparatus of claims 1-4, 6, and 13, respectively. They are rejected for the same reasons as claims 1-4, 6, and 13.
Regarding Claims 27-28, they are media claims practiced by the apparatus of claims 1-2, respectively. They are rejected for the same reasons as claims 1-2.
Regarding Claims 29-30, they are means plus function claims practiced by the apparatus of claims 1 and 15, respectively. They are rejected for the same reasons as claims 1 and 15.
Claims 7-8 and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Ould-Ahmed-Vall in view of Muller, in view of Chilappagari et al. (U.S. Patent Application No.: US 20210406030 A1), hereinafter “Chilappagari”.
Regarding Claim 7, Ould-Ahmed-Vall in view of Muller teach the device of claim 1, Ould-Ahmed-Vall in view of Muller do no teach:
wherein the rotation vector register file is configured to rotate the data by a rotation amount.
However, Chilappagari teaches:
wherein the rotation vector register file is configured to rotate the data by a rotation amount (¶0028, e.g., control logic specifies amount of shift).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the Control logic to select shift amount as taught by Chilappagari with the system comprising a matrix operations accelerator as taught by Ould-Ahmed-Vall in view of Muller. One would have been motivated to combine these references because both references disclose shifting vector data inside registers, and Chilappagari enhances the model of Ould-Ahmed-Vall in view of Muller by allowing for shifting amount to be dynamically selected.
Regarding Claim 8, Ould-Ahmed-Vall in view of Muller in view of Chilappagari teach:
The device of claim 6, wherein the rotation amount is based on an opcode of a multiply accumulate instruction or a parameter of the multiply accumulate instruction (Chilappagari: ¶0103, e.g., amount of shift is received as an input parameter).
The motivation to combine provided with respect to claim 7 applies equally to claim 8.
Regarding Claims 22-23, they are method claims practiced by the apparatus of claims 7-8, respectively. They are rejected for the same reasons as claims 7-8.
Allowable Subject Matter
Claims 5, 9-11, 12, 20, and 24-25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Ould-Ahmed-Vall – teaches a system comprising a matrix (tile) operations accelerator to perform multiply accumulate operations on matrices. The matrix operations accelerator uses a P.E. Grid to perform the Multiply accumulate operation, and further uses shifter circuitry inside the P.E. Grid to perform shifting of data within matrix input data. See Figs. 32-35 and ¶0223-0241. Ould-Ahmed-Vall does not teach or suggest the shifter circuitry including two rotators, nor receiving by a MAC a second and third input data to be used with first input data to generate a second output vector to be stored in the accumulate vector register. Instead, Ould-Ahmed-Vall teaches generating an updated C value using inputs C, A, and B, and outputting a single output vector to be stored in the accumulate vector register.
Muller – teaches a vector processing instruction to process a matrix and a vector. Muller uses a register file that uses register rA to shift data to be inputted in the accumulator, and register rV to hold input data for the multiply-accumulate operation. See Figs. 4a-5b and corresponding description. Muller does not teach or suggest the shifter circuitry including two rotators, nor receiving by a MAC a second and third input data to be used with first input data to generate a second output vector to be stored in the accumulate vector register. Instead, Muller teaches inputting shifted data to the accumulator part of the multiply-accumulate operation, and does not show using a second rotator in the shifting operation, nor using MAC a second and third input data from a source register to be used with first input data from a rotation register to be stored in an accumulator register.
Chilappagari – teaches a computer system that uses a SIMD block to perform MAC operations on operands A and B. Operands are stored in respective register files and are multiplied-accumulated in SIMD blocks. See Chilappagari: Figs. 5-23 and corresponding description. Chilappagari does not teach or suggest the shifter circuitry including two rotators, nor receiving by a MAC a second and third input data to be used with first input data to generate a second output vector to be stored in the accumulate vector register. Instead, Chilappagari teaches performing multiply-accumulate operations using data from operands A and B, where operand B shifted before being routed to SIMD Engines, but is silent in receiving by a MAC a second and third input data to be used with first input data to generate a second output vector to be stored in the accumulate vector register, and using two coupled rotators to rotate data in a register.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CARLOS H DE LA GARZA whose telephone number is (571)272-0474. The examiner can normally be reached Monday-Friday 9:30AM-6PM.
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/C.H.D./
Carlos H. De La GarzaExaminer, Art Unit 2182 (571)272-0474
/EMILY E LAROCQUE/Primary Examiner, Art Unit 2182
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