Prosecution Insights
Last updated: April 19, 2026
Application No. 17/662,517

SYSTEMS AND METHODS OF PLACING SUBSTRATES IN SEMICONDUCTOR MANUFACTURING EQUIPMENT

Non-Final OA §103§112
Filed
May 09, 2022
Examiner
MCCLAIN, GERALD
Art Unit
3652
Tech Center
3600 — Transportation & Electronic Commerce
Assignee
Eugenus Inc.
OA Round
3 (Non-Final)
74%
Grant Probability
Favorable
3-4
OA Rounds
2y 7m
To Grant
89%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allow Rate
575 granted / 773 resolved
+22.4% vs TC avg
Moderate +15% lift
Without
With
+14.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
42 currently pending
Career history
815
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
36.9%
-3.1% vs TC avg
§102
34.7%
-5.3% vs TC avg
§112
22.8%
-17.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 773 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 13 November 2025 has been entered. Claim Interpretation The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: securing device (Claims 1-2, 4-6, 8-15, and 17-22; all real structures have a portions that are perpendicular to each other), sensor assembly (Claims 1, 3-6, 8-15, and 17-22), memory device (Claims 1-6, 8-15, and 17-22), and optical sensor assembly (Claim 2). Claim Rejections - 35 USC § 112 Claims 1-6, 8-15, and 17-22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim limitation “memory device” invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. A memory device is a device that has memory. There is no structure disclosed in the written description for the structure thereto. The drawings only have black box 424 in FIG. 4A that does not disclose structure. Memory is not a structure. (Humans have (abstract) memory.) Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph. Claims 2-6, 8-15, and 17-22 depend on Claim 1. Claim Rejections - 35 USC § 103 Claim(s) 1-5, 8-15, and 17-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Johanson et al. (US 6405101) in view of Hayashi (US 6368450) (“PRIOR ART” of FIG. 10-11). Johanson discloses: Claim 1: calibrating a process position (inside 2; column 3, lines 4-21) of a semiconductor substrate (“wafer”) in a semiconductor process chamber (2), comprising: a sensor assembly (14A/14B; column 3, lines 19-21) configured to detect a position of the calibration substrate while the calibration substrate is transferred out of the semiconductor process chamber using a robot arm (FIG. 1; 6); and a memory device (column 6, lines 31-36) communicatively coupled to the robot arm (part of “robot of the semiconductor manufacturing equipment” in at least FIG. 1) and configured to record coordinates of the robot arm corresponding to the detected position of the calibration substrate (column 4, line 40, et seq.); Claim 2: wherein the sensor assembly comprises an optical sensor assembly comprising a pair of light sources configured to emit a pair of light beams in a substrate transfer path between the semiconductor process chamber and a transfer chamber connected to the semiconductor process chamber (“model E3L-2LE4-50 sensors from Omron Electronics, Inc. of Schaumburg, Ill” has pair of light sources, etc.; see attached NPL reference; 14A/14B); Claim 4: a robot controller (FIG. 2B, 6), wherein the robot controller is configured to, prior to placing a production semiconductor substrate at the centered process position, detect a position of the production semiconductor substrate using the sensor assembly and adjust the robot arm based on the detected position of the calibration substrate such that the semiconductor substrate is placed on the susceptor at the centered process position (column 4, line 40, et seq.); Claim 15: closing the processing chamber (at least required for vapor deposition); subjecting the calibration substrate to a process condition different from the open chamber condition (at least for vapor deposition); transferring the calibration substrate from the susceptor using the robot arm (6); detecting the position of the calibration substrate using the sensor assembly and recording the coordinates of the robot arm corresponding to the detected position of the calibration substrate (14A/14B); Claim 17: wherein the open chamber condition exposes the calibration substrate to an external atmosphere (9 is external to 2); Claim 19: placing a production semiconductor substrate on the susceptor to be processed at the centered process position using the recorded coordinates of the robot arm (FIG. 6-7); Claim 20: prior to placing the production semiconductor substrate on the susceptor, detecting a position of the production semiconductor substrate and adjusting the robot arm based on the detected position of the calibration substrate such that the production semiconductor substrate is placed on the susceptor at the centered process position (FIG. 6-7); Claim 21: wherein the detected position of the calibration substrate is obtained by detecting the position of the calibration substrate while transferring the calibration substrate using a pair of light beams in the substrate transfer path between the process chamber and a transfer chamber connected to the process chamber (14A/14B; FIG. 2A-2B); Claim 22: wherein detecting using the pair of light beams comprises detecting two or more edge regions of the calibration substrate as the calibration substrate crosses the pair of light beams (14A/14B; FIG. 2A-2B). Johanson does not directly show: Claim 1: a securing device configured to be removably disposed on a susceptor and laterally surround a calibration substrate to prevent the calibration substrate from sliding laterally on the susceptor by more than 2 mm from a centered process position relative to a center of the susceptor, wherein the securing device extends around an upper edge of the susceptor and has a horizontal portion contacting and resting on an upper surface of the susceptor and a vertical portion surrounding the susceptor; Claim 3: wherein the securing device comprises a ring structure configured to fixedly surround the calibration substrate on the susceptor; Claim 5: wherein the robot controller is further configured to adjust the robot arm based on the detected position of the calibration substrate when the detected position of the semiconductor substrate and the detected position of the calibration substrate are offset from each other by more than about 0.1 mm; Claim 8: wherein in a cross-sectional view in a horizontal direction, the securing device has an inverted L shape having the horizontal portion adjoined by the vertical portion, the horizontal portion extending inwards toward the center of the susceptor; Claim 9: wherein a length of extension of the horizontal portion inwards toward the center of the susceptor defines an inner diameter of the ring structure that is greater than a diameter of the calibration substrate by 2 mm or less; Claim 10: wherein the horizontal portion is configured to contact and rest on an outer edge region of the upper surface of the susceptor; Claim 11: wherein the calibration substrate is configured to contact and rest on the outer edge region of the upper surface of the susceptor, such that a bottom surface of the horizontal portion of the securing device and a bottom surface of the calibration substrate are configured to be coplanar; Claim 12: wherein the horizontal portion has a thickness that is greater than a thickness of the calibration substrate, such that an edge of the calibration substrate sliding on the susceptor is stopped by the horizontal portion of the securing device; Claim 13: wherein the vertical portion of the securing device surrounds a vertical outer edge of the susceptor; Claim 14: wherein the securing device is configured to prevent the calibration substrate from sliding laterally on the susceptor by more than 2 mm in response to closing the semiconductor process chamber and subjecting the calibration substrate to a process condition comprising one or both of a higher process temperature and a lower process pressure relative an open chamber condition exposing the calibration chamber to an external atmosphere; Claim 15: securing the calibration substrate under an open chamber condition with the securing device to prevent the calibration substrate from sliding laterally on the susceptor by more than 2 mm from the centered process position; Claim 18: wherein subjecting the calibration substrate to the process condition comprises subjecting to one or both of a higher process temperature and a lower process pressure relative the open chamber condition; Claim 23: wherein the vertical portion is horizontally interposed between the susceptor and an outer cylindrical support structure surrounding the susceptor, and wherein the securing device is fixedly attached to the cylindrical support structure. Hayashi shows a similar device having: Claim 1: a securing device (portion of 4 on 2) configured to be removably disposed on a susceptor and laterally surround the calibration substrate to prevent a calibration substrate from sliding laterally on the susceptor by more than 2 mm from a centered process position relative to a center of the susceptor (about 1 mm; column 1, lines 39-49), wherein the securing device extends around an upper edge of the susceptor and has a horizontal portion contacting and resting on an upper surface of the susceptor and a vertical portion surrounding the susceptor (4 over 2/etc. in FIG. 10); Claim 3: wherein the securing device comprises a ring structure (portion of 4 on 2) configured to fixedly surround the calibration substrate on the susceptor; Claim 5: wherein the robot controller is further configured to adjust the robot arm based on the detected position of the calibration substrate when the detected position of the semiconductor substrate and the detected position of the calibration substrate are offset from each other by more than about 0.1 mm (column 1, lines 50-64; thermal expansion may generate about 2 mm offset); Claim 8: wherein in a cross-sectional view in a horizontal direction, the securing device has an inverted L shape having the horizontal portion adjoined by the vertical portion, the horizontal portion extending inwards toward the center of the susceptor (FIG. 10); Claim 9: wherein a length of extension of the horizontal portion inwards toward the center of the susceptor defines an inner diameter of the ring structure that is greater than a diameter of the calibration substrate by 2 mm or less (about 1 mm; column 1, lines 39-49); Claim 10: wherein the horizontal portion is configured to contact and rest on an outer edge region of the upper surface of the susceptor (FIG. 10); Claim 11: wherein the calibration substrate is configured to contact and rest on the outer edge region of the upper surface of the susceptor, such that a bottom surface of the horizontal portion of the securing device and a bottom surface of the calibration substrate are configured to be coplanar (FIG. 10); Claim 12: wherein the horizontal portion has a thickness that is greater than a thickness of the calibration substrate, such that an edge of the calibration substrate sliding on the susceptor is stopped by the horizontal portion of the securing device (FIG. 10; MPEP 2115; further, W in FIG. 10 is an example substrate; 4 still prevents W from sliding laterally); Claim 13: wherein the vertical portion of the securing device surrounds a vertical outer edge of the susceptor (FIG. 10); Claim 14: wherein the securing device is configured to prevent the calibration substrate from sliding laterally on the susceptor by more than 2 mm in response to closing the semiconductor process chamber and subjecting the calibration substrate to a process condition comprising one or both of a higher process temperature and a lower process pressure relative an open chamber condition exposing the calibration chamber to an external atmosphere (column 1, lines 50-64; thermal expansion may generate about 2 mm offset); Claim 15: securing the calibration substrate under an open chamber condition with the securing device (portion of 4 on 2) to prevent the calibration substrate from sliding laterally on the susceptor by more than 2 mm from the centered process position (about 1 mm; column 1, lines 39-49); Claim 18: wherein subjecting the calibration substrate to the process condition comprises subjecting to one or both of a higher process temperature and a lower process pressure relative the open chamber condition (at least column 1, lines 39-60 of Hayashi; it is noted that Johanson teaches vapor disposition in column 2, lines 30-41; pressure effects are proportional to temperature effects); Claim 23: wherein the vertical portion is horizontally interposed between the susceptor and an outer cylindrical support structure surrounding the susceptor, and wherein the securing device is fixedly attached to the cylindrical support structure (lowermost portion of 4 fixed in FIG. 10); with a reasonable expectation of success for the purpose of providing a readily available and relatively inexpensive conventional susceptor (column 1, lines 39-64). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Johanson as taught by Hayashi and include Hayashi’s similar device having: Claim 1: a securing device configured to be removably disposed on a susceptor and laterally surround the calibration substrate to prevent a calibration substrate from sliding laterally on the susceptor by more than 2 mm from a centered process position relative to a center of the susceptor, wherein the securing device extends around an upper edge of the susceptor and has a horizontal portion contacting and resting on an upper surface of the susceptor and a vertical portion surrounding the susceptor; Claim 3: wherein the securing device comprises a ring structure configured to fixedly surround the calibration substrate on the susceptor; Claim 5: wherein the robot controller is further configured to adjust the robot arm based on the detected position of the calibration substrate when the detected position of the semiconductor substrate and the detected position of the calibration substrate are offset from each other by more than about 0.1 mm; Claim 8: wherein in a cross-sectional view in a horizontal direction, the securing device has an inverted L shape having the horizontal portion adjoined by the vertical portion, the horizontal portion extending inwards toward the center of the susceptor; Claim 9: wherein a length of extension of the horizontal portion inwards toward the center of the susceptor defines an inner diameter of the ring structure that is greater than a diameter of the calibration substrate by 2 mm or less; Claim 10: wherein the horizontal portion is configured to contact and rest on an outer edge region of the upper surface of the susceptor; Claim 11: wherein the calibration substrate is configured to contact and rest on the outer edge region of the upper surface of the susceptor, such that a bottom surface of the horizontal portion of the securing device and a bottom surface of the calibration substrate are configured to be coplanar; Claim 12: wherein the horizontal portion has a thickness that is greater than a thickness of the calibration substrate, such that an edge of the calibration substrate sliding on the susceptor is stopped by the horizontal portion of the securing device; Claim 13: wherein the vertical portion of the securing device surrounds a vertical outer edge of the susceptor; Claim 14: wherein the securing device is configured to prevent the calibration substrate from sliding laterally on the susceptor by more than 2 mm in response to closing the semiconductor process chamber and subjecting the calibration substrate to a process condition comprising one or both of a higher process temperature and a lower process pressure relative an open chamber condition exposing the calibration chamber to an external atmosphere; Claim 15: securing the calibration substrate under an open chamber condition with the securing device to prevent the calibration substrate from sliding laterally on the susceptor by more than 2 mm from the centered process position; Claim 18: wherein subjecting the calibration substrate to the process condition comprises subjecting to one or both of a higher process temperature and a lower process pressure relative the open chamber condition; Claim 23: wherein the vertical portion is horizontally interposed between the susceptor and an outer cylindrical support structure surrounding the susceptor, and wherein the securing device is fixedly attached to the cylindrical support structure; with a reasonable expectation of success for the purpose of providing a readily available and relatively inexpensive conventional susceptor. Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Johanson in view of Hayashi and Ottens et al. (US 7453063) (“Ottens”). Johanson discloses all the limitations of the claims as discussed above. Johanson does not directly show: Claim 6: wherein the calibration substrate is formed of a material different from the semiconductor substrate. Ottens shows a similar device having: Claim 6: wherein the calibration substrate is formed of a material different from the semiconductor substrate (ceramic (etc.) calibration substrate (column 7, line 40 to column 8, line 26) and semiconductor substrate (column 1, line 20)); with a reasonable expectation of success for the purpose of providing a calibration substrate with low thermal expansion so temperature changes do not greatly affect the calibration steps with the calibration substrate for improved calibration for processing semiconductor substrates (column 7, line 40 to column 8, line 26). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Johanson and Hayashi as taught by Ottens and include Ottens’s similar device having: Claim 6: wherein the calibration substrate is formed of a material different from the semiconductor substrate; with a reasonable expectation of success for the purpose of providing a calibration substrate with low thermal expansion so temperature changes do not greatly affect the calibration steps with the calibration substrate for improved calibration for processing semiconductor substrates. Response to Arguments Applicant's arguments filed 13 November 2025 have been fully considered but the 112(b) rejections are not persuasive. Re. the 112(f) claim interpretations, Applicant did not specifically argue against them. Re. 112(b) rejections, a memory device is a device that has memory. There is no structure disclosed in the written description for the structure thereto. The drawings only have black box 424 in FIG. 4A that does not disclose structure. The structure of the memory device must be within the four walls of the current application; they are not. Claiming that the memory device is communicatively coupled to the robot arm does not denote structure of the memory device; the robot arm is a structure separate from the memory device. Describing how the memory device interacts with other structures does not (a) define structure(s) of the memory device. Further, memory is not a structure. (Humans have (abstract) memory.) Applicant’s arguments re. the 103 rejections, see pp. 7-10, filed 13 November 2025, with respect to the rejection(s) of claim(s) 1-6, 8-15, and 17-22 under Johanson et al. have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Johanson, Hayashi (prior art), et al. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Gerald McClain whose telephone number is (571)272-7803. The examiner can normally be reached Monday through Friday from 8:30 a.m. to 5:00 p.m. and at gerald.mcclain@uspto.gov (see MPEP 502.03 (II)). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Saul Rodriguez can be reached at (571) 272-7097. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Gerald McClain/Primary Examiner, Art Unit 3652
Read full office action

Prosecution Timeline

May 09, 2022
Application Filed
Jan 19, 2023
Response after Non-Final Action
Feb 26, 2025
Non-Final Rejection — §103, §112
Jun 02, 2025
Response Filed
Aug 13, 2025
Final Rejection — §103, §112
Nov 13, 2025
Request for Continued Examination
Nov 22, 2025
Response after Non-Final Action
Nov 22, 2025
Non-Final Rejection — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
74%
Grant Probability
89%
With Interview (+14.8%)
2y 7m
Median Time to Grant
High
PTA Risk
Based on 773 resolved cases by this examiner. Grant probability derived from career allow rate.

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