Prosecution Insights
Last updated: July 17, 2026
Application No. 17/663,087

TUNABLE BUS FOR OPERATING CROSS-RESONANCE QUANTUM GATES

Final Rejection §103
Filed
May 12, 2022
Examiner
ALAWDI, ANWER AHMED
Art Unit
2851
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
International Business Machines Corporation
OA Round
3 (Final)
80%
Grant Probability
Favorable
4-5
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
4 granted / 5 resolved
+12.0% vs TC avg
Strong +25% interview lift
Without
With
+25.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 8m
Avg Prosecution
19 currently pending
Career history
37
Total Applications
across all art units

Statute-Specific Performance

§103
92.1%
+52.1% vs TC avg
§102
5.0%
-35.0% vs TC avg
§112
3.0%
-37.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 5 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Detailed Action Claims 1-13 have been withdrawn from consideration. Claim 18 has been canceled. Claims 14-17, 19, and 20 are pending. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 14 – 17, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US20190164076A1 (Kim) in view of US20180225586A1 (Chow) and further in view of US20170193388A1 (Filipp). In regards to claim 14 (Kim) shows a method, comprising: defining a qubit connectivity sub-lattice from a fixed grid lattice of qubits; Kim [0040] teaches that each of the control units 120a, 120b through 120k is independently programmable and controls a distinct set of qubits within the larger qubit system; the distinct set of qubits that are operated together under a single independently programmable control unit constitutes a defined, connected subset of the qubit array — i.e., a qubit connectivity sub-lattice partitioned from the overall qubit system — thereby teaching defining a qubit connectivity sub-lattice from a lattice of qubits. defining a second qubit connectivity sub-lattice from the fixed grid lattice of qubits; Kim [0040]-[0041] teach that a second independently programmable control unit (120b) controls a second distinct set of qubits in a different region of the qubit system, teaching defining a second qubit connectivity sub-lattice. wherein the second qubit connectivity sub-lattice is composed of a second group of qubits from the fixed grid lattice; Kim [0040]-[0041] teach that the second control unit (120b) controls a second distinct set of qubits, teaching that the second qubit connectivity sub-lattice is composed of a second group of qubits. wherein the qubit connectivity sub-lattice is distinct from the second qubit connectivity sub-lattice; Kim [0041] teaches that each control unit handles its assigned qubits in a different region of the qubit system, wherein the qubit sub-lattice of each control unit is thereby distinct from the others, teaching that the qubit connectivity sub-lattice is distinct from the second qubit connectivity sub-lattice. wherein the qubit connectivity sub-lattice and the second qubit connectivity sub-lattice comprise non-overlapping groups; Kim [0040] teaches that each control unit controls a distinct set of qubits, and Kim [0041] teaches that each control unit handles its assigned qubits in a different region of the qubit system; a distinct set of qubits occupying a different spatial region necessarily shares no qubit with another such set, because each qubit has a fixed physical location and can occupy only one region; the first and second qubit groups are therefore structurally non-overlapping rather than merely characterized as such, thereby teaching that the qubit connectivity sub-lattice and the second qubit connectivity sub-lattice comprise non-overlapping groups. Kim differs from the claimed invention in that it does not explicitly disclose wherein the qubit connectivity sub-lattice is composed of a group of qubits from the fixed grid lattice that are operably coupled by cross-resonance gate operations and tunable microwave resonator buses; the tunable microwave resonator buses, wherein the qubits are arranged in a fixed grid lattice; Chow teaches wherein the qubit connectivity sub-lattice is composed of a group of qubits from the fixed grid lattice that are operably coupled by cross-resonance gate operations and tunable microwave resonator buses; Chow [0027]-[0028] teach two fixed-frequency transmon qubits coupled through a bus resonator (a superconducting coplanar waveguide resonator), wherein a cross-resonance gate comprises the control qubit, the target qubit, and the bus resonator; Chow [0045] further teaches that the cross-resonance drive is a microwave tone applied to the control qubit at the target qubit's frequency through the bus, thereby entangling the qubits, so that the coupling is achieved entirely through microwave control of the resonator bus; Chow thus teaches that the group of qubits are operably coupled by cross-resonance gate operations. Chow differs from the claimed invention in that it does not explicitly disclose the tunable microwave resonator buses or the qubits arranged in a fixed grid lattice. Filipp teaches the tunable microwave resonator buses, wherein the qubits are arranged in a fixed grid lattice; Filipp [0016]-[0017] teach two fixed-frequency transmon qubits coupled by a frequency-tunable coupling element, the coupling element having a SQUID loop whose frequency is tuned by flux modulation, and Filipp [0027] and FIG. 3 teach a two-dimensional square lattice of qubits interconnected via such tunable coupling elements coupling neighboring qubits, thereby teaching the qubits arranged in a fixed grid lattice and operably coupled by tunable microwave resonator buses. The motivation to combine Kim and Chow at the effective filing date of the invention is to implement cross-resonance gate operations in Kim's partitioned qubit sub-lattice architecture using Chow's all-microwave entanglement technique. The motivation to combine Kim, Chow, and Filipp at the effective filing date of the invention is to provide the fixed grid lattice and tunable microwave resonator buses of Filipp's tunable coupling architecture on which Kim's sub-lattices are partitioned and Chow's cross-resonance gate operations are performed. In regards to claim 15 (Kim in view of Chow) does not show: wherein adjacent qubits of the fixed grid lattice are coupled together by the tunable microwave resonator buses. Filipp teaches wherein adjacent qubits of the fixed grid lattice are coupled together by the tunable microwave resonator buses; Filipp [0027] and FIG. 3 teach a two-dimensional square lattice in which neighboring qubits are interconnected via tunable coupling elements, thereby teaching that adjacent qubits of the fixed grid lattice are coupled together by the tunable microwave resonator buses. The motivation to combine Kim and Chow at the effective filing date of the invention is to implement cross-resonance gate operations in Kim's partitioned qubit sub-lattice architecture using Chow's all-microwave entanglement technique. The motivation to combine Kim, Chow, and Filipp at the effective filing date of the invention is to couple adjacent qubits of the sub-lattice through Filipp's tunable coupling elements interconnecting neighboring qubits in the two-dimensional lattice. In regards to claim 16 (Kim in view of Chow) does not show: setting a first tunable microwave resonator bus to a first frequency to minimize one or more quantum interactions between a first qubit pair from the group of qubits from the fixed grid lattice that are not connected in the qubit connectivity sub-lattice. Filipp teaches setting a first tunable microwave resonator bus to a first frequency to minimize one or more quantum interactions between a first qubit pair from the group of qubits from the fixed grid lattice that are not connected in the qubit connectivity sub-lattice; Filipp [0019] teaches that the coupling is zero when the qubits and the coupler are sufficiently far detuned, and Filipp [0027] teaches that in the two-dimensional lattice the qubits are detuned in their idle state such that the interaction is essentially switched off, thereby teaching setting a first tunable microwave resonator bus to a first frequency to minimize one or more quantum interactions between a first qubit pair from the group of qubits from the fixed grid lattice that are not connected in the qubit connectivity sub-lattice. The motivation to combine Kim and Chow at the effective filing date of the invention is to implement cross-resonance gate operations in Kim's partitioned qubit sub-lattice architecture using Chow's all-microwave entanglement technique. The motivation to combine Kim, Chow, and Filipp at the effective filing date of the invention is to use Filipp's frequency-tunable coupling to switch off interactions between non-connected qubit pairs while enabling cross-resonance gate operations between connected pairs. In regards to claim 17 (Kim in view of Chow) does not show: setting a second tunable microwave resonator bus to a second frequency that enables a cross-resonance gate operation via a bypass capacitor coupling between a second qubit pair from the qubits from the fixed grid lattice that are directly connected in the qubit connectivity sub-lattice. Filipp teaches setting a second tunable microwave resonator bus to a second frequency that enables a cross-resonance gate operation via a bypass capacitor coupling between a second qubit pair from the qubits from the fixed grid lattice that are directly connected in the qubit connectivity sub-lattice; Filipp [0027] teaches that, by modulating the frequency of the tunable coupler, a pairwise qubit-qubit interaction is switched on by driving at the difference frequency between the selected qubits, and Filipp [0016] and [0027] teach that the qubits are capacitively coupled to the tunable coupling element, thereby teaching setting a second tunable microwave resonator bus to a second frequency that enables a gate operation via a capacitive (bypass capacitor) coupling between a second directly connected qubit pair. The motivation to combine Kim and Chow at the effective filing date of the invention is to implement cross-resonance gate operations in Kim's partitioned qubit sub-lattice architecture using Chow's all-microwave entanglement technique. The motivation to combine Kim, Chow, and Filipp at the effective filing date of the invention is to enable cross-resonance gate operations between directly connected qubit pairs of the sub-lattice by switching on Filipp's tunable coupling at the difference frequency of the selected pair. In regards to claim 19 (Kim) shows the method of claim 14: wherein the qubit connectivity sub-lattice is associated with a first quantum processor, and wherein the second qubit connectivity sub-lattice is associated with a second quantum processor; Kim [0064] teaches multi-core quantum processing unit (QPU) systems comprising a network of quantum cores, and Kim [0069] teaches a plurality of quantum cores 370a, 370b, 370m, each quantum core comprising one or more qubits and constituting a quantum processor; the qubit sub-lattice of a first quantum core is thereby associated with a first quantum processor and the qubit sub-lattice of a second quantum core is associated with a second quantum processor, teaching that the qubit connectivity sub-lattice is associated with a first quantum processor and the second qubit connectivity sub-lattice is associated with a second quantum processor. In regards to claim 20 (Kim) does not show: wherein qubits from the fixed grid lattice are fixed frequency superconducting qubits. Chow teaches wherein qubits from the fixed grid lattice are fixed frequency superconducting qubits; Chow [0027] teaches that the system comprises two fixed-frequency transmon qubits; a transmon qubit is a superconducting qubit, and Chow operates the cross-resonance gate by driving the control qubit at the fixed resonance frequency of the target qubit, thereby teaching that the qubits of the fixed grid lattice are fixed frequency superconducting qubits. The motivation to combine Kim and Chow at the effective filing date of the invention is to implement the qubits of the sub-lattice as Chow's fixed-frequency superconducting qubits, which are suited for cross-resonance gate operations. Response to Arguments Applicant's arguments filed on 30 April 2026 have been fully considered but are not persuasive for the reasons set forth below. Applicant's remarks assert that an agreement was reached during the April 16, 2026 telephonic interview that the "non-overlapping groups" amendment overcomes the rejection. The Examiner's position is established by this written Office Action, which constitutes the official record of examination. See MPEP 713.04 ("the results of an interview...must be confirmed in a written Office action"). The amended claims have been fully considered on their merits and, for the reasons set forth herein, the rejection is maintained. With respect to claim 14, Applicant argues that the amendment reciting "the qubit connectivity sub-lattice and the second qubit connectivity sub-lattice comprise non-overlapping groups" overcomes the rejection over Kim and Chow. The Examiner respectfully disagrees. The primary basis for this position is Kim [0041], which teaches that each control unit handles its assigned qubits "in a different region" of the qubit system. A "region" is a physical, spatial division of the qubit array on the hardware substrate. Because each qubit occupies a fixed physical location, a qubit assigned to one spatial region cannot simultaneously be assigned to a different spatial region. The qubit groups respectively assigned to Kim's different spatial regions are therefore structurally and physically non-overlapping. This is not an inherency argument — it is the direct structural consequence of Kim's explicit teaching that the qubit groups reside "in a different region." The amended limitation "non-overlapping groups" does not distinguish the claimed subject matter from the prior art of record. With respect to the dependent claims (claims 15, 16, 17, 19, and 20), Applicant argues that these claims are allowable by virtue of their dependency from independent claim 14. However, since claim 14 remains unpatentable over the prior art of record for the reasons set forth above, the dependent claims are similarly unpatentable. The specific limitations of the dependent claims are additionally addressed by the teachings of Kim, Chow, and Filipp as discussed in the claim analysis above. Accordingly, the rejections of all pending claims are maintained. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANWER AHMED ALAWDI whose telephone number is (703)756-1018. The examiner can normally be reached Monday - Friday 8:00 am - 5:30 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on (571)-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANWER AHMED ALAWDI/Examiner, Art Unit 2851 /JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851
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Prosecution Timeline

May 12, 2022
Application Filed
Sep 24, 2025
Non-Final Rejection mailed — §103
Dec 24, 2025
Response Filed
Mar 25, 2026
Non-Final Rejection mailed — §103
Apr 30, 2026
Response Filed
Jun 18, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 4 most recent grants.

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Prosecution Projections

4-5
Expected OA Rounds
80%
Grant Probability
99%
With Interview (+25.0%)
3y 8m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 5 resolved cases by this examiner. Grant probability derived from career allowance rate.

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