Prosecution Insights
Last updated: April 19, 2026
Application No. 17/664,086

PROTECTING A CIRCUIT FROM AN INPUT VOLTAGE

Non-Final OA §102§103
Filed
May 19, 2022
Examiner
BARTOL, LANCE TORBJORN
Art Unit
2843
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Microchip Technology Inc.
OA Round
3 (Non-Final)
78%
Grant Probability
Favorable
3-4
OA Rounds
3y 5m
To Grant
99%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allow Rate
29 granted / 37 resolved
+10.4% vs TC avg
Strong +31% interview lift
Without
With
+30.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
38 currently pending
Career history
75
Total Applications
across all art units

Statute-Specific Performance

§103
54.5%
+14.5% vs TC avg
§102
18.2%
-21.8% vs TC avg
§112
26.3%
-13.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 37 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submissions filed on December 1 and December 18, 2025 have been entered. Response to Amendment The Amendment filed December 1, 2025 has been entered. Claims 1-6 and 19-23 remain pending in the application. Response to Arguments Applicant's arguments filed December 1, 2025 have been fully considered but they are not persuasive. Applicant argues that previously presented prior art reference Camagna et al. (Patent Publication Number WO 2007/121148 A2), as cited by applicant, hereafter referred to as Camagna, fails to disclose an operational amplifier that generates differential output biasing signals, and that therefore the rejection of independent claim 1 is improper. Examiner respectfully disagrees. Furthermore, applicant argues that Camagna fails to disclose the operational amplifier decreasing the DC common-mode voltage at first and second terminals of connectors, and that therefore the rejections of independent claims 19 and 21 are improper. Examiner respectfully disagrees. Regarding claim 1, applicant argues that amplifier 1714 of Fig. 17B of Camagna discloses a single control signal, in contrast to differential control signals. Fig. 17B of Camagna is reproduced below: PNG media_image1.png 575 745 media_image1.png Greyscale As shown in annotated Fig. 17B above, amplifier 1714 clearly discloses two output control signals (see “Differential Control Signals”) and that both of the outputs of amplifier 1714 are coupled to control device 1716. Therefore, 1716 responds to differential control signals from amplifier 1714. Furthermore, applicant argues that Camagna describes a negative input of amplifier 1714 being connected to a common-mode voltage derived from resistors. However, as shown above in Fig. 17B, the negative input of 1714 is coupled to capacitors, not resistors, and furthermore, applicant’s cited sections of Camagna (Page 31, lines 33-36 and Page 32, lines 1-3) refer to capacitors, not resistors. See pages 31-32 of Camagna reproduced below: PNG media_image2.png 891 598 media_image2.png Greyscale PNG media_image3.png 887 573 media_image3.png Greyscale As shown above, the cited sections of Camagna clearly refer to capacitors, not resistors. Furthermore, applicant argues that Camagna describes a single control signal 1718 on page 33, lines 1-3 of Camagna. However, Camagna does not describe this. Page 33 of Camagna is reproduced below: PNG media_image4.png 880 574 media_image4.png Greyscale As shown in page 33 of Camagna above, lines 1-3 do not disclose anything relating to a single control signal 1718. Furthermore, reference character 1718 is only used to refer to capacitors coupled to the input of amplifier 1714 (Camagna, Page 31, line 36-Page 32, line 3, “Capacitors 1718 coupled to the input Sine to the common-mode suppression amplifier 1714 may be implemented on a high voltage semiconductor die to facilitate blockage of high DC voltage”), see also pages 31-32 of Camagna reproduced above, which clearly state that reference character 1718 (not present in Fig. 17B) refers to capacitors, not to a single control signal). Therefore, applicant’s arguments are unconvincing and the rejections of claims 1, and 2-6 as dependent on claim 1, are maintained. Regarding claims 19 and 21, applicant argues that Camagna fails to disclose either “decrease a direct current (DC) common-mode voltage at the first and second connectors” or “decreasing the DC common-mode voltage at the first terminal and the second terminal” because Camagna explicitly preserves DC signal components and cites page 12, lines 4-5, and page 31, lines 1-4 of Camagna. See page 12 of Camagna reproduced below: PNG media_image5.png 881 573 media_image5.png Greyscale As shown in pages 12 and 31 of Camagna above, the cited portions of Camagna do not relate to preserving DC signal components, with page 12 relating to power source devices providing an open circuit at Ethernet frequencies and a short circuit at lower frequencies, and page 31 relates to suppressing common-mode noise without referring to either high frequency or DC noise. Therefore, Camagna does not explicitly disclose preserving DC signal components. Therefore, applicant’s arguments are unconvincing and the rejections of claims 19 and 21 (and claim 20 dependent on claim 19 and claims 22-23 dependent on claim 21) are maintained. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-2 and 19-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Camagna. Regarding claim 1, Camagna discloses: An apparatus (Camagna, Fig. 17B), comprising: one or more circuits (Fig. 17B, 1708, 1712, and 1730) to draw current from, or provide current to, a pair of connectors for an input circuit (Fig. 17B, 1706, see connection between 1730 and 1706), the pair of connectors for electrical coupling to first and second terminals of a twisted pair (see Fig. 2, an example of a larger system which can contain the network system of Fig. 17B, and twisted pairs 208, connected to network connectors 206), respective ones of the one or more circuits having a first inputs and a second input (Fig. 17B, 1708) respectively at least partially responsive to positive and negative biasing signals (Fig. 17B, see outputs of amplifier 1714); and an operational amplifier (Fig. 17B, 1714) to generate the positive and negative biasing signals (Fig. 17B, see outputs of 1714) as separate signals (Fig. 17B, see that outputs of 1714 correspond to positive and negative outputs), the operational amplifier comprising: a first input terminal (Fig. 17B, see positive input of 1714) at least partially responsive to a reference voltage (Fig. 17B, see VREF at positive input of 1714); and a second input terminal (Fig. 17B, see positive input of 1714) at least partially responsive to a direct current (DC) common-mode voltage of the input circuit (Page 31, lines 33-36). Regarding claim 2, Camagna further discloses: wherein the second input terminal of the operational amplifier is at least partially responsive to a feedback voltage (Camagna, Fig. 17B, see feedback loop from output of 1714 through circuits 1730 to positive input of 1714) and the feedback voltage is observable at a node electrically connected to both of the pair of connectors (Fig. 17B see connection between 1706, positive input of 1714, and controller 1716). Regarding claim 19, Camagna discloses: A system (Camagna, Fig. 17B), comprising: first and second connectors (Fig. 17B, 1706) for electrical coupling to respective first and second terminals of a twisted pair (see Fig. 2, an example of a larger system which can contain the network system of Fig. 17B, and twisted pairs 208, connected to network connectors 206); and one or more circuits (Fig. 17B, 1708, 1712, and 1730) coupled to the first and second connectors (Fig. 17B, see connection between 1730 and 1706) to decrease a direct current (DC) common-mode voltage at the first and second connectors (Page 30, lines 1-2 [capacitors 1712 are DC blocking capacitors and therefore block DC common-mode voltage]) and maintain a differential signal at the first and second connectors (Page 12, lines 4-5) by selectively drawing current from, or providing current to, the first and second connectors symmetrically (Page 45, lines 29-31 [network device of Camagna is configured to use balanced signals]) at least partially responsive to separate positive and negative biasing signals (Fig. 17B, see differential connections between 1706 and outputs of 1714). Regarding claim 20, Camagna further discloses: further comprising: an operational amplifier (Camagna, Fig. 17B, 1714) to generate the positive and negative biasing signals (Fig. 17B, see outputs of 1714), the operational amplifier comprising: a first input terminal (Fig. 17B, see positive input of 1714) at least partially responsive to a reference voltage (Fig. 17B, see VREF at positive input of 1714); and a second input terminal (Fig. 17B, see positive input of 1714) at least partially responsive to the DC common-mode voltage (Page 31, lines 33-36). Regarding claim 21, Camagna discloses: A method comprising: generating a bias signal (Camagna, Fig. 17B, see outputs of amplifier 1714) at least partially responsive to a feedback signal (Fig. 17B, see feedback loop from output of 1714 to positive input of 1714), the feedback signal at least partially responsive to a direct current (DC) common-mode voltage (Page 31, lines 33-36) of a first terminal (Fig. 17B, see terminal 3 of 1706) and a second terminal (Fig. 17B, see terminal 6 of 1706); and decreasing the DC common-mode voltage at the first terminal and the second terminal (Page 31, lines 31-33) by providing current to, or drawing current from, the first terminal and the second terminal at least partially responsive to the bias signal (Fig. 17B, see connection between 1706 and output of 1714). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 3-4 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Camagna as applied to claims 1 and 21, respectively, above, and further in view of Yamaguchi (Patent Publication Number CN 1,484,307 A), hereafter referred to as Yamaguchi. Regarding claim 3, Camagna fails to disclose: comprising a feedback-voltage protection circuit to cause a feedback voltage to be within a threshold. However, Yamaguchi teaches comprising a feedback-voltage protection circuit (Yamaguchi, Fig. 14, D1 and D2) to cause a feedback voltage to be within a threshold (Page 5, 2nd Paragraph from bottom, lines 1-4). Camagna and Yamaguchi are both considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in radio frequency communications. Therefore it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Camagna to incorporate the teachings of Yamaguchi to include the feedback voltage protection circuit of Yamaguchi in the circuit of Camagna, which would have the effect of protecting the circuit components of Camagna from damage due to excess signal levels (Yamaguchi, Page 10, Paragraph 5, lines 1-4). Regarding claim 4, Camagna fails to disclose: wherein the feedback-voltage protection circuit comprises a first number of diodes arranged between a rail voltage and a node at the feedback voltage and a second number of diodes between the node at the feedback voltage and ground. However, Yamaguchi further teaches wherein the feedback-voltage protection circuit comprises a first number of diodes (Yamaguchi, Fig. 14, D1) arranged between a rail voltage (Fig. 14, see connection between D1 and VDD) and a node at the feedback voltage (Fig. 14, see connection between D1 and node from negative feedback loop) and a second number of diodes (Fig. 14, D2) between the node at the feedback voltage (Fig. 14, see connection between D2 and node from negative feedback loop) and ground (Fig. 14, see connection between D2 and VSS). Camagna and Yamaguchi are both considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in radio frequency communications. Therefore it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Camagna to incorporate the teachings of Yamaguchi to include the feedback voltage protection circuit of Yamaguchi in the circuit of Camagna, which would have the effect of protecting the circuit components of Camagna from damage due to excess signal levels (Yamaguchi, Page 10, Paragraph 5, lines 1-4). Regarding claim 23, Camagna fails to disclose: comprising: protecting an operational amplifier used to generate the bias signal by preventing the feedback signal from exceeding a threshold. However, Yamaguchi teaches comprising: protecting an operational amplifier (Yamaguchi, Fig. 14, OP) used to generate the bias signal (Fig. 14, see output of OP) by preventing the feedback signal from exceeding a threshold (Page 5, 2nd Paragraph from bottom, lines 1-4). Camagna and Yamaguchi are both considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in radio frequency communications. Therefore it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Camagna to incorporate the teachings of Yamaguchi to include the feedback voltage protection circuit of Yamaguchi in the circuit of Camagna, which would have the effect of protecting the circuit components of Camagna from damage due to excess signal levels (Yamaguchi, Page 10, Paragraph 5, lines 1-4). Claims 5-6 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Camagna as applied to claims 1 and 21, respectively, above, and further in view of Barnette et al. (Patent Publication Number US 2016/0233659 A1), hereafter referred to as Barnette. Regarding claim 5, Camagna fails to disclose: wherein each of the one or more circuits comprise: a current mirror to draw the current from, or provide the current to, the pair of connectors at least partially responsive to the positive and negative biasing signals. However, Barnette teaches wherein each of the one or more circuits comprise: a current mirror (Barnette, Fig. 2, 40) to draw the current from, or provide the current to, the pair of connectors (Fig. 2, see connection between 40 and 20 [load/connectors]) at least partially responsive to the positive and negative biasing signals (Fig. 2, see connection between 40 and 11 [input]). Camagna and Barnette are both considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in radio frequency communications. Therefore it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Camagna to incorporate the teachings of Barnette to include the current mirror of Barnette in the circuits of Camagna, which would have the effect of allowing for a current gain to amplify signals flowing through the apparatus of Camagna (Barnette, Paragraph 26, lines 5-11). Regarding claim 6, Camagna fails to disclose: wherein each of the one or more circuits comprise: a protection circuit to protect a transistor of the current mirror from a voltage of one of the pair of connectors. However, Barnette further teaches wherein each of the one or more circuits comprise: a protection circuit (Barnette, Fig. 2, 80) to protect a transistor of the current mirror from a voltage of one of the pair of connectors (Fig. 2, see transistor Q2 and Paragraph 32, lines 1-5). Camagna and Barnette are both considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in radio frequency communications. Therefore it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Camagna to incorporate the teachings of Barnette to include the current mirror of Barnette in the circuits of Camagna, which would have the effect of allowing for a current gain to amplify signals flowing through the apparatus of Camagna (Barnette, Paragraph 26, lines 5-11). Regarding claim 22, Camagna fails to disclose: comprising: protecting a transistor of a current mirror used to provide the current, or draw the current, by preventing a voltage at a source or drain of the transistor from exceeding a safe- operational threshold. However, Barnette teaches comprising: protecting a transistor (Barnette, Fig. 2, Q2) of a current mirror used to provide the current, or draw the current (Fig. 2, 40), by preventing a voltage at a source or drain of the transistor (Fig. 2, see source/drain of Q2) from exceeding a safe- operational threshold (Paragraph 32, lines 1-5). Camagna and Barnette are both considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in radio frequency communications. Therefore it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Camagna to incorporate the teachings of Barnette to include the current mirror of Barnette in the circuits of Camagna, which would have the effect of allowing for a current gain to amplify signals flowing through the apparatus of Camagna (Barnette, Paragraph 26, lines 5-11). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ripley et al. (Patent Number US 11,646,701) discloses (Fig. 6) an apparatus comprising multiple current mirrors as part of a feedback loop of an operational amplifier. Small et al. (Patent Publication Number US 2023/0253931) discloses (Fig. 3) an amplifier comprising multiple current mirrors as part of a feedback loop of a transistor amplifier and protection diodes. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lance T Bartol whose telephone number is (703)756-1267. The examiner can normally be reached Monday - Thursday 6:30 a.m. - 4:00 p.m. CT, Alternating Fridays 6:30 - 3:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached at 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LANCE TORBJORN BARTOL/Examiner, Art Unit 2843 /ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
Read full office action

Prosecution Timeline

May 19, 2022
Application Filed
Feb 19, 2025
Non-Final Rejection — §102, §103
Jul 28, 2025
Response Filed
Aug 19, 2025
Final Rejection — §102, §103
Dec 01, 2025
Response after Non-Final Action
Dec 29, 2025
Request for Continued Examination
Jan 16, 2026
Response after Non-Final Action
Jan 28, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
78%
Grant Probability
99%
With Interview (+30.8%)
3y 5m
Median Time to Grant
High
PTA Risk
Based on 37 resolved cases by this examiner. Grant probability derived from career allow rate.

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