DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 16-17 and 19-20 and is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Ozawa et al. (US 2008/0197403 A1).
Regarding claim 16, Ozawa et al. teach a semiconductor device comprising: memory cells (Figs. 1-2; [0041]), at least one memory cell of the memory cells (Figs. 1-2; [0041]) comprising: a control gate region (5; Fig. 2, [0047]) overlying a charge structure (3; Fig. 2, [0047]); a capping region (9; Fig. 2, [0047]) overlying the control gate region (5); a liner (the continuous section of 8 above the layer 4, where 8 and 42 can have different kinds of insulating films; Fig. 2, [0052]) directly contacting the capping region (9) and directly contacting sidewalls of the control gate region (5), the liner (the continuous section of 8 above the layer 4) not directly contacting sidewalls of the charge structure (3; see Fig. 2).
Regarding claim 17, Ozawa et al. teach the semiconductor device of claim 16, wherein the sidewalls of the control gate region (5) and sidewalls of the capping region (9) comprise substantially continuous vertical surfaces (see Fig. 2).
Regarding claim 19, Ozawa et al. teach the semiconductor device of claim 16, wherein the liner (the continuous section of 8 above the layer 4) extends substantially continuously over the capping region (9) and the sidewalls of the control gate region (5; see Fig. 2).
Regarding claim 20, Ozawa et al. teach the semiconductor device of claim 16, wherein an entire upper surface (the top horizontal surface) of the control gate region (5) is in direct contact with an entire lower surface (the bottom horizontal surface) of the capping region (9).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2009/0023279 A1) in view of Tong et al. (US 2014/0353795 A1), and further in view of Hieda (US 2004/0178470 A1).
Regarding claim 1, Kim et al. teach a semiconductor device (Fig. 2) comprising an array of memory cells (Fig. 1F; [0019]), at least one memory cell of the array of memory cells (Fig. 1F; [0019]) comprising: a control gate (110a; Fig. 1F, [0021]) electrically isolated from a charge structure (104a; Fig. 1F, [0025]) underlying the control gate (110a) by a dielectric material (106; Fig. 1F, [0019]); another dielectric material (102; Fig. 1F, [0016]) underlying the charge structure (104a) and overlying a material (100; Fig. 1F, [0016]); and a liner (114; Fig. 1F, [0023]) directly on sidewalls of the control gate (110a) and directly on sidewalls (left and right sidewalls) and an upper surface (the upper portion of the surfaces of the left and right sidewalls) of a capping region (112; Fig. 1F, [0020]) over the control gate (110a), the liner (114) not on sidewalls of the charge structure (104a), and a thickness of the liner (114) on the sidewalls of the capping region (112; a thickness of 114 near the bottom end of 112) greater than a thickness of the liner (114) on the sidewalls of the control gate (110a; a thickness of 114 near the bottom end of 110a).
Kim et al. do not teach the liner comprising hydrogen and at least one of an oxide, a nitride, or an oxynitride.
In the same field of endeavor of semiconductor manufacturing, Tong et al. teach the liner (60, Fig. 3, [0019]) comprising hydrogen and at least one of an oxide, a nitride, or an oxynitride (an ISSG oxide; [0019], the ISSG oxide would incorporate hydrogen as disclosed in the paragraph [0049] of the current application).
In the same field of endeavor of semiconductor manufacturing, Hieda teaches that the ISSG process can produce a uniform and high quality oxide film ([0073]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Kim et al. and Tong et al. and to use the ISSG produced oxide as the material of the liner (114) as taught by Tong et al. ([0019] of Tong et al.), because Hieda teaches that the ISSG process can produce a uniform and high quality oxide film ([0073] of Hieda).
Regarding claim 2, Kim et al. teach the semiconductor device of claim 1, wherein the control gate (110a) comprises a single material (tungsten; [0019]).
Regarding claim 3, Kim et al. teach the semiconductor device of claim 1, wherein the capping region (112).
Kim et al. do not teach the capping region comprises multiple dielectric materials.
In the same field of endeavor of semiconductor manufacturing, Hieda teaches the capping region (17/18; Fig. 7A, [0070]) comprises multiple dielectric materials (layers of silicon nitride and silicon oxide; [0070]).
Kim et al. teach all the claimed elements except that Kim et al. is using a single layer of SiON for a etch mask (112; [0020-0021]) rather than a double layer of silicon nitride and silicon oxide.
In the same field of endeavor of semiconductor manufacturing, Hieda teaches using a double layer of silicon nitride and silicon oxide for the etch mask (17/18; [0070]).
One of ordinary skill in the art would have recognized that a single layer of SiON and a double layer of silicon nitride and silicon oxide are known equivalents for providing the etch mask within the semiconductor art.
It would have been obvious to one of ordinary skill in the art at the time of invention was made to substitute one know element (a single layer of SiON) for another known equivalent element (a double layer of silicon nitride and silicon oxide) resulting in the predictable result of providing the etch mask (KSR rationales B).
Regarding claim 4, Kim et al. teach the semiconductor device of claim 1, the sidewalls of the control gate (110a) are substantially smooth and substantially continuous with the sidewalls of the caping region (112, see Fig. 1F).
Regarding claim 5, Kim et al. teach the semiconductor device of claim 1, wherein the liner (114).
Kim et al. do not teach the liner comprises a densified material comprising hydrogen-occupied bonds.
In the same field of endeavor of semiconductor manufacturing, Tong et al. teach the liner (60, Fig. 3, [0019]) comprises a densified material comprising hydrogen-occupied bonds (an ISSG oxide; [0019], the ISSG oxide is a densified material comprising hydrogen-occupied bonds as disclosed in the paragraph [0049] of the current application).
In the same field of endeavor of semiconductor manufacturing, Hieda teaches that the ISSG process can produce a uniform and high quality oxide film ([0073]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Kim et al. and Tong et al. and to use the ISSG produced oxide as the material of the liner (114) as taught by Tong et al. ([0019] of Tong et al.), because Hieda teaches that the ISSG process can produce a uniform and high quality oxide film ([0073] of Hieda).
Regarding claim 6, Kim et al. teach the semiconductor device of claim 1, wherein the control gate (110a) comprises tungsten ([0019]) and the liner (114).
Kim et al. do not teach the liner (114) comprises silicon oxide.
In the same field of endeavor of semiconductor manufacturing, Tong et al. teach the liner (114) comprises oxide (an ISSG oxide; [0019])
In the same field of endeavor of semiconductor manufacturing, Hieda teaches that the ISSG process can produce a uniform and high quality silicon oxide film ([0073]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Kim et al. Tong et al. and Hieda, and to use the ISSG produced silicon oxide as the material of the liner because Tong et al. suggested using ISSF oxide as the material of the liner ([0019] of Tong et al.), and Hieda teaches that the ISSG process can produce a uniform and high quality silicon oxide film ([0073] of Hieda).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ozawa et al. as applied to claim 16 above, and further in view of Wu (US 2004/0094794 A1).
Regarding claim 18, Ozawa et al. teach the semiconductor device of claim 16, wherein the sidewalls of the charge structure (3), the sidewalls of the control gate region (5) and sidewalls of the capping region (9).
Ozawa et al. do not teach the sidewalls of the charge structure are sloped relative to the sidewalls of the control gate region and sidewalls of the capping region
In the same field of endeavor of semiconductor manufacturing, Wu teaches the sidewalls of the charge structure (floating gate layer 302b; Fig. 2A, [0015]) are sloped relative to the sidewalls of the control gate region (310a/309b; Fig. 2A, [0015]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Ozawa et al. and Wu and to have a tapered shaped charge structure as taught by Wu, because the taper shape may enhance the tunneling current in the erased state as taught by Wu ([0015]).
The combination of Ozawa et al. and Wu teaches “the sidewalls of the charge structure are sloped relative to sidewalls of the capping region”, because Wu teaches that the sidewalls of the charge structure (floating gate layer 302b; Fig. 2A, [0015]) are sloped relative to the sidewalls of the control gate region (310a/309b; Fig. 2A, [0015]), and Ozawa et al. teach that sidewalls of the capping region (9) are aligned with sidewalls of the control gate region (5; see Fig. 2).
Response to Arguments
Applicant's arguments filed 02/17/2026 have been fully considered but they are not persuasive.
On pages 6-8 of Applicant’s Response regarding claim 16, Applicant argues that Ozawa does not teach “a liner directly contacting the capping region and directly contacting sidewalls of the control gate region, the liner not directly contacting sidewalls of the charge structure" of claim 16 based on that Applicant interpreted “a liner” as “insulating films 8” of Ozawa, while “insulating films 8” of Ozawa are direct contacting sidewalls of the charge structure 3.
The Examiner respectfully disagrees with Applicant’s argument, because the Examiner interpreted “a liner” as “the continuous section of 8 above the layer 4” of Ozawa, while “the continuous section of 8 above the layer 4” of Ozawa is not direct contacting sidewalls of the charge structure 3 in Fig. 2 of Ozawa and reads on the limitation “a liner directly contacting the capping region and directly contacting sidewalls of the control gate region, the liner not directly contacting sidewalls of the charge structure" as disclosed above in the rejections. The fundamental principle of Applicant’s construction of claim language is that “applicants are their own lexicographers”. The Examiner’s claim interpretation has to follow “broadest reasonable interpretation” (MPEP 2111). The term “a liner” is in singular form, which a person ordinary skill in the art would interpret as a single piece of the structure having the liner characteristics. The meaning of the liner is “one that lines or is used to line or back something” based on “https://www.merriam-webster.com/dictionary/liner”. The structure of “the continuous section of 8 above the layer 4” of Ozawa in Fig. 2 shows a single piece of the structure being the liner to the control gate region 5 of Ozawa, and directly contacting the capping region 9 of Ozawa and directly contacting sidewalls of the control gate region 5 of Ozawa, and not directly contacting sidewalls of the charge structure 3 of Ozawa. Thus, the examiner’s interpretation is reasonable and the rejections are correct.
On pages 9-10 of Applicant’s Response regarding claim 1, Applicant argues that the Office alleges that Kim teaches "a liner (114; Fig. 1F, [0023]) directly on sidewalls of the control gate (110a) and directly on sidewalls (left and right sidewalls) and an upper surface (the upper portion of the surfaces of the left and right sidewalls) of a capping region (112; Fig. 1F, [0020])," which interprets a single structure of Kim as being both "sidewalls" and "an upper surface." The Office cannot utilize a single structure disclosed in Kim to make obvious two different structures recited in claim 1.
The Examiner respectfully disagrees with Applicant’s argument, because, firstly, a single structure can anticipate two different structures if the two structures are included in “a single structure”. Secondly, the portion of the claim 1 in argument, “sidewalls and an upper surface of a capping region”, is claiming two features (sidewalls and an upper surface) of a single structure (a capping region), i.e. sidewalls of a capping region and an upper surface of a capping region. There is nothing wrong to use 112 of Kim to anticipate a single structure of a capping region and sidewalls and an upper surface of a capping region. Thus, the rejections are correct.
On pages 10-11 of Applicant’s Response regarding claim 1, Applicant argues that the Office’s interpretation of “an upper surface” as being “the upper portion of the surfaces of the sidewall” is not consistent with the ordinary meaning, the specification, and the interpretation of a person ordinary skill in the art, while the original meaning implied from the claims is that the “upper surface” of the capping region is different and distinct from the “sidewalls” of the capping region.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., the “upper surface” of the capping region is different and distinct from the “sidewalls” of the capping region) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Furthermore, the interpretation is consistent with the specification, where Fig. 6 of the current application shows upper surfaces of the capping region 160 include an upper portion of the surfaces of the sidewall of the capping region 160. A person ordinary skill in the art would also interpret the upper portion of the surfaces of the sidewall of the capping region as an upper surface of the capping region due to the plain meaning of “an upper surface” of the capping region can be any surface of the capping region at the upper portion of the capping region.
On pages 11-12 of Applicant’s Response, regarding claim 1, Applicant argues that Kim does not teach "a thickness of the liner on the sidewalls of the capping region greater than a thickness of the liner on the sidewalls of the control gate" of claim 1, based on that drawings alone cannot be used as portions if the drawings are not to scale.
The Examiner respectfully disagrees with Applicant’s argument, because the limitation "a thickness of the liner on the sidewalls of the capping region greater than a thickness of the liner on the sidewalls of the control gate" is claiming the relative thickness of the liner at different locations, which can be indicated by the shape of liner in the drawings. Fig. 1F of Kim teaches this feature: “a thickness of the liner (114) on the sidewalls of the capping region (112; a thickness of 114 near the bottom end of 112) greater than a thickness of the liner (114) on the sidewalls of the control gate (110a; a thickness of 114 near the bottom end of 110a).” This feature is not affected by the scaling of the drawings. Thus, Fig. 1F provides the solid support anticipating this limitation.
On page 13 of Applicant’s Response, Applicant argues that Kim does not teach "wherein the sidewalls of the control gate are substantially smooth" of claim 1.
The Examiner respectfully disagrees with Applicant’s argument, because it is implied in Fig. 1F of Kim that the sidewalls of the control gate (110a) are substantially smooth and substantially continuous with the sidewalls of the caping region (112, see Fig. 1F)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yonemochi et al. (US 2006/0231884 A1) teach a device have the control gates and floating gates covered by multiple liners.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/HSIN YI HSIEH/Primary Examiner, Art Unit 2899 5/30/2026
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