DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-23 are presented for examination.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 23, 2022 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
Examiner objects to the specification for containing various grammatical informalities. Examiner has attached a marked-up copy of the specification indicating where errors have occurred. To the extent that the markings are not self-explanatory and are not corrected, Examiner will enumerate the remaining objections in a subsequent Office Action.
The abstract of the disclosure is objected to because “one of the new value” should be “one of the new values”. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Objections
Claims 1-19 are objected to because of the following informalities: the beginning word “[m]ethod” should be “[a] method” in claim 1 and “[t]he method” in the claims that are dependent thereon.
Claim 9 is objected to because of the following informalities: “conductance” should be “conductances”.
Claims 14 and 16 are objected to because of the following informalities: “switch” should be “the switch”.
Claims 20-23 are objected to because of the following informalities: the beginning word “[e]lectronic” should be “[a]n electronic” in claim 20 and “[t]he electronic” in the claims that are dependent thereon.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “primary memory component” and “secondary memory component” in claim 20 and “first control module” and “second control module” in claim 21.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 20-23 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim limitations “primary memory component”, “secondary memory component”, “first control module”, and “second control module” invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the functions. Therefore, it is unclear that Applicant had possession of the claimed invention as of the effective filing date. See rejection under 35 USC § 112(b) infra for further analysis.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 19-23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim limitations “primary memory component”, “secondary memory component”, “first control module”, and “second control module” invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed functions and to clearly link the structure, material, or acts to the functions.
Regarding the memory components, several portions of the specification recite encoding functions (e.g., pages 3-4, 6, 9, 14-15, 19, and 21 of the originally filed specification), but in none of these locations is an algorithm for performing the encoding disclosed.
Regarding the control modules, at most, there is language at the top of page 12 of the specification as filed that largely repeats the claimed functions and then states that the control is to occur “in a coordinated manner”. Toward the bottom of page 15, there is also some discussion of the operations of the first control module, but nothing that could plausibly be called a full algorithm for performing the entire claimed function of controlling both the word lines and the sense lines. The top of page 20 suggests that the control modules perform read and write operations, but this is not directly related to the claimed functions of controlling the word, sense, and bit lines.
Therefore, the claims are indefinite and are rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claims so that the claim limitations will no longer be interpreted as limitations under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed functions, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the functions recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the functions so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed functions, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed functions and clearly links or associates the structure, material, or acts to the claimed functions, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed functions. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
The terms “low”, “long”, “high”, and “short” in claim 19 are relative terms which render the claim indefinite. The terms are not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The specification does not provide an explicit definition for any of the four words, and Examiner is unaware of any accepted standard in the art that would serve as a dividing line between a low and a high current and between a long and a short duration. For purposes of examination, any current of any duration will be deemed to read on the claim.
All claims dependent on a claim rejected hereunder are also rejected for being dependent on a rejected base claim.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The analysis of the claims will follow the 2019 Revised Patent Subject Matter Eligibility Guidance, 84 Fed. Reg. 50 (“2019 PEG”).
Claim 1
Step 1: The claim recites a method; therefore, it is directed to the statutory category of processes.
Step 2A Prong 1: The claim recites, inter alia:
[A] forward pass including calculating an output vector by applying the binarized neural network on an input vector in a forward direction from the input neurons to the output neurons: This limitation recites the mathematical concept of calculating an output vector using standard neural network calculations.
[A] backward pass including computing an error vector between the calculated output vector and a learning output vector and calculating a new value of the input vector by applying the binarized neural network on the error vector in a backward direction from the output neurons to the input neurons: This limitation recites the mathematical concept of computing an error and calculating a new value of the input via backpropagation.
[A] weight update including, for each binary weight: computing a product by multiplying a respective element of the error vector with a respective element of the new value of the input vector; modifying a latent variable depending on the product; and updating the respective binary weight as a function of the latent variable with respect to a threshold: This limitation recites the mathematical concept of computing a product, changing a latent variable based on the product, and performing a mathematical update of the weight by applying a function of the latent variable and a threshold.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. The claim further recites that the method is for “training a binarized neural network, the binarized neural network including input neurons for receiving input values, output neurons for delivering output values and intermediate neurons between the input and output neurons, a respective binary weight being associated to each connection between two respective neurons, the method being implemented by an electronic circuit” and that “each binary weight [is] encoded using at least one primary memory component; each latent variable [is] encoded using at least one secondary memory component, each secondary memory component ha[s] a characteristic subject to a time drift, [and] each one of the primary and secondary memory components [is] a phase-change memory device.” However, these are all mere instructions to apply the judicial exception using a generic computer programmed with a generic class of computer algorithm. MPEP § 2106.05(f).
Step 2B: The claim does not contain significantly more than the judicial exception. The additional elements amount to mere instructions to apply the judicial exception for the same reasons as given above. As an ordered whole, the claim is directed to a mathematical concept of training a binary neural network using generically recited hardware. Nothing in the claim provides significantly more than this. As such, the claim is not patent eligible.
Claim 2
Step 1: A process, as above.
Step 2A Prong 1: The claim recites the same judicial exceptions as in claim 1.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. The claim further recites that “each primary memory component has a characteristic subject to a time drift”. However, as above, this is a mere instruction to apply the judicial exception using a generic computer programmed with generic classes of computer algorithm. MPEP § 2106.05(f).
Step 2B: The claim does not contain significantly more than the judicial exception. The claim further recites that “each primary memory component has a characteristic subject to a time drift”. However, as above, this is a mere instruction to apply the judicial exception using a generic computer programmed with generic classes of computer algorithm. MPEP § 2106.05(f).
Claim 3
Step 1: A process, as above.
Step 2A Prong 1: The claim recites the same judicial exceptions as in claim 1.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. The claim further recites that “the characteristic subject to the time drift is a conductance”. However, as above, this is a mere instruction to apply the judicial exception using a generic computer programmed with generic classes of computer algorithm. MPEP § 2106.05(f).
Step 2B: The claim does not contain significantly more than the judicial exception. The claim further recites that “the characteristic subject to the time drift is a conductance”. However, as above, this is a mere instruction to apply the judicial exception using a generic computer programmed with generic classes of computer algorithm. MPEP § 2106.05(f).
Claim 4
Step 1: A process, as above.
Step 2A Prong 1: The claim recites the same judicial exceptions as in claim 1.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. The claim further recites that “each binary weight is encoded using two complementary primary memory components connected to a common sense line”. However, as above, this is a mere instruction to apply the judicial exception using a generic computer programmed with generic classes of computer algorithm. MPEP § 2106.05(f).
Step 2B: The claim does not contain significantly more than the judicial exception. The claim further recites that “each binary weight is encoded using two complementary primary memory components connected to a common sense line”. However, as above, this is a mere instruction to apply the judicial exception using a generic computer programmed with generic classes of computer algorithm. MPEP § 2106.05(f).
Claim 5
Step 1: A process, as above.
Step 2A Prong 1: The claim recites the same judicial exceptions as in claim 4.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. The claim further recites that “the characteristic subject to the time drift is a conductance, and each binary weight depends on respective conductance of the two complementary primary memory components”. However, as above, this is a mere instruction to apply the judicial exception using a generic computer programmed with generic classes of computer algorithm. MPEP § 2106.05(f).
Step 2B: The claim does not contain significantly more than the judicial exception. The claim further recites that “the characteristic subject to the time drift is a conductance, and each binary weight depends on respective conductance of the two complementary primary memory components”. However, as above, this is a mere instruction to apply the judicial exception using a generic computer programmed with generic classes of computer algorithm. MPEP § 2106.05(f).
Claim 6
Step 1: A process, as above.
Step 2A Prong 1: The claim (not reproduced here to avoid formatting issues) recites a mathematical equation which could be calculated mentally.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. See claim 5 analysis.
Step 2B: The claim does not contain significantly more than the judicial exception. See claim 5 analysis.
Claim 7
Step 1: A process, as above.
Step 2A Prong 1: The claim recites the same judicial exceptions as in claim 1.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. The claim further recites that “each latent variable is encoded using two complementary secondary memory components connected to a common sense line”. However, as above, this is a mere instruction to apply the judicial exception using a generic computer programmed with generic classes of computer algorithm. MPEP § 2106.05(f).
Step 2B: The claim does not contain significantly more than the judicial exception. The claim further recites that “each latent variable is encoded using two complementary secondary memory components connected to a common sense line”. However, as above, this is a mere instruction to apply the judicial exception using a generic computer programmed with generic classes of computer algorithm. MPEP § 2106.05(f).
Claim 8
Step 1: A process, as above.
Step 2A Prong 1: The claim recites the same judicial exceptions as in claim 7.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. The claim further recites that “the characteristic subject to the time drift is a conductance, and each latent variable depends on respective conductances of the two complementary secondary memory components”. However, as above, this is a mere instruction to apply the judicial exception using a generic computer programmed with generic classes of computer algorithm. MPEP § 2106.05(f).
Step 2B: The claim does not contain significantly more than the judicial exception. The claim further recites that “the characteristic subject to the time drift is a conductance, and each latent variable depends on respective conductances of the two complementary secondary memory components”. However, as above, this is a mere instruction to apply the judicial exception using a generic computer programmed with generic classes of computer algorithm. MPEP § 2106.05(f).
Claim 9
Step 1: A process, as above.
Step 2A Prong 1: The claim (not reproduced here to avoid formatting issues) recites a mathematical equation which could be calculated mentally.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. See claim 8 analysis.
Step 2B: The claim does not contain significantly more than the judicial exception. See claim 8 analysis.
Claim 10
Step 1: A process, as above.
Step 2A Prong 1: The claim recites that “during the weight update, each latent variable is modified depending on the sign of the respective product”. This limitation recites the mathematical concept of modifying variables based on the sign of products.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. See claim 1 analysis.
Step 2B: The claim does not contain significantly more than the judicial exception. See claim 1 analysis.
Claim 11
Step 1: A process, as above.
Step 2A Prong 1: The claim recites that “each latent variable is increased if the respective product is positive, and conversely decreased if said product is negative”. This limitation recites the mathematical concept of altering latent variables based on the sign of products.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. See claim 10 analysis.
Step 2B: The claim does not contain significantly more than the judicial exception. See claim 10 analysis.
Claim 12
Step 1: A process, as above.
Step 2A Prong 1: The claim recites, inter alia, that “during the weight update, each binary weight is updated according to an algorithm including following first and second cases: [algorithm and meaning of relevant variables not reproduced here to avoid formatting issues]”. This algorithm is a series of mathematical calculations that could be executed mentally.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. The claim further recites that “the characteristic subject to the time drift is a conductance, and each binary weight depends on respective conductance of the two complementary primary memory components”. However, this is a mere instruction to apply the judicial exception using generically recited computing equipment. MPEP § 2106.05(f).
Step 2B: The claim does not contain significantly more than the judicial exception. The claim further recites that “the characteristic subject to the time drift is a conductance, and each binary weight depends on respective conductance of the two complementary primary memory components”. However, this is a mere instruction to apply the judicial exception using generically recited computing equipment. MPEP § 2106.05(f).
Claim 13
Step 1: A process, as above.
Step 2A Prong 1: The claim recites that “the algorithm consists of said first and second cases”. The algorithm remains mathematical under this further assumption.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. See claim 12 analysis.
Step 2B: The claim does not contain significantly more than the judicial exception. See claim 12 analysis.
Claim 14
Step 1: A process, as above.
Step 2A Prong 1: The claim recites that the “switch to G(WBLb,ij) > G(WBL,ij) is done by increasing G(WBLb,ij)”. Increasing a value is a mathematical concept and could be performed mentally.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. See claim 12 analysis.
Step 2B: The claim does not contain significantly more than the judicial exception. See claim 12 analysis.
Claim 15
Step 1: A process, as above.
Step 2A Prong 1: The claim recites that “Threshold1 is equal to (G(WBLb,ij) - G(WBL.ij))”. The algorithm remains mathematical under this further assumption.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. See claim 12 analysis.
Step 2B: The claim does not contain significantly more than the judicial exception. See claim 12 analysis.
Claim 16
Step 1: A process, as above.
Step 2A Prong 1: The claim recites that the “switch to G(WBL.ij) > G(WBLb,ij) is done by increasing G(WBL,ij)”. Increasing a value is a mathematical operation that could be performed mentally.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. See claim 12 analysis.
Step 2B: The claim does not contain significantly more than the judicial exception. See claim 12 analysis.
Claim 17
Step 1: A process, as above.
Step 2A Prong 1: The claim recites that “Threshold2 is equal to (G(WBL,ij) - G(WBLb,i)))”. The algorithm remains mathematical under these further assumptions.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. See claim 12 analysis.
Step 2B: The claim does not contain significantly more than the judicial exception. See claim 12 analysis.
Claim 18
Step 1: A process, as above.
Step 2A Prong 1: The claim recites the same judicial exceptions as in claim 1.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. The claim further recites that “increasing the conductance of a respective memory component is obtained by applying a SET pulse to the corresponding phase-change memory device”. However, as above, this is a mere instruction to apply the judicial exception using a generic computer programmed with generic classes of computer algorithm. MPEP § 2106.05(f).
Step 2B: The claim does not contain significantly more than the judicial exception. The claim further recites that “increasing the conductance of a respective memory component is obtained by applying a SET pulse to the corresponding phase-change memory device”. However, as above, this is a mere instruction to apply the judicial exception using a generic computer programmed with generic classes of computer algorithm. MPEP § 2106.05(f).
Claim 19
Step 1: A process, as above.
Step 2A Prong 1: The claim recites the same judicial exceptions as in claim 18.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. The claim further recites that “the SET pulse is a low current pulse with a long duration, and a RESET pulse is a high current pulse with a short duration”. However, as above, this is a mere instruction to apply the judicial exception using a generic computer programmed with generic classes of computer algorithm. MPEP § 2106.05(f).
Step 2B: The claim does not contain significantly more than the judicial exception. This judicial exception is not integrated into a practical application. The claim further recites that “the SET pulse is a low current pulse with a long duration, and a RESET pulse is a high current pulse with a short duration”. However, as above, this is a mere instruction to apply the judicial exception using a generic computer programmed with generic classes of computer algorithm. MPEP § 2106.05(f).
Claim 20
Step 1: The claim recites an electronic circuit; therefore, it is directed to the statutory category of machines.
Step 2A Prong 1: The claim recites the same judicial exceptions as in claim 1.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. The analysis at this step is identical to that of claim 1, except insofar as this claim recites an “electronic circuit comprising a plurality of memory cells” including the primary and secondary memory components. However, this is a mere instruction to apply the judicial exception using a generic computer. MPEP § 2106.05(f).
Step 2B: The claim does not contain significantly more than the judicial exception. The analysis at this step is identical to that of claim 1, except insofar as this claim recites an “electronic circuit comprising a plurality of memory cells” including the primary and secondary memory components. However, this is a mere instruction to apply the judicial exception using a generic computer. MPEP § 2106.05(f).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5, 7-8, 10-11, and 18-23 are rejected under 35 U.S.C. 103 as being unpatentable over Laydevant et al., “Training Dynamical Binary Neural Networks with Equilibrium Propagation,” in arXiv preprint arXiv:2103.08953 (2021) (“Laydevant”) in view of Bunandar et al. (US 20210036783) (“Bunandar”) and further in view of Huang et al., “Hardware Implementation of RRAM Based Binarized Neural Networks,” in 7.8 APL Materials (2019) (“Huang”).
Regarding claim 1, Laydevant discloses a “[m]ethod for training a binarized neural network, the binarized neural network including input neurons for receiving input values, output neurons for delivering output values and intermediate neurons between the input and output neurons, a respective binary weight being associated to each connection between two respective neurons, the method being implemented by an electronic circuit (energy-based neural networks have dynamics governed by a set of weights of the model W, an input x, and a state s of each neuron – Laydevant, sec. 2, first paragraph; Figure 1 shows that the weights in question are binary; sec. 3.2, subsection entitled “Results” indicates that the architecture used includes hidden [intermediate] layers; sec. 1, last paragraph before bullet points indicates that the learning of equilibrium propagation occurs on-chip [i.e., using an electronic circuit]) and comprising:
- a forward pass including calculating an output vector by applying the binarized neural network on an input vector in a forward direction from the input neurons to the output neurons (Laydevant sec. 2, subsection entitled “Binary Neural Networks (BNNs)” indicates that binary weights are used for forward passes; Algorithm 2 discloses producing an output weight matrix W [i.e., a set of weight vectors] using inputs);
- a backward pass including computing an error vector between the calculated output vector and a learning output vector and calculating a new value … by applying the binarized neural network on the error vector in a backward direction from the output neurons to the input neurons (during a second phase, a neuron needs to have its activation function change to compute an error gradient [error vector] locally and transmit it backward [in a backward pass] to upstream layers [result of this transmission is a new value] – Laydevant, sec. 4.2, first paragraph; equilibrium propagation involves backpropagating the prediction error backward in time [i.e., in a backward direction] by calculating the partial derivative of a loss function l that outlines a discrepancy between a steady neuron state s-* [calculated output vector] and a target y [learning output vector] – id. at sec. 2, subsections entitled “Energy-based models” and “Equilibrium propagation (EP)”); and
- a weight update (Laydevant Algorithm 2 is for updating weight vectors W) including, for each binary weight:
+ computing a product (Laydevant Algorithm 1, which is part of Algorithm 2, involves multiplying a momentum m by (1 – gamma), where gamma is an adaptivity rate) …;
+ modifying a latent variable depending on the product (Laydevant Algorithm 1 modifies momentum m [latent variable] based on the above product); and
+ updating the respective binary weight as a function of the latent variable with respect to a threshold (Laydevant Algorithm 1 flips the sign of each weight Wi [i.e., updates the weight]by comparing the absolute value of each momentum entry mi [latent variable] with a decision threshold tau [threshold] and flipping the weight if the magnitude of the momentum is greater than the threshold and the sign of the momentum equals that of the weight);
each binary weight being encoded using at least one primary memory component (binary optimizer without latent weights (BOP) [i.e., Algorithm 1] is of interest to reduce the memory footprint of BNN training – Laydevant, sec. 2, penultimate subsection, first paragraph; note that Algorithm 1 updates the weights, which suggests that they must be stored in a memory component);
each latent variable being encoded using at least one secondary memory component (binary optimizer without latent weights (BOP) [i.e., Algorithm 1] is of interest to reduce the memory footprint of BNN training – Laydevant, sec. 2, penultimate subsection, first paragraph; note that Algorithm 1 updates the momentum [latent variable], which suggests that it must be stored in a memory component different from that used to store the weights), each secondary memory component having a characteristic subject to a time drift (discrete-time update of the momentum can be written into a continuous-time update rule that reads as the differential equation describing the evolution [time drift] of the voltage of a capacitor; capacitors [secondary memory components] can thus be used to store the inertia – Laydevant, last paragraph before sec. 4) ….”
Laydevant appears not to disclose explicitly the further limitations of the claim. However, Bunandar discloses “a new value of the input vector (memory may store executable instructions that cause a processor to determine new input values – Bunandar, paragraph 39); … [and]
multiplying a respective element of the error vector with a respective element of the new value of the input vector (chain rule may be used to compute the gradient of the loss function with respect to the parameters; derivative of the error with respect to the weights is defined as an outer product between the error vector and the input vectors – Bunandar, paragraph 88 [note that the input vectors in question may be the new vectors]) ….”
Bunandar and the instant application both relate to neural networks and are analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Laydevant to compute a product of the error vector and the input vector, as disclosed by Bunandar, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would increase the accuracy of the resulting network by allowing it to be trained efficiently. See Bunandar, paragraphs 87-88.
Neither Laydevant nor Bunandar appears to disclose explicitly the further limitations of the claim. However, Huang discloses that “each one of the primary and secondary memory components [is] a phase-change memory device (nonvolatile memory used for neural networks includes phase change memory (PCM) – Huang, p. 1, second paragraph).”
Huang and the instant application both relate to neural networks and are analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Laydevant and Bunandar to employ a phase-change memory device, as disclosed by Huang, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would save memory space by allowing multiple bits to be stored in a single cell. See Huang, p. 1, second paragraph.
Regarding claim 2, Laydevant, as modified by Bunandar and Huang, discloses that “each primary memory component has a characteristic subject to a time drift (Huang Fig. 1 and third full paragraph of p. 2 disclose that paired RRAM devices P and D [memory components] may have conductance changes over time [characteristic subject to a time drift]).” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Laydevant and Bunandar to employ time-changing characteristics in the primary memory components, as disclosed by Huang, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would allow the memory to be easily updated with time-changing data. See Huang, third full paragraph of p. 2.
Regarding claim 3, Laydevant, as modified by Bunandar and Huang, discloses that “the characteristic subject to the time drift is a conductance (discrete-time update of the momentum can be written into a continuous-time update rule that reads as the differential equation describing the evolution [time drift] of the voltage of a capacitor; capacitors can thus be used to store the inertia – Laydevant, last paragraph before sec. 4 [note that conductance is the inverse of resistance; thus, by Ohm’s law, given a constant current, a time-varying voltage will result in a time-varying conductance]).”
Regarding claim 4, Laydevant, as modified by Bunandar and Huang, discloses that “each binary weight is encoded using two complementary primary memory components connected to a common sense line (bit line is connected to presynaptic neurons and the sense line [common sense line] is connected to postsynaptic neurons via a comparator; the comparator is used to detect the sign of the synaptic weight [i.e., the comparator encodes the weight] – Huang, paragraph spanning pp. 3-4; see also Fig. 3(a) (depicting transistors and RRAM components [primary memory components] along the sense lines)).” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Laydevant and Bunandar to encode the weight using memory components connected via a sense line, as disclosed by Huang, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would provide a highly parallel and energy-efficient hardware implementation of the networks. See Huang, p. 1, second paragraph.
Regarding claim 5, the rejection of claim 4 is incorporated. Laydevant further discloses that “the characteristic subject to the time drift is a conductance (discrete-time update of the momentum can be written into a continuous-time update rule that reads as the differential equation describing the evolution [time drift] of the voltage of a capacitor; capacitors can thus be used to store the inertia – Laydevant, last paragraph before sec. 4 [note that conductance is the inverse of resistance; thus, by Ohm’s law, given a constant current, a time-varying voltage will result in a time-varying conductance]) ….”
Neither Laydevant nor Bunandar appears to disclose explicitly the further limitations of the claim. However, Huang discloses that “each binary weight depends on respective conductance of the two complementary primary memory components (Huang Eqs. (1)-(5) and accompanying text collectively show that sign of the sum of the binary weight gradients depends on the difference between the conductances of paired RRAM devices P and D).” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Laydevant and Bunandar to modify the weights based on conductances of memory components, as disclosed by Huang, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would allow the relevant quantities to be encoded using simple physical circuits, thereby reducing memory footprint. See Huang, p. 2, third full paragraph.
Regarding claim 7, Laydevant, as modified by Bunandar and Huang, discloses that “each latent variable is encoded using two complementary secondary memory components connected to a common sense line (bit line is connected to presynaptic neurons and the sense line [common sense line] is connected to postsynaptic neurons via a comparator; the comparator is used to detect the sign of the synaptic weight – Huang, paragraph spanning pp. 3-4; see also Fig. 3(a) (depicting transistors and RRAM components [primary memory components] along the sense lines), Eqs. (1)-(5) and accompanying text (disclosing that the weight gradient [latent variable] is encoded using the difference between the conductances of complementary memory components P and D)).” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Laydevant and Bunandar to encode the latent variables with complementary memory components connected to a common sense line, as disclosed by Huang, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would provide a highly parallel and energy-efficient hardware implementation of the networks. See Huang, p. 1, second paragraph.
Regarding claim 8, the rejection of claim 7 is incorporated. Laydevant further discloses that “the characteristic subject to the time drift is a conductance (discrete-time update of the momentum can be written into a continuous-time update rule that reads as the differential equation describing the evolution [time drift] of the voltage of a capacitor; capacitors can thus be used to store the inertia – Laydevant, last paragraph before sec. 4 [note that conductance is the inverse of resistance; thus, by Ohm’s law, given a constant current, a time-varying voltage will result in a time-varying conductance]) ….”
Neither Laydevant nor Bunandar appears to disclose explicitly the further limitations of the claim. However, Huang discloses that “each latent variable depends on respective conductances of the two complementary secondary memory components (Huang Eqs. (1)-(5) and accompanying text collectively show that sign of the sum of the binary weight gradients [each weight gradient = latent variable] depends on the difference between the conductances of paired RRAM devices P and D).” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Laydevant and Bunandar modify the latent variables based on conductances of memory components, as disclosed by Huang, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would allow the relevant quantities to be encoded using simple physical circuits, thereby reducing memory footprint. See Huang, p. 2, third full paragraph.
Regarding claim 10, Laydevant, as modified by Bunandar and Huang, discloses that “during the weight update, each latent variable is modified depending on the sign of the respective product (Laydevant Algorithm 1 shows that the momentum m is updated based on a sum of a product of m and (1 – gamma) and a product of a gradient g and gamma, so that m is increased if this first product is positive and decreased if it is negative).”
Regarding claim 11, Laydevant, as modified by Bunandar and Huang, discloses that “each latent variable is increased if the respective product is positive, and conversely decreased if said product is negative (Laydevant Algorithm 1 shows that the momentum m is updated based on a sum of a product of m and (1 – gamma) and a product of a gradient g and gamma, so that m is increased if this first product is positive and decreased if it is negative).”
Regarding claim 18, Laydevant, as modified by Bunandar and Huang, discloses that “increasing the conductance of a respective memory component is obtained by applying a SET pulse to the corresponding phase-change memory device (SET pulse is applied on device P to increase its conductance – Huang, p. 2, last paragraph on left-hand column; device may be a phase-change memory – id. at p. 1, second paragraph).” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Laydevant and Bunandar to apply a SET pulse to increase conductance, as disclosed by Huang, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would provide a simple hardware implementation to adjust the relevant parameters of the network. See Huang, paragraph spanning pp. 2-3.
Regarding claim 19, Laydevant, as modified by Bunandar and Huang, discloses that “the SET pulse is a low current pulse with a long duration, and a RESET pulse is a high current pulse with a short duration (conductance may be modulated using a SET or a RESET pulse – Huang, paragraph spanning pp. 2-3 [note that the use of the word “pulse” implies the application of a given current for a given duration]).” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed inven