DETAILED ACTION
This office action addresses Applicant’s response filed on 9 March 2026. Claims 1, 3-8, 10-15, and 17-20 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over BISTLock (“BISTLock: Using BIST for IP Piracy Protection via Input Isolation with Near-Zero Overhead”) in view of Pouya (US 2002/0184582)
Regarding claim 1, BISTLock discloses a method comprising: applying a logic locking finite-state machine component to an integrated circuit, wherein the logic locking finite-state machine component is inserted in a test-enable logic path (p. 3, description of Fig. 3, finite-state machine (FSM) added to test controller);
receiving, at the logic locking finite-state machine component, an N-bit key for activating operations of the integrated circuit (p. 4, description of Fig. 4, 128-bit key);
generating, at the logic locking finite-state machine component, a 1-bit lock signal sequence based on the N-bit key; outputting, at the logic locking finite-state machine component, the 1-bit lock signal sequence to the integrated circuit (p. 3, description of Fig. 3 and p. 4, Fig. 3; MUX select bit output based on 128-bit key); and
activating a test mode based on an incorrect key being given to the logic locking finite-state machine component (p. 2, BIST logic remains in test mode with incorrect key; p. 3, Fig. 1, test mode PRPG inputs; description of Fig. 3, locked FSM forces selection of PRPG).
BISTLock does not appear to explicitly disclose that the test-enable logic path is specifically a scan-enable logic path, and that scan inputs are selected in the scan mode. Pouya discloses these limitations (Fig. 2; ¶¶23, 28). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of BISTLock and Pouya, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of locking scan chains. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. BISTLock discloses a logic-locking component inserted on a test-enable path that forces selection of test inputs. Pouya teaches that the test-enable path is specifically a scan-enable path, and that the forced selection of test inputs is specifically of scan inputs. The teachings of Pouya are directly applicable to BISTLock in the same way, so that BISTLock would similarly use the logic-locking component to lock scan chains.
Regarding claim 3, BISTLock discloses placing the integrated circuit into a non-functional mode upon the receiving the incorrect key, wherein the operations are prevented from executing in the integrated circuit (p. 2, BIST logic remains in test mode with incorrect key).
Claim(s) 4-6, 8, 10-13, 15, and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over BISTLock in view of Pouya and Abdelmoneum (US 2022/0200655).
Regarding claim 4, BISTLock does not appear to explicitly disclose modifying a clock gating enable signal to include a secret key as the correct key. Abdelmoneum discloses these limitations (¶¶23, 30). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of BISTLock, Pouya, and Abdelmoneum, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of locking clocked circuit elements. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. BISTLock discloses an FSM for logic locking based on a key. Abdelmoneum teaches that logic-locking FSM is used to enable/disable clocked circuit elements through clock gating. The teachings of Abdelmoneum are directly applicable to BISTLock in the same way, so that BISTLock’s FSM would similarly enable/disable clocked circuit elements based on the key.
Regarding claim 5, BISTLock does not appear to explicitly disclose propagating a clock signal to sequencing elements upon sending a correct key. Abdelmoneum discloses these limitations (Abstract, ¶23). Motivation to combine remains consistent with claim 4.
Regarding claim 6, BISTLock does not appear to explicitly disclose gating a clock signal to disable sequencing elements from capturing a new logic value by one or more based upon the incorrect key. Abdelmoneum discloses these limitations (Abstract, ¶¶23, 28, 31). Motivation to combine remains consistent with claim 4.
Claims 8 and 10-13 are directed to systems comprising computers and executable instructions for performing the methods of claims 1 and 3-6, and are rejected under similar reasoning. BISTLock does not appear to explicitly disclose systems comprising computers and executable instructions for performing the claimed methods. Abdelmoneum discloses such systems for performing the claimed methods (¶59). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of BISTLock, Pouya, and Abdelmoneum, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of computer-aided design of circuits. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. BISTLock discloses integrating a logic-locking FSM into a circuit design. Persons having ordinary skill in the art would understand that modifying circuit designs could be done with computers, as taught by Abdelmoneum. The teachings of Abdelmoneum are directly applicable to BISTLock in the same way, so that BISTLock would similarly use computers to integrate the FSM into a circuit design more efficiently.
Claims 15 and 17-19 are directed to computer program products comprising computer-readable storage media having program instructions for performing the methods of claims 1 and 3-6, and are rejected under similar reasoning. BISTLock does not appear to explicitly disclose computer program products having program instructions for performing the claimed methods; Abdelmoneum discloses these limitations (¶59). Motivation to combine remains consistent with claim 8.
Claim(s) 7, 8, 14, 15, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over BISTLock in view of Pouya and Bhunia (US 2021/0192018).
Regarding claim 7, BISTLock discloses applying a logic locking FSM component or a logic locking with RTL gating to a current design (p. 3, description of Fig. 2 insertion of key logic), but does not appear to explicitly disclose that the application is at a gate level, at a register-transfer logic level, or on an abstraction level. Bhunia discloses that the application is at a gate level, at a register-transfer logic level, or on an abstraction level (¶¶44, 115). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of BISTLock, Pouya, and Bhunia, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of flexibly protecting hardware designs from unauthorized analysis and access at different stages of the design process. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. BISTLock discloses applying logic locking to circuit designs. Bhunia teaches that circuits are designed and provided at various levels of abstraction such as RTL or gate level, and automatically applying logic locking to designs at those abstraction levels. The teachings of Bhunia are directly applicable to BISTLock in the same way, so that BISTLock would similarly apply logic locking to designs at various levels of abstraction, to flexibly integrate design protections at different stages of the design process.
Claims 8 and 14 are directed to systems comprising computers and executable instructions for performing the methods of claims 1 and 7, and are rejected under similar reasoning. BISTLock does not appear to explicitly disclose systems comprising computers and executable instructions for performing the claimed methods. Bhunia discloses such systems for performing the claimed methods (¶¶138-139). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of BISTLock, Pouya, and Bhunia, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of computer-aided design of circuits. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. BISTLock discloses integrating a logic-locking FSM into a circuit design. Persons having ordinary skill in the art would understand that modifying circuit designs could be done with computers, as taught by Bhunia. The teachings of Bhunia are directly applicable to BISTLock in the same way, so that BISTLock would similarly use computers to integrate the FSM into a circuit design more efficiently.
Claims 15 and 20 are directed to computer program products comprising computer-readable storage media having program instructions for performing the methods of claims 1 and 7, and are rejected under similar reasoning. BISTLock does not appear to explicitly disclose computer program products having program instructions for performing the claimed methods; Bhunia discloses these limitations (¶¶138-139). Motivation to combine remains consistent with claims 7 and 8.
Response to Arguments
Applicant’s arguments have been considered but are moot in view of the new grounds of rejection. Applicant asserts that the prior art fails to teach newly-added limitations, which are addressed above using newly-cited prior art.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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21 March 2026
/ARIC LIN/ Examiner, Art Unit 2851
/JACK CHIANG/ Supervisory Patent Examiner, Art Unit 2851