DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, filed 2/11/2022, with respect to the rejection(s) of the independent claim(s) under the combination of prior arts have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Davey (US pg. no. 20200280508).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huilgol (US pg. no. 20220091872), further in view of Khan (US pg. no. 20220407775), further in view of Davey (US pg. no. 20200280508).
Regarding claim 1. Huilgol discloses an apparatus (fig. 1 discloses network appliance 101. The device comprising 101 (NIC) corresponds to apparatus) comprising:
a packet processing device ( [0042] discloses a network appliance 101 (packet processing device), can have a control plane 102 and a data plane 103. The control plane provides forwarding information (e.g., in the form of table management information) to the data plane and the data plane receives packets on input interfaces, processes the received packets, and then forwards packets to desired output interfaces) comprising:
circuitry to perform packet processing operations on the packet device according to a configuration (fig. 1, data plane and its components; [0042] the data plane receives packets on input interfaces, processes the received packets, and then forwards packets to desired output interfaces) and circuitry to execute control plane software (fig. 1 discloses control plane and its components with software executing in it that corresponds to circuit to execute control plane software and the software executed respectively) to provide the configuration (fig. 1 P4 table management information P4 programming sent to the data plane to program the data plane corresponds to configuration; [0046] discloses a P4 program (configuration) is provided to the data plane via the control plane 102. Communications between the control plane and the data plane can use a dedicated channel or bus, can use shared memory, etc. The P4 program includes software code that configures the functionality of the data plane 103 to implement particular processing and/or forwarding logic and to implement processing and/or forwarding tables that are populated and managed via P4 table management information that is provided to the data plane from the control plane) to the circuitry to perform packet processing operations according to the configuration ([0042] discloses a network appliance 101, such as a NIC, can have a control plane 102 (circuitry to execute control plane software to provide the configuration) and a data plane 103. The control plane provides forwarding information (e.g., in the form of table management information (configuration)) to the data plane and the data plane receives packets on input interfaces, processes the received packets, and then forwards packets to desired output interfaces).
But, Huilgol does not explicitly disclose: wherein the circuitry to perform packet processing operations on the packet processing device according to the configuration is to continue operation independent of change of operation of the circuitry to execute the control plane software.
However, in the same field of endeavor, Khan inherently disclose discloses wherein the circuitry to perform packet processing operations on the packet processing device according to the configuration is to continue operation independent of change of operation of the circuitry to execute the control plane software ([0059] discloses when the active control-plane crashes (circuitry to execute control plane software unavailable), then the standby control-plane of the other device is configured to switch over without manual intervention and takes over operation of the data plane (circuitry to perform packet processing operations ) of the physical network device. The switchover is performed without any interruption to the system operation; [0064] In the stack 103, the target network device 104 is initially put in an active mode while the debug network device 102 is put in standby mode. In the active mode, the control plane 110 (circuitry to execute control plane software) of the target network device 104 services the data plane 114 of (circuitry to perform packet processing operations) the target network device 104. Once both target network device 104 and debug network device 102 are synchronized in states, a switchover operation is triggered to put the control plane 108 of the debug network device 102 in active mode, and it then takes over the role of servicing the data plane 114 of the target network device 104. Notably, following the switchover operation, the data plane 114 maintains operation throughout the debugging or profiling session—thus, there is no change in the network from the switchover operation from the perspective of the network and peer network devices. While in this active state, the debug network device 102 (e.g., via instrumented control plane, hardware instrumentations, or both) provides instrumentation operation to debug or profile the control plane operation, the data plane operation, and the network operation of the stack and its subcomponents; [0059] In yet another aspect, the exemplary system and method is configured to provide protection against system failures during live debug session of a target node. In such embodiment, when the active control-plane crashes, then the standby control-plane of the other device is configured to switch over without manual intervention and takes over operation of the data plane of the physical network device. The switchover is performed without any interruption to the system operation).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time of the invention was effectively filed to combine the teaching of Huilgol with Khan. The modification would allow high availability of system when one component such as an active control plane is upgrading or failed.
But, the combination does not explcltly disclose discloses wherein the circuitry to perform packet processing operations and the circuitry to execute the control plane software are on the same device (fig. 2 discloses control planes 210 and 230 are on the same device 200 with the data plane 230; ([0030-0031] discloses the high availability router 200 comprises a primary control plane part 210, a secondary control plane part 220 and a data plane part 230. The control plane parts 210, 220 may include two similar data plane software modules, arranged in an active/standby high availability configuration, executing on two different hardware elements, for example two separate application specific integrated circuits (ASICs). The data plane part may include two similar data plane software modules, arranged in an active/active high availability configuration, each installed on a respective one of the two different hardware elements, such that each respective control plane software module is installed on the same hardware element as one of the data plane software modules. [0031] The data plane part comprises a plurality of network interfaces 231, 232, 233. Each of the first, second and third routers has a respective link 150 to the high availability router).
wherein the circuitry to perform packet processing operations on the packet processing device according to the configuration is to continue operation independent of change of operation of the circuitry to execute the control plane software (fig. 7 and [0040] In normal operation the primary control plane part 210 is active within the high availability router is active and the secondary control plane part 220 is on standby. In use, data packets from the first router 310 to the second router 320 will be routed via the new link which connects network interface 312 to network interface 322. Data packets from the first router 310 to the third router 330 are likely to be routed via the high availability router, as this route involves only two hops and is likely to have a lower cost than the route via the second router, the high availability router and then the third router. Traffic between the second router and the third router is likely to be routed via the high availability router for similar reasons. [0041] Consider the situation where the primary control plane part of the high availability router and a portion of the data plane part fails. FIG. 5 shows a schematic depiction of the network 110 in such a scenario. The secondary control plane part 220 of the high availability router is now active. The forwarding plane still functional connecting 200 with 320 is operational with the secondary control plane).
Therefore, it would have been obvious to a person having ordinary skill in eth art et the time of the invention was effectively filed to combine the teaching of the combination with Davey. The modification would allow high availability of control plane to continue communication when active control plane fail by falling back a redundant control plane. The modification would allow continuation of communication.
Regarding claim 2. The combination discloses apparatus of claim 1.
Huilgol, wherein the configuration comprises one or more match-action entries that specify packet processing and packet forwarding operations ([0046-0047] discloses a P4 program (configuration) is provided to the data plane via the control plane 102... The P4 program includes software code that configures the functionality of the data plane 103 to implement particular processing and/or forwarding logic and to implement processing and/or forwarding tables that are populated and managed via P4 table management information that is provided to the data plane from the control plane…[0047] The data plane 103 includes a programmable packet processing pipeline 104 that is programmable using a domain-specific language such as P4 and that can be used to implement the programmable packet processing pipeline 104. As described in the P4 specification, a programmable packet processing pipeline can include an arbiter 105, a parser 106, a match-action pipeline 107, a deparser 108, and a demux/queue 109. The data plane elements described may be implemented as a P4 programmable switch architecture, as a P4 programmable NIC).
Regarding claim 3. The apparatus of claim 1.
Khan discloses, wherein the packet processing device comprises circuitry to configure connectivity between a host and the circuitry to perform packet processing operations (fig. 1 discloses the target network device 104 (packet processing device) comprises CPI/DPI transport (circuitry to configure connectivity ) to enable communication with CPI/DPI of the debug network device 102 (host); [0113] The instrumented control plane 108 (control plane of host) of the debug network device 102 (host) makes control-plane updates received at the data plane 114 (the circuitry to perform packet processing operations ) of the target network device 104 using the control-plane-data-plane transport modules 120, 122 (circuitry to configure connectivity between a host and the circuitry to perform packet processing operations). Data plane updates determined at the instrumented control plane 108 are also pushed to the data plane 114 of the target network device 104 using the control-plane-data-plane interface transport modules 120, 122 ( circuitry to configure connectivity between a host and the circuitry to perform packet processing operations)), wherein:
based on unavailability of the circuitry to execute control plane software, the circuitry to configure connectivity between a host and the circuitry to perform packet processing operations is to apply a second configuration to maintain connectivity between the host and the circuitry to perform packet processing operations ([0064] In the stack 103, the target network device 104 is initially put in an active mode while the debug network device 102 is put in standby mode. In the active mode, the control plane 110 (the circuitry to execute control plane software) of the target network device 104 services the data plane 114 (circuitry to perform packet processing operations) of the target network device 104. Once both target network device 104 and debug network device 102 are synchronized in states, a switchover operation (second configuration) is triggered to put the control plane 108 of the debug network device 102 in active mode (control plane 110 (the circuitry to execute control plane software) is in standby mode that corresponds to unavailability of the circuitry to execute control plane software), and it then takes over (corresponds to configuring connectivity between the host (102) and the data plane 114 that corresponds to circuitry to perform packet processing operations) the role of servicing the data plane 114 of the target network device 104. Notably, following the switchover operation (configuring connectivity), the data plane 114 maintains operation throughout the debugging or profiling session—thus, there is no change in the network from the switchover operation from the perspective of the network and peer network devices…[0065] For the control plane 108 of the debug network device 102 (host) to service the data plane 114 of the target network device 104, a virtual transport layer may be implemented, e.g., by a control-plane data-plane interface transport module (also referred to herein as a “virtual PCI” or “VPCI module” and shown in FIG. 1 as a “control plane interface/data plane interface transport” (CPI/DPI Transport) 120 and 122 that corresponds to circuitry to configure connectivity between a host and the circuitry to perform packet processing operations).
Regarding claim 4. The combination discloses apparatus of claim 3.
Khan discloses, wherein the second configuration comprises one or more of: access to data queues, or access to direct memory access (DMA) circuitry ([0124] discloses the data-plane-control-plane transport modules 120, 122 (circuit) implements a logical data-plane interface that (i) provides, or can interface to, the device access layer and (ii) provides communication between the data-plane drivers running on the instrumented control plane 108 of the debug network device 102 and the data-plane 110 of the target network device 104. the control plane 108 of the debug network device 102 can view and access the entire memory map (access to data queues or DMA) of the data-plane device (e.g., 114). The data-plane-control-plane transport modules 120, 122 may implement a tunnel ... The data-plane-control-plane transport modules 120, 122 may encapsulate a given bus transactions to send through a given tunnel. Raw register/memory access operations are then sent and received over the data-plane-control-plane transport modules 120, 122).
Regarding claim 5. The apparatus of claim 3.
Khan discloses, wherein based on unavailability of the circuitry to execute control plane software, the circuitry to configure connectivity between a host system and the circuitry to perform packet processing operations is to configure packet processing operations of the circuitry to perform packet processing operations ([0151] Once the control-plane states are synchronized to the same states, the debug controller triggers (917) a switchover (SSO) operation , and the debug switch “S2” 102a is directed to assume the active role while the target switch “S1” 104a assumes the standby role. Once in the active role, the debug switch “S2” 102a runs (922) as the control plane for the target switch “S1” 104a using the logical data-plane interface (e.g., vPCI), which may be initiated at this sequence or earlier as discussed herein. The control plane 108 of the debug switch “S2” 102a uses the logical data-plane interface to perform data-plane updates (923) (to configure packet processing operations) to the data plane 114 of the target switch “S1” 104a (shown as “Virtual Transport: DP updates” 923).).
Regarding claim 6. The combination discloses apparatus of claim 3.
Khan discloses, wherein the unavailability of the circuitry to execute control plane software comprises change of one or more of: control plane application([0051 wherein the first control plane of the target network device is initially executing in an active stacked configuration, and wherein the second control plane of the debug network device is initially executing in a standby stacked configuration; and trigger a switchover operation such as in-service software upgrade (ISSU) (upgraded software corresponds to control plane application) operations wherein the first control plane of the target network device is switched from the active stacked configuration to the standby stacked configuration and disconnected from updating the data plane of the target network device, and wherein the second control plane of the debug network device is switched from the standby stacked configuration to the active stacked configuration and connected, over a network connection, to update the data plane of the target network device, wherein the one or more debugging processes is operatively executed concurrently with the second control plane of the debug network device to evaluate at least one of: i) said second control plane (reflecting the first control plane), ii) a hardware or firmware configuration of the target network device, and iii) the network; [0160] discloses stacking, SSO and CNF (Cache & Flush) operations are used in conjunction with fast software upgrade (FSU/xFSU) operation (software upgraded corresponds to control plane software) to reduce outage for non-redundant systems. The exemplary system and method may employ these operations... Once a debug network device is created on-demand, it may form a stack with physical target network device. SSO operation as described herein may be used to synchronize the states of the target network device to the debug network device. At this point, a switchover is performed, and the instrumented control plane of the debug network device is set to active mode (the control plane that was active is turned to standby (is unavailable)). Subsequent control traffic intended for the control plane of the target network device can be redirected (not mirrored) to the debug network device).
Regarding claim 7. The combination discloses apparatus of claim 1.
Huilgol discloses, wherein the circuitry to perform packet processing operations comprises one or more of:
a parser (fig. 1 data plane 103 comprises parser 106), or exact match-action circuitry (fig. 1 data plane 103 comprises match action pipeline 107; [0047] The data plane 103 includes a programmable packet processing pipeline 104 that is programmable using a domain-specific language such as P4 and that can be used to implement the programmable packet processing pipeline 104. As described in the P4 specification, a programmable packet processing pipeline can include an arbiter 105, a parser 106, a match-action pipeline 107, a de-parser 108, and a demux/queue 109).
Regarding claim 8. The combination discloses apparatus of claim 1.
Huilgol discloses, wherein the packet processing device comprises one or more of: a network interface controller (NIC) ([0047] The data plane 103 includes a programmable packet processing pipeline 104 that is programmable using a domain-specific language such as P4 and that can be used to implement the programmable packet processing pipeline 104. As described in the P4 specification, a programmable packet processing pipeline can include an arbiter 105, a parser 106, a match-action pipeline 107, a de-parser 108, and a demux/queue 109. The data plane elements described may be implemented as a P4 programmable switch architecture, as a P4 programmable NIC);
Regarding claim 9. The combination discloses apparatus of claim 1.
Huilgol discloses, comprising a host (fig. 4 host system 400) , wherein the host comprises one or more processors to execute a process to provide the configuration to the circuitry to execute control plane software (fig. 4 discloses CPU cores 407. Examiner notes that to provide the configuration to the circuitry to execute control plane software is an intended use where an intended use is not given patentable weight).
Regarding claim 10. Huilgol discloses at least one non-transitory computer-readable medium comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to:
configure a first processor to execute a control plane to configure a packet processing circuitry with a configuration ([0042] discloses a network appliance 101 (packet processing device), can have a control plane 102 (first processor) and a data plane 103 (packet processing circuitry). The control plane provides forwarding information (e.g., in the form of table management information that corresponds to configure a packet proces) to the data plane and the data plane receives packets on input interfaces, processes the received packets, and then forwards packets to desired output interfaces; [0047] discloses The control plane is often referred to as a CPU (central processing unit) although, in practice, control planes often include multiple CPU cores and other elements; fig. 1 discloses control plane (CPU) providing P4 programming to data plane to configure data processing by the programmable data plane).
But, Huilgol does not explicitly disclose: wherein the packet processing circuitry is to continue operation independent of operation of the first processor to execute a control plane.
However, in the same field of endeavor, Khan discloses , wherein the packet processing circuitry is to continue operation independent of change of operation of the first processor to execute a control plane (([0059] discloses when the active control-plane crashes (circuitry to execute control plane software unavailable), then the standby control-plane of the other device is configured to switch over without manual intervention and takes over operation of the data plane (circuitry to perform packet processing operations ) of the physical network device. The switchover is performed without any interruption to the system operation; [0064] In the stack 103, the target network device 104 is initially put in an active mode while the debug network device 102 is put in standby mode. In the active mode, the control plane 110 (circuitry to execute control plane software) of the target network device 104 services the data plane 114 of (circuitry to perform packet processing operations) the target network device 104. Once both target network device 104 and debug network device 102 are synchronized in states, a switchover operation is triggered to put the control plane 108 of the debug network device 102 in active mode, and it then takes over the role of servicing the data plane 114 of the target network device 104. Notably, following the switchover operation, the data plane 114 maintains operation throughout the debugging or profiling session—thus, there is no change in the network from the switchover operation from the perspective of the network and peer network devices. While in this active state, the debug network device 102 (e.g., via instrumented control plane, hardware instrumentations, or both) provides instrumentation operation to debug or profile the control plane operation, the data plane operation, and the network operation of the stack and its subcomponents; [0059] In yet another aspect, the exemplary system and method is configured to provide protection against system failures during live debug session of a target node. In such embodiment, when the active control-plane crashes, then the standby control-plane of the other device is configured to switch over without manual intervention and takes over operation of the data plane of the physical network device. The switchover is performed without any interruption to the system operation).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time of the invention was effectively filed to combine the teaching of Huilgol with Khan. The modification would allow high availability of system when one component such as an active control plane is upgrading or failed.
The combination does not explicitly disclose: a packet processing device includes both the packet processing circuitry and the first processor to execute a control plane.
However, in the same field of endeavor, Davey discloses a packet processing device includes both the packet processing circuitry and the first processor to execute a control plane( fig. 7 discloses the device 200 comprises control planes 20-22 and data plane 230 (the packet processing circuitry)).
Therefore, it would have been obvious to a person having ordinary skill in eth art et the time of the invention was effectively filed to combine the teaching of the combination with Davey. The modification would allow high availability of control plane to continue communication when active control plane fail by falling back a redundant control plane. The modification would allow continuation of communication.
Regarding claim 11. The combination discloses non-transitory computer-readable medium of claim 10.
Huilgol discloses, wherein the configuration comprises one or more match-action entries and the one or more match-action entries specifies packet processing and packet forwarding operations ([0046-0047] discloses a P4 program (configuration) is provided to the data plane via the control plane 102... The P4 program includes software code that configures the functionality of the data plane 103 to implement particular processing and/or forwarding logic and to implement processing and/or forwarding tables that are populated and managed via P4 table management information that is provided to the data plane from the control plane…[0047] The data plane 103 includes a programmable packet processing pipeline 104 that is programmable using a domain-specific language such as P4 and that can be used to implement the programmable packet processing pipeline 104. As described in the P4 specification, a programmable packet processing pipeline can include an arbiter 105, a parser 106, a match-action pipeline 107, a deparser 108, and a demux/queue 109. The data plane elements described may be implemented as a P4 programmable switch architecture, as a P4 programmable NIC).
Regarding claim 12. The combination discloses non-transitory computer-readable medium of claim 10.
Khan discloses, comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to: configure a second processor to configure connectivity between a host and the packet processing circuitry according to a second configuration, wherein based on unavailability of the first processor, the packet processing circuitry is to maintain connectivity with the host system based on the second configuration ([0064] In the stack 103, the target network device 104 is initially put in an active mode while the debug network device 102 is put in standby mode. In the active mode, the control plane 110 (first processor) of the target network device 104 services the data plane 114 (packet processing circuitry) of the target network device 104. Once both target network device 104 and debug network device 102 are synchronized in states, a switchover operation (connectivity configuration) is triggered to put the control plane 108 (second processor) of the debug network device 102 in active mode (control plane 110 (first processor) is in standby mode that corresponds to unavailability of unavailability of the first processor), and it then takes over (corresponds to configuring connectivity between the host (102) and the data plane 114 (packet processing circuitry) the role of servicing the data plane 114 of the target network device 104. Notably, following the switchover operation (configuring connectivity), the data plane 114 maintains operation throughout the debugging or profiling session—thus, there is no change in the network from the switchover operation from the perspective of the network and peer network devices).
Regarding claim 13. The combination discloses non-transitory computer-readable medium of claim 12.
All other limitations of claim 13 are similar with the limitations of claim 4.
Regarding claim 14. The combination discloses non-transitory computer-readable medium of claim 10.
Khan discloses , comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to: based on unavailability of the first processor, configure a second processor to configure packet processing operations of the packet processing circuitry ([0051 wherein the first control plane (first processor) of the target network device is initially executing in an active stacked configuration, and wherein the second control plane (second processor) of the debug network device is initially executing in a standby stacked configuration; and trigger a switchover operation such as in-service software upgrade (ISSU) (upgraded software corresponds to control plane application) operations wherein the first control plane of the target network device is switched from the active stacked configuration to the standby stacked configuration and disconnected from updating the data plane (packet processing circuitry) of the target network device, and wherein the second control plane of the debug network device is switched from the standby stacked configuration to the active stacked configuration and connected, to update the data plane (configuring the packet processing operation of the packet processing circuitry) of the target network device, wherein the one or more debugging processes is operatively executed concurrently with the second control plane of the debug network device).
Regarding claim 15. The combination discloses on-transitory computer-readable medium of claim 10.
All other limitations of claim 15 ae similar with the limitations of claim 7.
Regarding claim 16. The combination discloses non-transitory computer-readable medium of claim 10.
All other limitations of claim 16 are similar with the limitations of claim 8.
Regarding claim 17. The combination discloses a method comprising:
All other limitations of claim 17 are similar with eth limitations of claim 10.
Regarding claim 18. The method of claim 17.
All other limitations of claim 18 are similar with the limitations of claim 2.
Regarding claim 19. The combination discloses method of claim 17.
All other limitations of claim 19 are similar with eth limitations of claim 12.
Regarding claim 20. The combination discloses method of claim 17.
All other limitations of claim 20 are similar with the limitations of claim 15.
Regarding claim 21, The combination discloses apparatus of claim 1.
Davey discloses, wherein the change of operation of the circuitry to execute the control plane software comprises one or more of: other unavailability of the circuitry to execute the control plane software ([0040-0045])
Regarding claim 22, the combination discloses The apparatus of claim 21.
Davey discloses, wherein during unavailability of the circuitry to execute the control plane software, the circuitry to perform packet processing operations according to a configuration is to provide an interface between the circuitry to perform packet processing operations and a host system to permit copying of packets to or from the host system (fig. 7 and [0040-0040] discloses when the active control plane fails, the secondary control plane is active and the data plane connected to device 320 enables copying of packets from device 200 to outside communication to continue).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MESSERET F. GEBRE whose telephone number is (571)272-8272. The examiner can normally be reached 9:00 am-5:30PM.
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/MESSERET F GEBRE/Primary Examiner, Art Unit 2445