DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-10, 12, 14-15 and 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 states, “the second conductor region is electrically coupled with a second conductive material, which is disposed between a third insulating region and the first insulating region, through the gap area” & “wherein a third conductive material layer is disposed on the third insulating region opposite to the first insulating region”. This language does not clearly claim the subject matter described within the specification. As an initial point it appears that the “third conductive material layer” is not a distinct layer but merely a portion of the conductive layer 221 which is also considered “the second conductive material”. Additionally “the third insulating region” and it’s positioning even when using BRI (broadest reasonable interpretation) is not positionally clearly defined in relation to that of the second conductor region, second conductive material and first insulating region. The ambiguous nature of the limitation requires further language and should be supported by that of the specification. No new matter should be included.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 8-10, 12 and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Brigham et al. (US PG. Pub. 2017/0208695).
Regarding claim 8 – Brigham teaches a multi-conductor through hole structure (figs. 1A-2 [title] Brigham states, “Sleeved Coaxial Printed Circuit Board Vias”), comprising: one or more through holes (90 [paragraph 0023] Brigham states, “the via 90 passes through the different materials, such as the laminate material 25, 45 and the dielectric material 35”) disposed in a first insulating region (35); a first conductor region (combination of layers 30, 40 & 70 [paragraph 0033] Brigham states, “electrically connecting the conductive material of the metal sleeve 70 to this interior layer 30, 40”), that corresponds to a ground plated region ([paragraph 0033] Brigham states, “this interior layer 30, 40 may be one or more ground layers”), disposed about a wall of the one or more through holes (see fig. 1A); a second conductor region (60 [paragraph 0024] Brigham states, “signal carried by the conductive path 60”), that corresponds to a power/signal region (discussed above in quoted paragraph 0024), disposed in the one or more through holes (claimed structure shown in figure 1A), wherein an inner wall and an outer wall of the first conductor region (see figure 2) disposed on a surface of the first insulating region are discontinuous at a gap area (fig. 2, 71 [paragraph 0027] Brigham states, “notches 70 are made in the metal sleeve 70 to allow the traces 21, 51 to contact the conductive path 60”), wherein the second conductor region is electrically coupled with a second conductive material (conductive material 21 shown within the gap area 71), which is disposed between a third insulating region (insulation region including layer 25 shown within the gap area 71) and the first insulating region, through the gap area (in an overhead view as shown in figure 2 the second conductive material 21 is shown between the first and third insulating regions), the third insulating region (region of insulation layer 25) being disposed over the first insulating region (35), and wherein a third conductive material layer (extension portion of 21 [paragraph 0035] Brigham states, “signal trace 21”) is disposed on the third insulating region (insulation region including layer 25 shown within the gap area 71) opposite to the first insulating region (35) for providing different types of electrical communication; and a second insulating region (80 [paragraph 0038] Brigham states, “filler material 80 may be an epoxy filler”) disposed between an inside wall of the first conductor region (combination of layers 30, 40 & 70 and a wall of the second conductor region (60).
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Regarding claim 9 – Brigham teaches the multi-conductor through hole structure of claim 8, wherein the first conductor region (figs. 1A-2, combination of layers 30, 40 & 70) and the second conductor region (60) are arranged coaxially ([paragraph 0041] Brigham states, “This serves to create the desired coaxial via, where there is an inner conductor 60, surrounded by an insulating filler material 80, which is, in turn, surrounded by a metal sleeve 70”).
Regarding claim 10 – Brigham teaches the multi-conductor through hole structure of claim 8,wherein the first conductor region (figs. 1A-2, combination of layers 30, 40 & 70) and the second conductor region (160) are formed to be cylindrical ([paragraph 0023] Brigham states, “via 90 is a hollow cylindrical passageway between a plurality of layers”; figures 1A-2 show the first and second conductor regions being “cylindrical”).
Regarding claim 12 – Brigham teaches a substrate comprising: the multi-conductor through hole structure of claim 8; a buildup insulating layer (fig. 1A, 25) disposed over a surface of a core insulating layer (35) that corresponds to the first insulating region (see fig. 1A), the buildup insulating layer (25) corresponding to the third insulating region (structure shown in figure 1A); the first conductor region (combination of layers 30, 70 & 40) further disposed on one or more portions of the surface of the core insulating layer (35) between the buildup insulating layer (25) and the core insulating layer (layer 30 is shown between the buildup insolating layer 25 and core insulting layer 35), one or more third conductor layers (fig. 1B, 21) disposed on the buildup insulating layer (25) opposite the core insulating layer (see fig. 1B), and one or more fourth conductor regions (upper conductor region of 60 passing through buildup insulting layer 25) disposed through the buildup insulating layer (25) between respective ones of one or more third conductor layers (21).
Regarding claim 21 – Brigham teaches the multi-conductor through hole structure of claim 8, wherein the second conductive material layer (fig. 2, conductive material 21 shown within the gap area 71) disposed between the third insulating region (region of insulation layer 25) and the first insulating region (35) is configured to provide electrical communication with the second conductor region (60; figures 1A-2 show the second conductive material layer 21 being in electrical/mechanical connection to second conductor region 60).
Claim(s) 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brigham et al. in view of Gallegos et al. (US PG. Pub. 2013/0105987).
Regarding claim 14 – Brigham teaches a circuit package, comprising: a substrate including one or more multi-conductor through hole structures of claim 8.
Brigham fails to teach an integrated circuit coupled to the substrate, wherein ground, power and signal subcircuits of the integrated circuit are electrically coupled to respective ground plated regions and power/signal regions of respective ones of the one or more multi- conductor through hole structures of the substrate.
Gallegos teaches a circuit package (figs. 1-2), comprising: a substrate (104 [paragraph 0015] Gallegos states, “laminate structure 104”) including one or more multi-conductor through hole structures (fig. 2, 150 [paragraph 0015] Gallegos states, “coaxial via structure 150”); and an integrated circuit (106 [paragraph 0016] Gallegos states, “chip 106”) coupled to the substrate (104), wherein a signal subcircuit (signal subcircuit connected to solder balls 231 & 236) of the integrated circuit (106) is electrically coupled to respective power/signal regions ([paragraph 0015] Gallegos states, “The laminate structure 104 generally comprises one or more power layers, ground plane layers, and wiring interconnects”) of respective ones of the one or more multi-conductor through hole structures (150) of the substrate (104).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit package comprising a substrate with a multi-conductor through hole as taught by Brigham with the integrated circuit with ground and power subcircuits that connected through the multi-conductor through hole of the substrate as taught by Gallegos because Gallegos states regarding this structural arrangement, “A laminate interconnect having a coaxial via structure can be used in any application specific integrated circuit (ASIC) in which it is desirable to reduce loop inductance between power and ground connections, reduce loop inductance between signal and ground connections, and reduce inductive coupling between signal connections. Minimizing inductance and inductive coupling improves signal isolation and reduces cross talk between signal paths” [paragraph 0012].
Regarding claim 15 – Brigham in view of Gallegos teach the circuit package of claim 14, further comprising: a printed circuit board (Gallegos; fig. 1, 102 [paragraph 0013] Gallegos states, “a printed circuit (PC) board 102”) coupled to the substrate (104 [paragraph 0015] Gallegos states, “laminate structure 104”) opposite the integrated circuit (106 [paragraph 0014] Gallegos states, “The chip 106 generally comprises the active circuit elements of the ASIC circuitry”).
Response to Arguments
Applicant’s arguments with respect to claim(s) 8-10, 12, 14-15 and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN T SAWYER whose telephone number is (571)270-5469. The examiner can normally be reached M-F 8:30 am - 5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at 5712722342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVEN T SAWYER/Primary Examiner, Art Unit 2847