Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 1st, 2025 has been received. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendments
Acknowledgment is made of the amendment filed 07/21/2025 (“Amend.”), in which: claims 1, 2, and 10 are amended; no claims are cancelled; new claim 26 is added; and the rejection of the claims are traversed. Claims 1 – 26 are currently pending an Office action on the merits as follows, wherein claims 16 – 25 are withdrawn from consideration due a restriction/election requirement.
Applicant’s arguments with respect to Claims 1 – 26, wherein claims 16 – 25 are withdrawn from consideration due a restriction/election requirement, have been fully considered but are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35
U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 3, 5 – 9, 13 – 15, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Son et al. (US 20210183862 A1), and further in view of Rami et al. (US 20200259018 A1) and Kondo (US 20160247917 A1).
Regarding independent claim 1, Son teaches a semiconductor device, comprising:
an active layer (Fig. 3; semiconductor pattern SP) including a channel (Fig. 3; channel region CH) which is spaced apart from a substrate (Fig. 3; substrate SUB) and extending in a first direction parallel to a surface of the substrate (Fig. 3);
a gate dielectric layer (Fig. 8A; gate insulating layer GI) formed over the active layer (Fig. 8A);
a word line (Fig. 3 ; gate electrode GE (WL)) oriented laterally over the gate dielectric layer to face the active layer (Fig. 3), and …
However, Son remains silent regarding the semiconductor device further comprising:
a word line … including a low work function electrode and a high work function electrode which are arranged parallel to each other in the first direction; and
a dielectric capping layer having a first portion, which extends in a second direction perpendicular to the first direction, disposed between the high work function electrode and the low work function electrode.
However, in the same field of endeavor, Rami discloses a word line (Fig. 2A; gate electrode 112) including a low work function electrode (Fig. 2A; first WF material 112-1) and a high work function electrode (Fig. 2A; second WF material 112-2) which are arranged parallel to each other in the first direction (Fig. 2A).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Son’s semiconductor structure to include an asymmetric gate structure with materials of distinct work functions, as disclosed by Rami, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Rami’s gate structure is comparable to Son’s gate structure because they both correspond to word lines for a transistor having a dual gate structure. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Son’s dual gate structure to additionally include an asymmetrical structure; wherein portions of the asymmetrical structure includes materials with distinct work functions, as disclosed by Rami, with the predictable result of forming gate structures that can sustain high breakdown voltages while providing performance comparable to those of thin-gate transistors (Rami: [0018]).
Further, in a similar field of endeavor, Kondo teaches a transistor structure in Fig. 13; wherein a gate electrode 40 includes a first gate part 41 and a second gate part 42 (Fig. 13). Further, Kondo discloses in [0062] that the first gate part 41 has a higher work function than the second gate part 42. Further, Kondo discloses an insulating film 35, which is a portion of the second gate dielectric film 32 (materials of which are disclosed in [0054]) between the two gate parts ([0056]). Examiner asserts that the materials disclosed are commonly known in the art to be used in capping layers or barrier layers that halt the diffusion of material, e.g., impurities, between semiconducting components. In the examiner’s opinion, forming the insulating film 35 in Kondo’s device would prevent the diffusion of material between the gate parts which include n-type and p-type impurities. This is similar to Son’s teaching of the gate electrodes GE including doped semiconductor material (at least [0042]). Thus, Kondo’s teaching may be applied to the transistor structure of Son, further in view of Rami, to yield a transistor structure wherein a dielectric capping layer having a first portion, which extends in a second direction perpendicular to the first direction, disposed between the high work function electrode and the low work function electrode
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the transistor structure of Son, further in view of Rami, to include Kondo’s insulating film 35 as a capping layer, because such a modification is the result of combining prior art elements according to known methods to yield predictable results. More specifically, the transistor structure of Son, further in view of Rami, as modified by Kondo’s capping layer can yield a predictable result of preventing the flow of impurities out of the gate electrodes since a material of the gate electrode may include n-type or p-type impurities. Since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, one of ordinary skill in the art would have recognized that the results of the combination were predictable before the effective filing date of the instant invention.
Regarding dependent claim 3, Son, further in view of Rami, and Kondo, teach the semiconductor device of claim 1, wherein:
the dielectric capping layer includes silicon oxide (Kondo: [0017] and [0054]).
Regarding dependent claim 5, Son, further in view of Rami and Kondo, teach the semiconductor device of claim 1; however, Son remains silent wherein:
the low work function electrode includes doped polysilicon which is doped with an N-type impurity.
However, Son does disclose that their gate electrode materials may include doped polysilicon ([0042]).
Additionally, Rami discloses that their low work function electrode may include TiSi, wherein TiSi is known in the art to be a product formed when doping polysilicon with titanium (Ti). Further, Ti is an n-type impurity in polysilicon, this at least suggest that Rami’s low work function electrode may be formed from polysilicon which is doped with an N-type impurity .
Even further, in a similar field of endeavor, Kondo teaches in Fig. 13 that the low work function second gate part 42 may be formed from doped polysilicon which is doped with an N-type impurity (Fig. 13 and [0065]).
From at least disclosures of Son, Rami, and Kondo, it would have been obvious to form a gate electrode that includes a low work function electrode; wherein the low work function electrode is formed from doped polysilicon which is doped with an N-type impurity.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the word line/gate electrode structure of Son and Rami to include the materials disclosed by Kondo, because such a modification is the result of simple substitution of one known element for another producing a predictable result. More specifically, the materials disclosed by Rami for their low work function electrode and the materials disclosed by Kondo for their gate electrode perform the same general and predictable function, the predictable function being used to form gate electrodes. Since each individual element and its function are shown in the prior art, albeit shown in separate references, the difference between the claimed subject matter and the prior art rests not on any individual element or function but in the very combination itself - that is in the substitution of the materials disclosed by Rami for their low work function electrode by replacing it with the materials disclosed by Kondo for their gate electrode. Thus, the simple substitution of one known element for another producing a predictable result renders the claim obvious before the effective filing date of the instant invention.
Regarding dependent claim 6, Son, further in view of Rami and Kondo, teach the semiconductor device of claim 1, wherein:
the high work function electrode includes a metal-based material (Rami: [0055]).
Regarding dependent claim 7, Son, further in view of Rami and Kondo, teach the semiconductor device of claim 1, wherein:
the high work function electrode includes titanium nitride, tungsten or a stack of titanium nitride and tungsten (Rami: [0055]).
Regarding dependent claim 8, Son, further in view of Rami and Kondo, teach the semiconductor device of claim 1, wherein:
the active layer includes a semiconductor material or an oxide semiconductor material (Son: [0037]).
Regarding dependent claim 9, Son, further in view of Rami and Kondo, teach the semiconductor device of claim 1, wherein:
the active layer includes polysilicon, monocrystalline silicon, germanium, silicon germanium or IGZO (Indium Gallium Zinc Oxide) (Son: [0037]).
Regarding dependent claim 13, Son, further in view of Rami and Kondo, teach the semiconductor device of claim 1, wherein the active layer further includes:
a first source/drain region (Son: Fig. 3; first dopant region SD1) disposed on one side of the channel (Son: Fig. 3); and
a second source/drain region (Son: Fig. 3; second dopant region SD2) disposed on another side of the channel (Son: Fig. 3),
wherein the first source/drain region is adjacent to the high work function electrode, and the second source/drain region is adjacent to the low work function electrode (Yielded through the combination of Son, Rami, and Kondo).
Only two possibilities exist for the positions of the high and low work function electrodes with respect to the bit line and the capacitor, used to proxy the position of the first and second source/drain regions, respectively; either the high work function electrode is adjacent to the bit line and the low work function electrode is adjacent to the capacitor, or the low work function electrode is adjacent to the bit line and the high work function electrode is adjacent to the capacitor. Since there are a finite number of possibilities, it would have been obvious to one of ordinary skill in the art to try the different combinations with a reasonable expectation of success. Therefore, it would have been obvious to form the semiconductor/transistor device of Son, further in view of Rami, wherein the first source/drain region is adjacent to the high work function electrode, and the second source/drain region is adjacent to the low work function electrode.
Regarding dependent claim 14, Son, further in view of Rami and Kondo, teach the semiconductor device of claim 13, further comprising:
a bit line (Son: Fig. 3; bit lines BL) coupled to the first source/drain region (Son: [0043]);
a capacitor (Son: Fig. 3; data storage element DS and [0033]) including a storage node (Son: Fig. 8A; first electrode EL1) coupled to the second source/drain region (Son: [0075]);
a bit line contact node (Son: Fig. 8A; silicide pattern SC) between the bit line and the first source/drain region (Son: [0078]); and
a storage contact node (Son: Fig. 8A; second end SPe2) between the capacitor and the second source/drain region (Son: Fig. 8A and [0075]),
wherein the bit line is adjacent to the high work function electrode (Yielded through the combination of Son, Rami, and Kondo), and the storage node is adjacent to the low work function electrode (Yielded through the combination of Son, Rami, and Kondo).
Only two possibilities exist for the positions of the high and low work function electrodes with respect to the bit line and the capacitor; either the high work function electrode is adjacent to the bit line and the low work function electrode is adjacent to the capacitor, or the low work function electrode is adjacent to the bit line and the high work function electrode is adjacent to the capacitor. Since there are a finite number of possibilities, it would have been obvious to one of ordinary skill in the art to try the different combinations with a reasonable expectation of success. Therefore, it would have been obvious to form the semiconductor/transistor device of Son, further in view of Rami, such that the bit line is adjacent to the high work function electrode, and the storage node is adjacent to the low work function electrode.
Regarding dependent claim 15, Son, further in view of Rami and Kondo, teach the semiconductor device of claim 1, wherein:
the word line includes a double word line, a single word line, or a gate all around word line (Son: Fig. 3 and [0050] – [0051]).
Regarding dependent claim 26, Son, further in view of Rami and Kondo, teach the semiconductor device of claim 1; however, Son remains silent wherein
the low work function electrode is thicker than the high work function electrode.
However, in a similar field of endeavor, Kondo teaches an embodiment of TFET 200 (Fig. 21) including a lower work function gate electrode part 42 and a high work function gate electrode part 41 wherein the low work function electrode is thicker than the high work function electrode. Examiner asserts that Kondo’s embodiment shown in Fig. 21 may be used to modify the transistor structure of Son and Rami to yield a transistor structure wherein the low work function electrode is thicker than the high work function electrode.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the transistor structure of Son, further in view of Rami and Kondo, to include Kondo’s gate electrode feature wherein the low work function electrode is thicker than the high work function electrode, because such a modification is taught, suggested, or motivated by the art. More specifically, the motivation to modify the low work function electrode of Son and Rami to include Kondo’s gate electrode feature wherein the low work function electrode is thicker than the high work function electrode is implicitly provided by Fig. 21 of Kondo, showing that the low work function electrode is thicker than the high work function electrode. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the transistor structure of Son, further in view of Rami and Kondo, to include Kondo’s gate electrode feature wherein the low work function electrode is thicker than the high work function electrode, with the motivation of altering the voltage that may be applied to the material. The person of ordinary skill in the art would have recognized the benefit of providing a low work function electrode next to a high work function electrode that both function as gate electrode; wherein the low work function electrode is thicker than the high work function electrode.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Son et al. (US 20210183862 A1), and further in view of Rami et al. (US 20200259018 A1), Kondo (US 20160247917 A1), and Jung et al. (US 20210257368 A1).
Regarding dependent claim 2, Son, further in view of Rami and Kondo, teach the semiconductor device of claim 1; however, Son remains silent wherein:
the dielectric capping layer has a second portion extending to cover an upper surface and a lower surface of the high work function electrode.
However, in the same field of endeavor, Jung teaches, e.g., Fig. 17a, a transistor structure wherein a block insulating film GE_BI is formed above and below gate electrode GE1 and GE2. Examiner asserts that such a modification would have been obvious to one of ordinary skill in the art while incorporating features of Kondo to the transistor structure of Son, further in view of Rami. Thus, Jung’s disclosure may be used to modify the transistor structure of Son, further in view of Rami and Kondo, to yield a transistor structure wherein the dielectric capping layer extends to cover an upper surface and a lower surface of the high work function electrode.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the transistor structure of Son, Rami, and Kondo, to include Jung’s feature wherein the dielectric capping layer extends to cover an upper surface and a lower surface of the high work function electrode, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Jung’s dielectric capping layer is comparable to the capping layer of Son, further in view of Kondo, because they may include the same materials ([0052] of Jung). Therefore, it is within the capabilities of one of ordinary skill in the art to modify the capping layer of Son and Kondo to include Jung’s feature wherein the dielectric capping layer extends to cover an upper surface and a lower surface of the high work function electrode with the predictable result of preventing the flow of impurities out of the gate electrode layer to surrounding transistor components.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Son et al. (US 20210183862 A1), and further in view of Rami et al. (US 20200259018 A1), Kondo (US 20160247917 A1), and Oh et al. (US 20160172488 A1).
Regarding dependent claim 4, Son, further in view of Rami and Kondo, teach the semiconductor device of claim 1; however, Son remains silent wherein:
the low work function electrode has a work function lower than a mid-gap work function of silicon, and the high work function electrode has a work function higher than the mid-gap work function of silicon.
However, in the same field of endeavor, Oh discloses in [0050] that the gate electrode includes a high work function portion and a low work function portion wherein the low work function electrode has a work function lower than a mid-gap work function of silicon, and the high work function electrode has a work function higher than the mid-gap work function of silicon.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the transistor structure of Son, Rami, and Kondo, to include the device feature wherein the low work function electrode has a work function lower than a mid-gap work function of silicon, and the high work function electrode has a work function higher than the mid-gap work function of silicon, as disclosed by Oh, because such a modification is taught, suggested, or motivated by the art. More specifically, the motivation to modify the transistor structure of Son, Rami, and Kondo, to include a gate structure wherein the relative work functions of portions of the word lines/gate electrodes are such that the low work function electrode has a work function lower than a mid-gap work function of silicon, and the high work function electrode has a work function higher than the mid-gap work function of silicon, as disclosed by Oh, are explicitly provided by Oh, stating that the problem of junction leakage can be improved ([0061]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the invention to modify the transistor structure of Son, Rami, and Kondo, to include a gate structure wherein the relative work functions of portions of the word lines/gate electrodes are such that the low work function electrode has a work function lower than a mid-gap work function of silicon, and the high work function electrode has a work function higher than the mid-gap work function of silicon, as disclosed by Oh, with the motivation of improving the devices characteristics.
Claims 10 – 12 is rejected under 35 U.S.C. 103 as being unpatentable over Son et al. (US 20210183862 A1), and further in view of Rami et al. (US 20200259018 A1), Kondo (US 20160247917 A1), and Choi et al. (US 20220173106 A1).
Regarding dependent claim 10, Son, further in view of Rami and Kondo, teach the semiconductor device of claim 1; however, Son remains silent wherein the gate dielectric layer includes:
a first gate dielectric layer disposed between the low work function electrode and the active layer; and
a second gate dielectric layer disposed between the high work function electrode and the active layer and thinner than the first gate dielectric layer,
wherein the dielectric capping layer has a second portion extending to be disposed between the second gate dielectric layer and the high work function electrode.
However, Rami discloses:
a first gate dielectric layer (Fig. 2A; first gate dielectric 110-1) disposed between the low work function electrode and the active layer (Fig. 2A; fin 104. See [0036]); and
a second gate dielectric layer (Fig. 2A; first gate dielectric 110-2) disposed between the high work function electrode and the active layer (Fig. 2A) and thinner than the first gate dielectric layer (Fig. 2A), …
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the transistor structure of Son and Rami to include first and second gate dielectric layers between the low work function electrode and the active layer, and between the high work function electrode and the active layer, respectively, as disclosed by Rami, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Rami’s first and second gate dielectric layers are comparable to Son’s gate dielectric layer because they insulate the conductive gate structures from the active layer. Therefore, it is within the capabilities of one of ordinary skill in the art to modify the transistor structure of Son and Rami to include Rami’s first and second gate dielectric layers with the predictable result of improving device transduction and output resistance (Rami: [0050] – [0052]).
Further, in the same field of endeavor, Choi teaches, e.g., Fig. 18A, a transistor structure TRa wherein two types of insulating materials (Fig. 18A; gate dielectric layers 182 and separation insulating patterns 154P) are formed between the active layer and the gate electrodes. Choi’s transistor structure TRa includes a top gate electrode and a bottom gate electrode. Due to the similarity between transistor devices, examiner asserts that a modification to include a structure wherein two insulating type layers may be between the gate electrode and active layer, in view of Choi, would have been obvious to one of ordinary skill in the art; further having one of those insulating layers being a capping layer would have been obvious in view of Kondo’s transistor structure. Thus, Choi’s disclosure may be used to modify the transistor structure of Son, further in view of Rami and Kondo, to yield a transistor structure wherein the dielectric capping layer has a second portion extending to be disposed between the second gate dielectric layer and the high work function electrode.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the capping layer and gate insulating structure of Son, further in view of Rami and Kondo, to include Choi’s feature wherein the dielectric capping layer has a second portion extending to be disposed between the second gate dielectric layer and the high work function electrode, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Choi’s insulating layers are comparable to the capping layer and gate insulating layers of Son, Rami, and Kondo because they may include the same materials for insulating gate electrodes and active layers in a transistor structure. Therefore, it is within the capabilities of one of ordinary skill in the art to modify the capping layer and gate insulating structure of Son, further in view of Rami and Kondo, to include Choi’s feature wherein the dielectric capping layer has a second portion extending to be disposed between the second gate dielectric layer and the high work function electrode with the predictable result of preventing impurities from diffusing from the gate electrodes into the gate insulating layers.
Regarding dependent claim 11, Son, further in view of Rami, and Kondo, teach the semiconductor device of claim 10, wherein:
the dielectric capping layer and the first and second gate dielectric layers include the same material.
Kondo teaches that an insulating film 35 may be formed of the same material as the gate dielectric film 30 ([0054] and [0056]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the transistor structure of Son, Rami, and Kondo, to include the same materials in the gate dielectric layers and dielectric capping layer, as disclosed by Kondo, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, the insulating and capping layers used by Kondo to form insulating films and capping layers are comparable to the materials used by Son and Rami to form gate dielectric layers because the materials are insulating. Therefore, it is within the capabilities of one of ordinary skill in the art to modify the transistor structure of Son, Rami, and Kondo to include the same material in the gate dielectric layers and capping layer, as disclosed by Kondo, with the predictable result of forming gate insulating and capping structures.
Regarding dependent claim 12, Son, further in view of Rami and Kondo, teach the semiconductor device of claim 11, wherein:
each of the first gate dielectric layer and the second gate dielectric layer includes silicon oxide, silicon nitride, a metal oxide, a metal oxynitride, a metal silicate, a high-k material, a ferroelectric material, an antiferroelectric material, or a combination thereof (Rami: [0040]).
Conclusion
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to the applicant's disclosure:
US 20200105761 A1 – previously relied upon.
US 20130020570 A1 – previously relied upon.
US 11742425 B2 – considered for its disclosure of work function material.
US 20100308390 A1 – considered for the disclosed dual-gate structure wherein the conducive gate materials may include one portion made of metal and the other made of doped polysilicon.
US 20130069052 A1 – considered for their disclosed materials.
US 20130099305 A1 – considered for their pronged gate electrode structure.
US 20190067375 A1 – considered for the disclosed dual-gate structure wherein the conducive gate materials may include one portion made of metal and the other made of doped polysilicon.
US 20190103407 A1 – considered for similar structural features to the instant application.
US 20190164985 A1 – considered for similar structural features to the instant application.
US 20220181457 A1 – considered for its relevance to US 20160172488 A1.
Shao, G. (2021). Work function and electron affinity of semiconductors: Doping effect and complication due to Fermi level pinning. ENERGY & ENVIRONMENTAL MATERIALS, 4(3), 273–276. https://doi.org/10.1002/eem2.12218 - discloses a mid-gap work function for silicon to be about 4.85 eV.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARIO A AUTORE whose telephone number is (571)270-0059. The examiner can normally be reached Monday - Friday, 8 am - 5 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MARIO A. AUTORE JR.
Examiner
Art Unit 2897
/MARIO ANDRES AUTORE JR/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights