Prosecution Insights
Last updated: April 19, 2026
Application No. 17/673,727

PROGRAMMING A PACKET PROCESSING PIPELINE

Non-Final OA §103
Filed
Feb 16, 2022
Examiner
DABIPI, DIXON F
Art Unit
2451
Tech Center
2400 — Computer Networks
Assignee
Intel Corporation
OA Round
3 (Non-Final)
78%
Grant Probability
Favorable
3-4
OA Rounds
3y 0m
To Grant
92%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allow Rate
189 granted / 243 resolved
+19.8% vs TC avg
Moderate +14% lift
Without
With
+13.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
18 currently pending
Career history
261
Total Applications
across all art units

Statute-Specific Performance

§101
8.1%
-31.9% vs TC avg
§103
61.6%
+21.6% vs TC avg
§102
15.0%
-25.0% vs TC avg
§112
8.9%
-31.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 243 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/22/2025 has been entered. Response to Arguments Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claim(s) 1-3,5,9-13,17 and 19-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (CN 116033043 A) (filed 25 October 2021), in view of Atli et al. (US 2020/0028776 A1), further in view of He et al. (US 2021/0266253 A1). Regarding claim 1, Li discloses at least one non-transitory computer-readable medium comprising instructions stored thereon, that if executed by one or more processors cause the one or more processors to (Li, [0013-0014] discloses a computing device comprising a processor, the memory, a communication interface. The memory is used to store at least one executable instruction, which causes the processor to perform certain operations): perform a virtual switch (OpenFlow switch) having a Programming Protocol-independent Packet Processors (P4) proto (P4proto) portion (P4 protocol module) within an ofproto portion (OpenFlow protocol module) to provide configurations (configuration/reconfiguration of OpenFlow switch) from control plane (SDN controller) to configure packet processing actions to be performed by a programmable pipeline of a packet processing device (Li, Step 131, [0049-0054], step 131, a Software Defined Network (SDN) controller is used to provide configuration/reconfiguration of an OpenFlow switch using P4 program to improve network forwarding performance. In step 131 runtime time information of the P4 program is sent to the software defined network SDN controller and the P4 protocol module of the open switch, making the SDN controller and the P4 protocol module of the open switch interact based on the forwarding rule of the P4 protocol; the P4 protocol module of the open switch and the OpenFlow protocol module perform the configuration of the forwarding rule). Li did not explicitly disclose “multiple control planes”, wherein: the provide configurations from multiple control planes to configure packet processing actions to be performed by the programmable pipeline of the packet processing device comprises translating a first configuration from a first control plane of the multiple control planes to a compiled format compatible with the programmable pipeline to configure the programmable pipeline and provide a second configuration from a second control plane of the multiple control planes without translation to configure the programmable pipeline; the programmable pipeline is configured using the translated configuration from the first control plane and the untranslated configuration from the second control plane. In particular, Atli discloses provide configurations from multiple control planes (figs. 5&6, CP1 – CPK) to configure packet processing (fig. 7, N4 messages) actions (activate specific agent application from the specific SDN protocol type) to be performed by a programmable pipeline of a packet processing device (P4 switch 154) (Atli, [Abstract, fig. 7, [0006; 0042;0044] receiving one or more messages (configuration/messages (N4)) from the multiple control planes (CP1 – CPK), translating messages received using to activate specific agent application from the specific SDN protocol type to the programming language associated with the switching component of the network switch; and programming the switching component according to translated messages. A UPF comprising Translator 134 and Programming Protocol-Independent Packet Processor (P4 switch 154), and SMF is comprised of controller 102. Agent 121 is the Agent for N4 protocol. When selected by SMF using interface 117, Translator 134 activates only that Agent and translates the received N4 messages/configuration to a P4 program using block 158, and loads the program onto P4 switch 154. Programming protocol-independent packet processors (P4) which is a protocol and platform-independent domain specific language used to describe networking pipelines), wherein: the provide configurations from multiple control planes (figs. 5&6, CP1 – CPK) to configure packet processing (fig. 7, N4 messages) actions to be performed by the programmable pipeline (fig. 7, P4) of the packet processing device comprises translating a first configuration from a first control plane of the multiple control planes (CP1 – CPK) to a compiled format compatible with the programmable pipeline to configure the programmable pipeline (Atli, [Abstract, fig. 7, [0006; 0042] discloses receiving one or more messages (configuration/messages (N4)) from the multiple control planes (CP1 – CPK), translating messages received using to activate specific agent application from the specific SDN protocol type to the programming language associated with the switching component of the network switch; and programming the switching component according to translated messages. Fig. 7 discloses a UPF comprising Translator 134 and Programming Protocol-Independent Packet Processor (P4 switch 154), and SMF is comprised of controller 102. Agent 121 is the Agent for N4 protocol. When selected by SMF using interface 117, Translator 134 activates only that Agent and translates the received N4 messages/configuration to a P4 program using block 158, and loads the program onto P4 switch 154. Programming protocol-independent packet processors (P4) which is a protocol and platform-independent domain specific language used to describe networking pipelines), the programmable pipeline (P4 switch 154) is configured using the translated configuration (N4 messages/configuration) from the first control plane (Atli [Abstract, fig. 7, [0006; 0042] discloses a UPF comprising Translator 134 and Programming Protocol-Independent Packet Processor (P4 switch 154). The system receives configuration from multiple control plans such as CP1 – CPK. When an agent is selected by SMF using interface 117, Translator 134 activates only that Agent and translates the received N4 messages/configuration to a P4 program using block 158, and configures the P4 switch 154 using the translated configuration/program. Programming protocol-independent packet processors (P4) is a protocol and platform-independent domain specific language used to describe/configure networking pipelines). One of ordinary skill would have been motivated to combine the teachings of Li and Atli because these teachings are from the same field of endeavor with respect to programmable packet processing pipeline that is configured using a virtual switch. Therefore, it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Li with the teachings of Atli, thereby enabling configuration messages to be translated to the programming language associated with the switching component of the network switch; and (e) programming the switching component according to translated messages, Atli, [0008]. Li and Atli did not explicitly disclose provide a second configuration from a second control plane of the multiple control planes without translation to configure the programmable pipeline, and the untranslated configuration from the second control plane. He discloses provide a second configuration from a second control plane of the multiple control planes (controller 1400) without translation to configure the programmable pipeline (He, figs. 14 & 15, [0088-0090] controller 1400 and/or resource manager 1410 (second control plane) provides a second configuration that can be used to configure programmable pipeline 1422 of switch 1420 without translation and programmable pipeline 1422 of switch 1420 is to also configure match-action tables of programmable pipeline 1462 of NIC 1460. Although a single NIC is shown, switch 1420 can configure multiple NICs or IPUs. The controller 1400 executes a Virtual Switch Agent (e.g., Open vSwitch, Nginx, and so forth) that could dynamically move certain rules/configurations from NIC 1460 to switch 1420 or from switch 1420 to NIC 1460, without translation of the rules/configuration), and the programmable pipeline is configured using the untranslated configuration from the second control plane (He, figs. 14 & 15, [0088-0090] controller 1400 and/or resource manager 1410 (second control plane) provides a second configuration that can be used to configure programmable pipeline 1422 of switch 1420 without translation. The controller 1400 executes a Virtual Switch Agent (e.g., Open vSwitch, Nginx, and so forth) that could dynamically move certain rules/configurations from NIC 1460 to switch 1420 or from switch 1420 to NIC 1460). One of ordinary skill would have been motivated to combine the teachings of Li, Atli and He because these teachings are from the same field of endeavor with respect to programmable packet processing pipeline that is configured using a virtual switch. Therefore, it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Li and Atli with the teachings of He, thereby enabling performance of traffic rules for a group of one or more VMs could be performed by compute server 1450, performance of traffic rules for a different group of one or more VMs could be performed by NIC 1460, and performance of traffic rules for yet another group of one or more VMs could be performed by switch 1420, He, [0089]. Regarding claim 2, Li, Atli and He disclose the at least one non-transitory computer-readable medium of claim 1, wherein the virtual switch is to provide inter-virtual execution environment communications and the virtual switch consistent with Open vSwitch, VPP, or Stratum (He [0089] controller 1400 can execute a Virtual Switch Agent (e.g., Open vSwitch, Nginx, and so forth) or orchestration application (e.g., OpenStack, VMware vCloud, Kubernetes, and so forth) that could dynamically move certain rules from NIC 1460 to switch 1420 or from switch 1420 to NIC 1460.). The motivation to combine is similar to that of claim 1. Regarding claim 3, Li, Atli and He disclose the at least one non-transitory computer-readable medium of claim 1, wherein a programming language of at least one of the multiple control planes comprises Openflow and the programming language comprises one or more of: (P4), C, Python, Broadcom Network Programming Language (NPL), Linux eBPF, or x86 compatible executable binaries or other executable binaries (Atli, FIG. 8A, N4 messages are forwarded to agent N4. As N4 receives a forwarding rule update, it sends the required modification directives to a P4 Program Generator. P4 Program Generator prepares a new P4 program by adding new modifications to the lastly configured program and forwards to P4 switch. As P4 switch successfully implement the new P4 program, the success is reported to the SMF with “N4 Session Establishment, Modification or Termination Response”.). The motivation to combine is similar to that of claim 1. Regarding claim 5, Li, Atli and He disclose the at least one non-transitory computer-readable medium of claim 1, wherein the multiple control planes (fig. 19, Control planes 1920,1924 and 1928) comprise two or more of: a virtual switch controller, runtime server for the programmable pipeline, or kernel controller (Atli, fig. 3, [0028-0030] discloses software switches such as Open vSwitch (OVS) comprising a software-based virtual switching fabric (vSwitch) and virtual ports (vPort) on a purely software based SDN switch. The Software defined Network include SDN/server controllers and uses Programming Protocol-Independent Packet Processor (P4) as a preferred program for processing packets. Also, each of the vSwitches include controllers in the virtual switching fabric). The motivation to combine is similar to that of claim 1. Regarding claim 9, Li, Atli and He disclose the at least one non-transitory computer-readable medium of claim 1, wherein the packet processing device (network virtualization device (NVD)) comprises one or more of: a network interface controller (NIC), a remote direct memory access (RDMA)-enabled NIC, SmartNIC, router, switch, forwarding element, infrastructure processing unit (IPU), or data processing unit (DPU) (Atli [0021] discloses a network device such as a switch, router, or a controller is a piece of networking equipment, including hardware and software that communicatively interconnects other equipment on the network (e.g., other network devices, end systems). The motivation to combine is similar to that of claim 1. Regarding claim 10, Li discloses an apparatus (Li, [0013-0014] discloses a computing device comprising a processor, the memory, a communication interface. The memory is used to store at least one executable instruction, which causes the processor to perform certain operations): comprising: The rest of the limitations of claim 10 are rejected with rational similar to that of claim 1. Regarding claim(s) 11-13 the claim(s) is/are rejected with rational similar to that of claim(s) 2-3 and 5, respectively. Regarding claim 17, Li, Atli and He discloses the apparatus of claim 10, comprising a server (Network device) that is to execute the virtual switch (switch), wherein the server is communicatively coupled to the packet processing device (Processors) (Atli [0020-0023] discloses a network device that communicatively interconnects other equipment on the network devices, including switches, routers, controllers, end systems, hardware, software, processors and memory storing instructions that are executed by the processors to perform specified functions). The motivation to combine is similar to that of claim 1. Regarding claim 19, the claim is rejected with rational similar to that of claim 1. Regarding claim 20, Li, Atli and He disclose the method of claim 19, wherein a programming language of at least one of the multiple control planes comprises Openflow and the programming language comprises one or more of: (P4), C, Python, Broadcom Network Programming Language (NPL), Linux eBPF, or x86 compatible executable binaries or other executable binaries (Atli, fig. 6, [0026; 40] discloses the use of OpenFlow to specify a protocol that a switch can instantly recognize and translate its messages into the programming language of the fixed-function ASIC within the switch and program it accordingly. The rules within OpenFlow messages are programmed as match-action entries in flow-tables within the ASIC. A directly-programmable generic switch (shown as P4 switch 154). In this embodiment, Translator 134 is an adjunct to generic/P4 switch 154. It has three key functions: Agent Blades 112 that has different types of agents 121, each agent supporting a different SDN protocol (such as OpenFlow, N4, etc.) towards controller 102 representing the control plane (CP)). The motivation to combine is similar to that of claim 1. Regarding claim 21, Li, Atli and He discloses the at least one non-transitory computer-readable medium of claim 1, wherein the ofproto portion is to provide an interface consistent with OpenFlow (Li [0049-0054], step 131, discloses a Software Defined Network (SDN) controller used to provide configuration/reconfiguration of an OpenFlow switch using P4 program to improve network forwarding performance. In step 131 runtime time information of the P4 program is sent to the software defined network SDN controller and the P4 protocol module of the open switch, making the SDN controller and the P4 protocol module of the open switch interact based on the forwarding rule of the P4 protocol; the P4 protocol module of the open switch and the OpenFlow protocol module perform the configuration of the forwarding rule). The motivation to combine is similar to that of claim 1. Claim(s) 6, 14 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (CN 116033043 A), in view of Atli et al. (US 2020/0028776 A1), in view of He et al. (US 2021/0266253 A1), further in view of Brar et al. (US 2022/0210070 A1) Regarding claim 6, Li, Atli and He disclose the at least one non-transitory computer-readable medium of claim 5, but did not explicitly disclose wherein the virtual switch controller configures the programmable pipeline with header field value matches and association action(s) (identifying any policies (e.g., security lists) configured for the VNIC) related to one or more of: port selection (determining destination information for the packet from the packet headers), enabling of packet mirroring, or VXLAN utilization. Brar discloses wherein the virtual switch controller configures the programmable pipeline with header field value matches and association action(s) (identifying any policies (e.g., security lists) configured for the VNIC) related to one or more of: port selection (determining destination information for the packet from the packet headers), enabling of packet mirroring, or VXLAN utilization (Brar [0071] a packet received by a VNIC for processing is associated with the source compute instance and includes a packet header from which a selected destination port information is determined and defines routing and security policies configured for a switch performing pipeline processing of the received packet. The packet processing data path in an NVD may comprise multiple packet pipelines, each composed of a series of packet transformation stages such). One of ordinary skill would have been motivated to combine the teachings of Li, Atli, He and Brar because these teachings are from the same field of endeavor with respect to programmable packet processing pipeline that is configured using a virtual switch. Therefore, it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Li, Atli and He with the teachings of Brar, thereby enabling an L2 virtual network interface to emulate an L2 port of a L2 virtual network. Storm control information applicable to the L2 port is sent to a network virtualization device that hosts the L2 virtual network interface to improve functionality and value of virtual networks, Brar, [Abstract]. Regarding claim(s) 14 the claim(s) is/are rejected with rational similar to that of claim(s) 6. Regarding claim 18, Li, Atli and He the apparatus of claim 17, but did not explicitly disclose comprising a data center that comprises the server and a second packet processing device, wherein the packet processing device is to transmit packets processed by the programmable packet processing pipeline to the second packet processing device. Brar discloses a data center that comprises the server and a second packet processing device, wherein the packet processing device is to transmit packets processed by the programmable packet processing pipeline to the second packet processing device (Brar, fig. 1, [0065] discloses a distributed environment 100 comprises CSPI 101 that provides services and resources that customers can subscribe to and use to build their virtual cloud networks (VCNs). The CSPI 101 include data centers organized into one or more regions where is data center include physical servers (e.g., 202,203 and 208). [0113] the data centers provide packet processing data path in an NVD comprising multiple packet pipelines, each composed of a series of packet transformation stages. Upon receiving a packet, the packet is parsed and classified to a single pipeline. The packet is then processed in a linear fashion, one stage after another, until the packet is either dropped or sent out over an interface of the NVD). The motivation to combine is similar to that of claim 6. Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (CN 116033043 A), in view of Atli et al. (US 2020/0028776 A1), in view of He et al. (US 2021/0266253 A1), further in view of Wang et al. (US 2019/0075019 A1). Regarding claim 4, Li, Atli and He disclose the at least non-transitory computer-readable medium of claim 1, comprising instructions stored thereon, but did not explicitly disclose that if executed by one or more processors cause the one or more processors to: receive a configuration of table entry format and configure the programmable pipeline with at least one configuration from one or more of the multiple control planes in a format consistent with the received table entry format. Wang discloses that if executed by one or more processors cause the one or more processors to: receive a configuration of table entry format (a switch configuration list stored in the storage unit 14) and configure the programmable pipeline with at least one configuration from one or more of the multiple control planes (configuration messages from each controller) in a format consistent with the received table entry format (Wang [0033-0035;0043] discloses a switch S1 processes a received packet according to the instruction corresponding to the Table-Miss Flow entry, or the switch S1 searches for the next flow table through the pipeline. Each switch stores a configuration list in storage unit 14 in a table format. Packets received by the switch are routed through a packet processing pipeline based on a configuration message/format selected from the list of configuration messages received and stored by the switch in the storage unit 14). One of ordinary skill would have been motivated to combine the teachings of Li, Atli, He and Wang because these teachings are from the same field of endeavor with respect to packet processing pipeline that is configured using a virtual switch. Therefore, it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Li, Atli and He with the teachings of Wang which enables an automatic-configuration of a switch applicable of providing a communication channel between a SDN system controller a switch, Wang [0013]. Claim(s) 7 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (CN 116033043 A), in view of Atli et al. (US 2020/0028776 A1), in view of He et al. (US 2021/0266253 A1), further in view of Radi et al. (US 2020/0349080 A1). Regarding claim 7, Li, Atli and He disclose the at least one non-transitory computer-readable medium of claim 5, but did not explicitly disclose wherein the runtime server for the programmable pipeline configures the programmable pipeline with header field value matches and association actions related to one or more of: tunnels, mirroring, security group, connection tracking, forwarding, sampling of a flow to determine statistics, or link aggregation group (LAG). Radi discloses wherein the runtime server for the programmable pipeline configures the programmable pipeline with header field value matches and association actions related to one or more of: tunnels, mirroring, security group, connection tracking, forwarding, sampling of a flow to determine statistics, or link aggregation group (LAG) (Radi, fig.4, [0057-0060] discloses a traffic manager 38 such as a runtime server receives a cache line request. The traffic manager 38/runtime server receives the cache line request as a packet by a parser module 34 of a programmable switch 112. The parser module 34 is configured to extract values from the packet, such as a destination address, operation type, or a source address, from a header in the packet for match-action operations performed by the ingress and egress stages. The extracted header values are fed into the ingress pipeline that includes stages 36.sub.1 and 36.sub.2. Traffic manager 38 may mirror the originally received packet for the cache line request to a port for host 120 to provide host 120 with cache miss data). One of ordinary skill would have been motivated to combine the teachings of Li, Atli, He and Radi because these teachings are from the same field of endeavor with respect to packet processing pipeline that is configured using a virtual switch. Therefore, it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Li, Atli and He with the teachings of Radi which enables a programmable switch to process cache line request from a plurality of clients, Radi [Abstract]. Regarding claim 15, the claim is rejected with rational similar to that of claim 7. Claim(s) 8 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (CN 116033043 A), in view of Atli et al. (US 2020/0028776 A1), in view of He et al. (US 2021/0266253 A1), further in view of Waters (US 11,956,150 B1). Regarding claim 8, Li, Atli and He disclose the at least one non-transitory computer-readable medium of claim 5, but did not explicitly disclose wherein the kernel controller configures the programmable pipeline with one or more of: routing determination and tunneling. Waters discloses wherein the kernel controller configures the programmable pipeline with one or more of: routing determination and tunneling (Waters, col. 5, lines 34-60, discloses a programmable network device 130 that can be configured to perform various packet processing operations, including packet filtering, pipeline processing, routing, etc. A packet analysis kernel 143 is configured to parse data packets entering via one or more of interface(s) 142, and determine how to process the data packets. If the data packet is associated with user data (for example, being destined to an external network and/or end-user device), then the data packet is transmitted to pipeline processing module 144. Pipeline processing module 144 can perform various operations. For secured data packets transmitted to host 134 and/or other network nodes via host 134. The host 134 can transmit the data packet to a session management function (SMF) via an N4 interface, while maintaining a secure tunnel such as IPsec). One of ordinary skill would have been motivated to combine the teachings of Li, Atli, He and Waters because these teachings are from the same field of endeavor with respect to packet processing pipeline that is configured using a virtual switch. Therefore, it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Li, Atli and He with the teachings of waters which enables a FPGA associated with a first network, to identify a data session associated with the data packet, and based on the identifying, routing the data packet to at least one of a host module coupled to the first FPGA or a pipeline processing circuit embedded into the first FPGA., waters, col. 2, lines 17-26. Regarding claim 16, the claim is rejected with rational similar to that of claim 8. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIXON F DABIPI whose telephone number is (571)270-3673. The examiner can normally be reached on Monday - Friday from 9:00 am to 5:00 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christopher L Parry, can be reached at telephone number 571-272-8328. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from Patent Center. Status information for published applications may be obtained from Patent Center. Status information for unpublished applications is available through Patent Center to authorized users only. Should you have questions about access to the USPTO patent electronic filing system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). Examiner interviews are available via a variety of formats. See MPEP § 713.01. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) Form at https://www.uspto.gov/InterviewPractice. /D.F.D/ Examiner, Art Unit 2451 /Chris Parry/Supervisory Patent Examiner, Art Unit 2451
Read full office action

Prosecution Timeline

Feb 16, 2022
Application Filed
Mar 29, 2022
Response after Non-Final Action
Jan 24, 2025
Non-Final Rejection — §103
Apr 14, 2025
Interview Requested
Apr 28, 2025
Response Filed
Aug 17, 2025
Final Rejection — §103
Nov 21, 2025
Response after Non-Final Action
Dec 22, 2025
Request for Continued Examination
Jan 08, 2026
Response after Non-Final Action
Jan 20, 2026
Non-Final Rejection — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
78%
Grant Probability
92%
With Interview (+13.7%)
3y 0m
Median Time to Grant
High
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