DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office Action is in response to Applicant’s amendment filed on April 28, 2026. Claims 1, 12 and 18 have been amended. No claims have been added. Claims 11 and 20-22 have been cancelled, 13-17 and 23-43 have been cancelled previously. Claims 44-49 have been withdrawn. Currently, claims 1-10, 12, 18-19 and 44-49 are pending.
Response to Arguments
Applicant’s arguments filed 04/28/2026 with respect to claims 1 and 18 have been considered but are not persuasive. The reason is set forth below,
Regarding Claim 1 & 18, page 9, of the applicant’s arguments recites that “As amended, each of independent claims 1 and 18 requires selective deposition of conductively doped silicon from an exposed silicon containing surface, with the selectively deposited silicon having an average maximum- straight-line distance across individual of its crystal grains more than 200% larger than an average maximum-straight-line distance across individual crystal grains of the crystalline silicon having the exposed surface. The amendment is supported by the specification at, for example, paragraph 0033. Cai is relied upon as disclosing selectively depositing silicon having larger than the silicon from the first layer (action at page 19). However, the range recited in presently amended claims 1 and 18 does not overlap the teaching of Cai. Nor does Cia suggest this recited feature.”
However, the amendment introduces a new subject matter as the original claim set and the specification does not mention “having an average maximum-straight-line distance across individual of its crystal grains more than 200% larger than an average maximum-straight-line distance across individual crystal grains of the crystalline silicon.” See rejection under 35 USC 112 below.
Furthermore, upon further searching the newly found prior art CUI, Zhixin (US 20220045091 A1) “CUI et al.” discloses “the pedestal channel portions 11 can be polycrystalline and can have a first average grain size after crystallization annealing (if any), and the vertical semiconductor channels 60 can be polycrystalline and can have a second average grain size that is…..at least six times, and/or at least ten times, such as three to fifteen times, the first average grain size. For example, the first average grain size may be in a range from 10 nm to 100 nm, and the second average grain size may be in a range from 100 nm to 1 micron, although lesser and greater dimensions may also be employed for each of the first average grain size and the second average grain size.” ¶ [0175].
For the stated reasons above a final rejection has been made using over TOBIOKA et al. (US 20220246636 A1) in view of Hopkins et al. (US 20210358930 A1) further in view of CUI, Zhixin (US 20220045091 A1) “CUI et al.”.
Claim Objections
Claim 1 is objected to because of the following informalities:
In claim 1, lines 25-29 repeated the limitations “the selectively-deposited conductively-doped silicon being crystalline in a finished circuitry construction, having an average maximum-straight-line distance across individual of its crystal grains more than 200% larger than an average maximum-straight-line distance across individual crystal grains of the crystalline silicon;”
In claim 1 line 25 recited “being more narrow than” which should be “being narrower than”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL. —The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 1 and 18 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 and 18 recite “the selectively-deposited conductively-doped silicon being crystalline in a finished circuitry construction, having an average maximum-straight-line distance across individual of its crystal grains more than 200% larger than an average maximum-straight-line distance across individual crystal grains of the crystalline silicon;”. However, the original claim set and the specification does not mention “having an average maximum-straight-line distance across individual of its crystal grains more than 200% larger than an average maximum-straight-line distance across individual crystal grains of the crystalline silicon”. Therefore, it introduces new matter which is not covered by the original claim set and the original specification filed with the application.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 and 18 recites “the selectively-deposited conductively-doped silicon being crystalline in a finished circuitry construction, having an average maximum-straight-line distance across individual of its crystal grains more than 200% larger than an average maximum-straight-line distance across individual crystal grains of the crystalline silicon;” However, the claim did not mention “a crystalline silicon” earlier in the claim. There is insufficient antecedent basis for these limitations in the claim. Claim 1 is independent and the specification ¶ [0029] recited surface 71 and conductively doped silicon 42 both are crystalline silicon. Therefore, it is unclear which crystalline silicon is the crystalline silicon and the scope of the claim is unclear. For examination purposes, the crystalline silicon will be interpreted as exposed silicon containing surface 71 of channel material.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9-10, 12 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over TOBIOKA et al. (US 20220246636 A1) in view of Hopkins et al. (US 20210358930 A1) further in view of CUI, Zhixin (US 20220045091 A1) “CUI et al.”.
With Regard to Claim 1, TOBIOKA et al. Figs. 16A-16B, 17, 18A-18D and 21A-21B discloses a method used in forming a memory array (“a method of forming a three-dimensional memory device” ¶ [0003]) comprising strings (“a plurality of NAND memory strings” ¶ [0039]) of memory cells (“three-dimensional memory stack structures” ¶ [0063]), comprising:
forming a conductor tier (“layer 112” ¶ [0138]) comprising conductor material on a substrate (“a substrate 8” ¶ [0192]);
forming laterally-spaced memory-block regions (“each memory array region 100” ¶ [0063]; as seen in Figs. 16B and 21B, where we interpret individual memory block regions to be one of the plural memory block regions 100 separated by trenches 79) individually comprising a vertical stack (“three-dimensional memory stack structures are to be subsequently formed” ¶ [0062]) comprising alternating first tiers and second tiers (“A plurality of first electrically conductive layers 146” ¶ [0152] “an overlying insulating layer 132” ¶ [0148]; “The memory-level assembly includes at least one alternating stack 132, 146” ¶ [0156]) directly above the conductor tier, channel-material strings (“the vertical semiconductor channels 60” ¶ [0139]) extending through the first tiers and the second tiers (Fig. 18A-18D shows the channels 60 extending through first and second tiers);
forming a void space (“A source cavity 109 is formed” ¶ [0137]; as shown in Fig. 18C) directly above the conductor tier laterally-across individual of the memory-block regions, the void space comprising an exposed silicon-containing surface (“The lower source-level semiconductor layer 112 and the upper source-level semiconductor layer 116 may include a doped semiconductor material such as doped polysilicon or doped amorphous silicon.” ¶ [0057]; Fig. 18C shows the void space 109 is in between 112 and 116 and both layers contain silicon); and
selectively depositing conductively-doped silicon onto and from the exposed silicon-containing surface (“selective semiconductor deposition process grows a doped semiconductor material having a doping of the second conductivity type from physically exposed semiconductor surfaces around the source cavity 109.” ¶ [0141]), the doped silicon (“The deposited doped semiconductor material forms a source contact layer 114” ¶ [0141]) being directly electrically coupled to the channel material of the channel-material strings (“contact sidewalls of the vertical semiconductor channels 60.” ¶ [0141]) and being directly electrically coupled to the conductor material of the conductor tier (Fig. 18D shows 114 is directly coupled to 112) and directly electrically coupling the channel-material strings to the conductor material of the conductor tier (Fig. 18D shows 114 is directly connected to channel 60 and layer 112).
However, TOBIOKA et al. does not explicitly discloses conductively doped silicon, the memory-block regions being laterally spaced from one another by individual horizontally-elongated trenches, the conductively-doped silicon being selectively deposited to have lateral edges that are laterally inward of the lateral edges of the memory-block regions, and forming an intervening material within the horizontally-elongated trenches, the intervening material having an upper portion extending elevationally from an upper surface of the stack to a bottommost surface of the stack and having a lower portion extending from the upper portion to the conductor tier, an entirety of the upper portion being narrower than and an entirety of the lower portion,
the selectively-deposited conductively-doped silicon being crystalline in a finished circuitry construction, having an average maximum-straight-line distance across individual of its crystal grains more than 200% larger than an average maximum-straight-line distance across individual crystal grains of the crystalline silicon;
In the similar field of endeavor of memory devices, Hopkins et al. Fig. 35 discloses conductively doped silicon (“conductively-doped polysilicon 47” ¶ [0015]; “conductive materials 42 are conductively-doped semiconductor material (e.g., conductively-doped polysilicon)” ¶ [0038]), the memory-block regions being laterally spaced from one another (“longitudinally-along immediately-laterally-adjacent memory blocks 58.” ¶ [0045]) by individual horizontally-elongated trenches (“Horizontally-elongated trenches 40” ¶ [0031]), the conductively-doped silicon 42 & 47 being selectively deposited to have lateral edges that are laterally inward of the lateral edges (Fig. 35 shows conductive material 42 & 47 are laterally inward of the lateral edges of 58) of the memory-block regions 58, and
forming an intervening material (“Intervening material 57 has been formed” ¶ [0045]) within the horizontally-elongated trenches 40, the intervening material 57 having an upper portion (Portion of the 57 above 18L in Fig. 35) extending elevationally from an upper surface (Upper surface of the trench 40 in Fig. 35) of the stack to a bottommost surface (lower surface of the trench 40 in Fig. 35) of the stack and having a lower portion (Portion of the 57 below 18U in Fig. 35) extending from the upper portion (Portion of the 57 above 18L in Fig. 35) to the conductor tier,
the intervening material 57 having a uniform width along an entirety of the upper portion (Fig. 35 shows intervening material 57 has a uniform width in the upper portion) being narrower than (Fig. 35 shows upper portion of intervening material 57 is narrower than lower portion of intervening material 57) an entirety of the lower portion (Portion of the 57 below 18U in Fig. 35; Fig. 35 shows intervening material 57 has a uniform width in the lower portion).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the doped silicon layer of TOBIOKA et al. with the conductively doped silicon layer that have lateral edges laterally inward and intervening material of Hopkins et al. in order to provide lateral electrical isolation (insulation) between immediately-laterally-adjacent memory-blocks. Such may include one or more of insulative, semiconductive, and conducting materials and, regardless, may facilitate conductive tiers from shorting relative one another in a finished circuitry construction (Hopkins, ¶ [0045]).
However, Hopkins et al. does not disclose the selectively-deposited conductively-doped silicon being crystalline in a finished circuitry construction, having an average maximum-straight-line distance across individual of its crystal grains more than 200% larger than an average maximum-straight-line distance across individual crystal grains of the crystalline silicon;
In the similar field of endeavor of memory device CUI et al. discloses the selectively-deposited conductively-doped silicon being crystalline in a finished circuitry construction, having an average maximum-straight-line distance across individual of its crystal grains more than 200% larger than an average maximum-straight-line distance across individual crystal grains of the crystalline silicon (“the pedestal channel portions 11 can be polycrystalline and can have a first average grain size after crystallization annealing (if any), and the vertical semiconductor channels 60 can be polycrystalline and can have a second average grain size that is…..at least six times, and/or at least ten times, such as three to fifteen times, the first average grain size. For example, the first average grain size may be in a range from 10 nm to 100 nm, and the second average grain size may be in a range from 100 nm to 1 micron, although lesser and greater dimensions may also be employed for each of the first average grain size and the second average grain size.” ¶ [0175]; when the second grain size is at least six times which is 600% and is larger than 200%);
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the doped silicon layer of TOBIOKA et al. with the conductively doped silicon layer that have lateral edges laterally inward and intervening material of Hopkins et al. with the different grain size of CUI et al. so that the n-type dopant atoms in the source contact layer diffuse in the pedestal channel portions at a lower diffusion rate than in the vertical semiconductor channels (CUI et al., [00174]).
With Regard to Claim 2, TOBIOKA et al. as modified by Hopkins et al. and CUI et al. discloses the limitation of claim 1 as discussed above. TOBIOKA et al. further discloses wherein the silicon-containing surface (103 and 105) (“lower sacrificial liner 103 and the upper sacrificial liner 105 may include silicon oxide, silicon nitride, and/or a dielectric metal oxide” ¶ [0059) on and from which the conductively-doped silicon (“the doped semiconductor material may include doped polysilicon” ¶ [0142]) is selectively deposited comprises silicon of the channel material (“channel material layer 60L includes, and/or consists essentially of, boron-doped amorphous silicon or boron-doped polysilicon.” ¶ [0126]; the claim language is merely requiring that all three elements be made of silicon and TOBIOKA et al. discloses that all the required layers comprise silicon containing material).
With Regard to Claim 3, TOBIOKA et al. as modified by Hopkins et al. and CUI et al. discloses the limitation of claim 1 as discussed above. TOBIOKA et al. further discloses wherein the silicon-containing surface on and from (103 and 105) which the conductively-doped silicon 114 is selectively deposited comprises a floor (Figs. 18B-18D show layer 103 make the floor of the void space on layer 112) of the void space 109.
With Regard to Claim 4, TOBIOKA et al. as modified by Hopkins et al. and CUI et al. discloses the limitation of claim 3 as discussed above. TOBIOKA et al. further discloses wherein the floor comprises the conductor material (“lower source-level semiconductor layer 112 and the upper source-level semiconductor layer 116 may include a doped semiconductor material such as doped polysilicon or doped amorphous silicon.” ¶ [0057]; the void space floor is on the layer 112, therefore the conductive material of the void space is same as the conductive material of the conductive tier layer 112) of the conductor tier 112.
With Regard to Claim 5, TOBIOKA et al. as modified by Hopkins et al. and CUI et al. discloses the limitation of claim 1 as discussed above. TOBIOKA et al. further discloses wherein the silicon-containing surface on and from which the conductively-doped silicon is selectively deposited comprises a ceiling (Figs. 18B-18D show layer 105 make the floor of the void space under layer 116) of the void space 109.
With Regard to Claim 6, TOBIOKA et al. as modified by Hopkins et al. and CUI et al. discloses the limitation of claim 1 as discussed above. TOBIOKA et al. further discloses wherein the silicon-containing surface (103 and 105) (“lower sacrificial liner 103 and the upper sacrificial liner 105 may include silicon oxide, silicon nitride, and/or a dielectric metal oxide” ¶ [0059) on and from which the conductively-doped silicon (“the doped semiconductor material may include doped polysilicon” ¶ [0142]) is selectively deposited comprises silicon of the channel material (“channel material layer 60L includes, and/or consists essentially of, boron-doped amorphous silicon or boron-doped polysilicon.” ¶ [0126]; the claim language is merely requiring that all three elements be made of silicon and TOBIOKA et al. discloses that all the required layers comprise silicon containing material),
a floor (Figs. 18B-18D show layer 103 make the floor of the void space on layer 112) of the void space, and
a ceiling (Figs. 18B-18D show layer 105 make the floor of the void space under layer 116) of the void space.
With Regard to Claim 7, TOBIOKA et al. as modified by Hopkins et al. and CUI et al. discloses the limitation of claim 1 as discussed above. TOBIOKA et al. further discloses wherein the first tiers 142 are conductive tiers (“material layers 142 may comprise an insulating material, a semiconductor material, or a conductive material. The second material of the first sacrificial material layers 142 may be subsequently replaced with electrically conductive electrode” ¶ [0072]) in a finished circuitry construction (“material layers 142 may comprise ….. a conductive material. The second material of the first sacrificial material layers 142 may be subsequently replaced with electrically conductive electrodes which may function, for example, as control gate electrodes of a vertical NAND device” ¶ [0072]) and the second tiers are insulative tiers (“first insulating layers 132” ¶ [0070]) in the finished circuitry construction (Fig. 19 shows a finished circuitry with the insulating layers 132), the void space 109 being in a lowest of the conductive tiers (“source-level semiconductor layer 116” ¶ [0056]; Fig. 18B shows the cavity 109 is in a lowest level conductive tiers) .
With Regard to Claim 9, TOBIOKA et al. as modified by Hopkins et al. and CUI et al. discloses the limitation of claim 1 as discussed above. TOBIOKA et al. further discloses wherein the selectively depositing is of polysilicon (“selective semiconductor deposition process may be selected such that the source cavity 109 is filled with the source contact layer 114, …. the doped semiconductor material may include doped polysilicon” ¶ [0142]).
With Regard to Claim 10, TOBIOKA et al. as modified by Hopkins et al. and CUI et al. discloses the limitation of claim 1 as discussed above. TOBIOKA et al. further discloses wherein the selectively depositing is of amorphous silicon and further comprising annealing the amorphous silicon to form polysilicon therefrom (“doped amorphous silicon that may be subsequently converted into doped polysilicon by an anneal process” ¶ [0060]; as the layer 114 comprises doped polysilicon and in the same embodiment, layer 118 also comprises doped polysilicon which is from doped amorphous silicon that may be subsequently converted into doped polysilicon by an anneal process, it is obvious that the layer 114 is also converted using annealing process to make a functional semiconductor for use in a high performance setting).
With Regard to Claim 12, TOBIOKA et al. as modified by Hopkins et al. and CUI et al. discloses the limitation of claim 1 as discussed above. However, TOBIOKA et al. does not disclose wherein the average maximum-straight-line distance across the individual crystal grains of the selectively-deposited conductively-doped silicon in the finished circuitry construction is no more than 10,000% greater than the average maximum-straight-line distance across the individual crystal grains of the crystalline silicon.
In the similar field of endeavor of memory device CUI et al. discloses the average maximum-straight-line distance across the individual crystal grains of the selectively-deposited conductively-doped silicon in the finished circuitry construction is no more than 10,000% greater than the average maximum-straight-line distance across the individual crystal grains of the crystalline silicon (“the pedestal channel portions 11 can be polycrystalline and can have a first average grain size after crystallization annealing (if any), and the vertical semiconductor channels 60 can be polycrystalline and can have a second average grain size that is…..at least six times, and/or at least ten times, such as three to fifteen times, the first average grain size. For example, the first average grain size may be in a range from 10 nm to 100 nm, and the second average grain size may be in a range from 100 nm to 1 micron, although lesser and greater dimensions may also be employed for each of the first average grain size and the second average grain size.” ¶ [0175]; when the second grain size is 3 to 15 times which is less than 10,000%);
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the doped silicon layer of TOBIOKA et al. with the conductively doped silicon layer that have lateral edges laterally inward and intervening material of Hopkins et al. with the different grain size of CUI et al. so that the n-type dopant atoms in the source contact layer diffuse in the pedestal channel portions at a lower diffusion rate than in the vertical semiconductor channels (CUI et al., [00174]).
With Regard to Claim 18, TOBIOKA et al. Figs. 16, 17, 18A-18D and 21A-21B discloses a method used in forming a memory array (“a method of forming a three-dimensional memory device” ¶ [0003]) comprising strings (“a plurality of NAND memory strings” ¶ [0039]) of memory cells (“three-dimensional memory stack structures” ¶ [0063]), comprising:
forming a conductor tier (“layer 112” ¶ [0138]) comprising conductor material on a substrate (“a substrate 8” ¶ [0192]);
forming laterally-spaced memory-block regions (“each memory array region 100” ¶ [0063]; as seen in Figs. 16B and 21B, where we interpret individual memory block regions to be one of the plural memory block regions 100 separated by trenches 79)
individually comprising a vertical stack (“three-dimensional memory stack structures are to be subsequently formed” ¶ [0062]) comprising alternating first tiers and second tiers (“A plurality of first electrically conductive layers 146” ¶ [0152] “an overlying insulating layer 132” ¶ [0148]; “The memory-level assembly includes at least one alternating stack 132, 146” ¶ [0156]) directly above the conductor tier, channel-material strings (“the vertical semiconductor channels 60” ¶ [0139]) extending through the first tiers and the second tiers (Fig. 18A-18D shows the channels 60 extending through first and second tiers);
the channel-material of the channel-material strings comprising crystalline silicon (“channel material layer 60L includes, and/or consists essentially of, boron-doped amorphous silicon or boron-doped polysilicon.” ¶ [0126]) directly above the conductor tier laterally-across individual of the memory-block regions,
the void space comprising exposed sidewall surfaces comprising the crystalline silicon of the channel-material strings (Fig. 18C shows the void space is in contact with the exposed surface of the channel material); and
selectively depositing doped silicon onto and from silicon-containing surfaces (“selective semiconductor deposition process grows a doped semiconductor material having a doping of the second conductivity type from physically exposed semiconductor surfaces around the source cavity 109.” ¶ [0141]), comprising the exposed sidewall surfaces of the crystalline silicon of the channel-material strings (Fig. 18D shows 114 is filled in the exposed surface of the channel material),
the doped silicon (“The deposited doped semiconductor material forms a source contact layer 114” ¶ [0141]) being directly electrically coupled to the channel material of the channel-material strings (“contact sidewalls of the vertical semiconductor channels 60.” ¶ [0141]) and being directly electrically coupled to the conductor material of the conductor tier (Fig. 18D shows 114 is directly coupled to 112) and directly electrically coupling the channel-material strings to the conductor material of the conductor tier (Fig. 18D shows 114 is directly connected to channel 60 and layer 112).
with opposing of the lateral edges of the memory-block regions within each of the individual horizontally-elongated trenches being spaced from each other by an equal distance along an entirety of a height of the vertical stack (Figs. 16B and 21B, shows opposing lateral edges of the memory-block regions 100 within each of the individual horizontally-elongated trenches 79 being spaced from each other by an equal distance along an entirety of a height of the vertical stack).
However, TOBIOKA et al. does not explicitly discloses conductively doped silicon and channel-material strings comprising crystalline silicon, the memory-block regions being laterally spaced from one another by individual horizontally-elongated trenches, the trenches defining lateral edges of the memory-block regions; the conductively-doped silicon being selectively deposited to have lateral edges that are laterally inward of the lateral edges of the memory-block regions and
filling the trenches with an isolation material, an upper portion of the isolation material being within the stack and a lower portion of the isolation material extending from a bottom of the stack to the conductor tier, isolation material being narrower along an entirety of the upper portion relative to a minimum width of the lower portion,
the selectively-deposited conductively-doped silicon being crystalline in a finished circuitry construction, having an average maximum-straight-line distance across individual of its crystal grains more than 200% larger than an average maximum-straight-line distance across individual crystal grains of the crystalline silicon;
In the similar field of endeavor of memory devices, Hopkins et al. Fig. 35 discloses conductively doped silicon (“conductively-doped polysilicon 47” ¶ [0015]; “conductive materials 42 are conductively-doped semiconductor material (e.g., conductively-doped polysilicon)” ¶ [0038]), and channel-material strings comprising crystalline silicon (“channel materials 36 include appropriately-doped crystalline semiconductor material, such as one or more silicon,” ¶ [0025]), the memory-block regions being laterally spaced from one another (“longitudinally-along immediately-laterally-adjacent memory blocks 58.” ¶ [0045]) by individual horizontally-elongated trenches (“Horizontally-elongated trenches 40” ¶ [0031]), the conductively-doped silicon 42 & 47 being selectively deposited to have lateral edges that are laterally inward of the lateral edges (Fig. 35 is laterally inward of the lateral edges of 58) of the memory-block regions 58 and
filling the trenches 40 with an isolation material (“Intervening material 57 has been formed in trenches 40”; “Intervening material 57 may provide lateral electrical isolation (insulation) between immediately-laterally-adjacent memory blocks.” ¶ [0045]), an upper portion of the isolation material (Portion of the 57 above 18L in Fig. 35) being within the stack and a lower portion of the isolation material (Portion of the 57 above 18L in Fig. 35) extending from a bottom of the stack to the conductor tier, isolation material being narrower (Fig. 35 shows intervening material 57 has a uniform width in the upper portion and uniform lower portion and upper portion of 57 is narrower than lower portion of 57) along an entirety of the upper portion (Portion of the 57 above 18L in Fig. 35) relative to a minimum width (Fig. 35 shows intervening material 57 has a uniform width in the lower portion) of the lower portion (Portion of the 57 below 18U in Fig. 35).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the doped silicon layer of TOBIOKA et al. with the conductively doped silicon layer that have lateral edges laterally inward of Hopkins et al. in order to provide lateral electrical isolation (insulation) between immediately-laterally-adjacent memory-blocks. Such may include one or more of insulative, semiconductive, and conducting materials and, regardless, may facilitate conductive tiers from shorting relative one another in a finished circuitry construction (Hopkins, ¶ [0045]).
However, Hopkins et al. does not disclose the selectively-deposited conductively-doped silicon being crystalline in a finished circuitry construction, having an average maximum-straight-line distance across individual of its crystal grains more than 200% larger than an average maximum-straight-line distance across individual crystal grains of the crystalline silicon;
In the similar field of endeavor of memory device CUI et al. discloses the selectively-deposited conductively-doped silicon being crystalline in a finished circuitry construction, having an average maximum-straight-line distance across individual of its crystal grains more than 200% larger than an average maximum-straight-line distance across individual crystal grains of the crystalline silicon (“the pedestal channel portions 11 can be polycrystalline and can have a first average grain size after crystallization annealing (if any), and the vertical semiconductor channels 60 can be polycrystalline and can have a second average grain size that is…..at least six times, and/or at least ten times, such as three to fifteen times, the first average grain size. For example, the first average grain size may be in a range from 10 nm to 100 nm, and the second average grain size may be in a range from 100 nm to 1 micron, although lesser and greater dimensions may also be employed for each of the first average grain size and the second average grain size.” ¶ [0175]; when the second grain size is at least six times which is 600% and is larger than 200%);
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the doped silicon layer of TOBIOKA et al. with the conductively doped silicon layer that have lateral edges laterally inward and intervening material of Hopkins et al. with the different grain size of CUI et al. so that the n-type dopant atoms in the source contact layer diffuse in the pedestal channel portions at a lower diffusion rate than in the vertical semiconductor channels (CUI et al., [00174]).
Claim 8 and 19 is rejected under 35 U.S.C. 103 as being unpatentable over TOBIOKA et al. (US 20220246636 A1) in view of Hopkins et al. (US 20210358930 A1) further in view of CUI, Zhixin (US 20220045091 A1) “CUI et al.” further in view of KANG et al. (US 20200168629 A1).
With Regard to Claim 8, TOBIOKA et al. as modified by Hopkins et al. and CUI et al. discloses the limitation of claim 1 as discussed above. However, TOBIOKA et al. does not disclose wherein the selectively depositing is of epitaxial silicon.
In the similar field of endeavor of memory devices, KANG et al. Figs. 8B-8F discloses wherein the selectively depositing is of epitaxial silicon (“The contact source layer 287 may be formed of a doped silicon layer including a source dopant. The contact source layer 287 may be formed a selective growth process (e.g., Selective Epitaxial Growth (SEG))” ¶ [0151-0152]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the silicon layer of TOBIOKA et al. with the epitaxial silicon of KANG et al. in order to fabricate high quality crystal semiconductor to enhance performance.
With Regard to Claim 19, TOBIOKA et al. as modified by Hopkins et al. and CUI et al. discloses the limitation of claim 18 as discussed above. However, TOBIOKA et al. does not disclose wherein the selectively depositing is of epitaxial silicon.
In the similar field of endeavor of memory devices, KANG et al. Figs. 8B-8F discloses wherein the selectively depositing is of epitaxial silicon (“The contact source layer 287 may be formed of a doped silicon layer including a source dopant. The contact source layer 287 may be formed a selective growth process (e.g., Selective Epitaxial Growth (SEG))” ¶ [0151-0152]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the silicon layer of TOBIOKA et al. with the epitaxial silicon of KANG et al. in order to fabricate high quality crystal semiconductor to enhance performance.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior arts, Wu et al. (US 11488977 B2) filing date 2021-01-12; Rabkin et al. (US 9287290 B1) filing date 2015-02-11; SHIN et al. (US 20230040214 A1) filing date 2022-02-15; Greenlee et al. (US 20230055422 A1) filing date 2021-08-23; Hopkins et al. (US 20210358939 A1) filing date 2020-05-13; Hopkins et al. (US 20210280595 A1) filing date 2020-03-03; and Hopkins et al. (US 20210280594 A1) filing date 2020-03-03 made of record and not relied upon is considered pertinent to applicant’s disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AKHEE SARKER-NAG whose telephone number is (703)756-4655. The examiner can normally be reached Monday -Friday 7:15 AM to 5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, YARA J. GREEN can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AKHEE SARKER-NAG/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
