Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Remarks
The Examiner acknowledges the amendments to claims, and to the drawings.
Applicant Initiated Interview
The Examiner acknowledges and generally agrees with the short summary of the interview held on 10/01/2025.
Objections to the Drawings
The Examiner acknowledges the amendments to the applicant’s drawings, and withdraws the drawing objections due to the amendments to the drawings.
Claim interpretation under 35 U.S.C. 112(f)
The Examiner acknowledges and has fully considered the applicant’s arguments regarding claim interpretation under 112(f). The Examiner has been persuaded by the arguments and withdraws 112(f) claim interpretations.
Rejections under 35 U.S.C. 112(a)
The Examiner acknowledges and has fully considered the applicant’s arguments regarding the 112(a) rejections. The Examiner has been persuaded by the applicant’s arguments and withdraws the 112(a) rejections regarding claims 1-20
Rejections under 35 U.S.C. 112(b)
The Examiner acknowledges the applicant’s amendments to claims 16 and 17, and withdraws the 112(b) rejection due to the amendments. Furthermore, the Examiner withdraws the 112(b) rejections to claims 1, 3-8, 18, 20, 11, and 13-17 due to the applicant’s earlier arguments regarding the vector circuit.
Rejections under 35 U.S.C. 102 and 103
The Examiner acknowledges and has fully considered the amendments made to the independent claims. The Examiner acknowledges amendments made to the independent claims. The applicant seemingly asserts that the Examiner agreed that the amendments to the independent claims would overcome the current rejections, Remarks page 3. The Examiner notes, however, that the amendments which are made to the claims differ than the amendments that were proposed and discussed during the interview held on 10/1/2025. Furthermore, while the Examiner expressed that the proposed amendments would likely overcome the listed prior art, no agreement was reached. The Examiner respectfully disagrees with the applicant that the current amendments overcome the listed prior art.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, claim 1 recites the limitations of: “dispatch a first instruction to a sequencer circuit, a second instruction to a scalar circuit, a third instruction to a load and store circuit, or a fourth instruction to the vector circuit”. It is unclear if it is meant to be understood as dispatch the first instruction or second instruction or third instruction or fourth instruction, or it is meant to be understood as dispatch a first instruction and second instruction then a third or fourth instruction, or if it is meant to be understood as dispatch the first three instructions or the fourth instruction, or any other combination of dispatching the four instructions. For purposes of Examination, the Examiner interprets the claim limitation as: dispatch a first instruction to a sequencer circuit, or a second instruction to a scalar circuit, or a third instruction to a load and store circuit or a fourth instruction to the vector circuit.
Claims 2-10 inherit the same deficiency as claim 1 based on dependence.
Regarding claim 11, claim 11 recites the recites the limitations of: “dispatching, by the align and dispatch circuit, a first instruction to a sequencer circuit, a second instruction to a scalar circuit, a third instruction to a load and store circuit, or a fourth instruction to the vector circuit”. It is unclear if it is meant to be understood as dispatch the first instruction or second instruction or third instruction or fourth instruction, or it is meant to be understood as dispatch a first instruction and second instruction then a third or fourth instruction, or if it is meant to be understood as dispatch the first three instructions or the fourth instruction, or any other combination of dispatching the four instructions. For purposes of Examination, the Examiner interprets the claim limitation as: dispatch a first instruction to a sequencer circuit, or a second instruction to a scalar circuit, or a third instruction to a load and store circuit or a fourth instruction to the vector circuit.
Claims 12-17 inherit the same deficiency as claim 11 based on dependence.
Regarding claim 18, claim 18 recites the limitations of: “dispatch a first instruction to a sequencer circuit, a second instruction to a scalar circuit, a third instruction to a load and store circuit, or a fourth instruction to the vector circuit”. It is unclear if it is meant to be understood as dispatch the first instruction or second instruction or third instruction or fourth instruction, or it is meant to be understood as dispatch a first instruction and second instruction then a third or fourth instruction, or if it is meant to be understood as dispatch the first three instructions or the fourth instruction, or any other combination of dispatching the four instructions. For purposes of Examination, the Examiner interprets the claim limitation as: dispatch a first instruction to a sequencer circuit, or a second instruction to a scalar circuit, or a third instruction to a load and store circuit or a fourth instruction to the vector circuit.
Claims 19-20 inherit the same deficiency as claim 18 based on dependence.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7, and 10-17 are rejected under 35 U.S.C. 102(a)(1), and 102(a)(2) as being anticipated by Heinecke et al. (U.S. Patent Application Publication No. US 2019/0079767 A1), hereinafter “Heinecke”.
With regards to claim 1, Heinecke teaches:
An accelerator circuit comprising: (Fig. 1);
a vector circuit; (Fig. 1 item 117 (execution circuitry); Fig. 2 item 200 (processor), 214 (execution circuitry));
an instruction memory to store a plurality of instructions; (Fig. 1 item 101 (storage); [0042]
regarding instructions fetched from storage (101) (as memory));
an align and dispatch circuitry configured to: receive from the instruction memory an instruction packet comprising multiple instructions stored in a same address in the instruction memory; (Fig. 1 items 109 (Decode circuitry), 113 (register rename/scheduling circuit) and the multiple outputs from the scheduling circuit based on the single instruction; [0042] regarding the decode circuitry taking the instructions and generating it into one or more operations);
and dispatch a first instruction to a sequencer circuit, a second instruction to a scalar circuit, a third instruction to a load and store circuit, or a fourth instruction to the vector circuit; (Fig. 1 items 109 (decode circuitry), 113(scheduling circuit) output to the execution circuitry, as a fourth instruction);
and a data memory to store input data; ([0040] regarding source vectors located in memory (as data memory); Fig. 1 item 115 (register file/memory); Fig. 2 items 204, 206, 208 regarding location of a first, and second source, and output (destination) in reg/mem);
wherein the vector circuit is coupled to the instruction memory and the data memory, (Fig. 1 items 101 (storage), 115 (register file/memory), 117 (execution circuitry); Fig. 2 items 204, 206, 208 regarding location of a first, and second source, and output (destination) in reg/mem);
the vector circuit configured to: read at least a subset of the instructions of the instruction packet from the align and dispatch circuit that is to receive the instruction packet from the instruction memory, (Fig. 1 items 101 (storage), 105 (fetch), 109 (decode), 113 (scheduling circuit), 117 (Execution circuitry); Fig. 2; [0046] regarding fetch and decode circuitry to read instructions; [0042] regarding the decode circuitry taking the instructions and generating it into one or more operations);
each instruction in the at least the subset of the instructions to include a first identification of at least a portion of a first vector and a second identification of at least a portion of a second vector, (Fig. 2 item 201 (instruction), 206 (first source location), 208 (second source location), 212A (first source), 212B (second source); [0045] regarding the first and second source being vectors);
decode each instruction in the at least the subset of the instructions; (Fig. 2; [0045]-[0046] regarding that the apparatus of fig. 2 (which is of the execution circuitry), decodes instructions which have fields to specify opcode, first and second source locations, and destination vectors);
receive at least a portion of the input data from the data memory that corresponds to the at least the subset of the instructions, (Fig. 1 item 115 (register file/memory), 117 (execution circuitry); Fig. 2 item 201 (instruction), 206 (first source location from reg/mem), 208 (second source location from reg/mem), 212A (first source), 212B (second source); [0045] regarding the first and second source being vectors; [0046] regarding the instruction containing first source data and second source data);
and perform a respective vector operation in accordance with each instruction in the subset on at least one first element of the first vector and at least one second element of the second vector from the received portion of input data (Fig. 1 117 (execution circuitry); Fig. 2 item 201 (instruction), 202 (opcode), 206 (first source location from reg/mem), 208 (second source location from reg/mem), 212A (first source), 212B (second source), 214 (execution circuitry); [0045] regarding the first and second source being vectors; [0046] regarding the opcode from the instruction set indicating operations for the execution circuitry to perform on the first vector data and second vector data);
to generate at least one output element of an output vector, (Fig. 2 item 204 (destination location), 214 (execution circuitry), 218 (destination vector as an output vector); [0037] regarding the instruction performing operations on two source inputs and outputting the result to a destination vector);
each instruction in the subset indicating positions in respective vectors for (i) the at least one first element, (ii) the at least one second element, and (iii) the at least one output element. (Fig. 2 item 201 (instruction), 206 (first source location), 208 (second source location), 212A (first source), 212B (second source), 204 (destination location, 218 (destination vector as output vector); [0045] regarding the first and second source being vectors).
With regards to claim 2, Heinecke teaches the accelerator circuit of claim 1, as referenced above.
Heinecke further teaches:
wherein each instruction in the subset indicates at least one position in the first vector for the at least one first element, at least one position in the second vector for the at least one second element, and least one position in the output vector for the at least one output element. (Fig. 2 item
201 (instruction), 206 (first source location), 208 (second source location), 212A (first source), 212B (second source), 204 (destination location, 218 (destination vector as output vector); [0045] regarding the first and second source being vectors; [0056] regarding instructions defining locations of bits; As interpreted by the Examiner, [0056] recites the instructions defining locations of bits, and Fig. 2 shows arrows from specific individual elements from the first source (212A), and the second source (212B), to the execution circuit (214), and from the execution circuit to the specific location in the destination vector (218)).
With regards to claim 3, Heinecke teaches the accelerator circuit of claim 1, as referenced above.
Heinecke further teaches:
wherein the vector circuit is further configured to: perform the respective vector operation on a first plurality of elements of the first vector and a second plurality of elements of the second vector to generate a plurality of output elements of the output vector, (Fig. 1 117 (execution circuitry); Fig. 2 item 201 (instruction), 202 (opcode), 206 (first source location from reg/mem), 208 (second source location from reg/mem), 212A (first source), 212B (second source), 214 (execution circuitry), as noted by the Examiner, fig. 2 indicates multiple elements from the first and second vectors used in computations in the execution circuitry; [0045] regarding the first and second source being vectors; [0046] regarding the opcode from the instruction set indicating operations for the execution circuitry to perform on the first vector data and second vector data);
wherein each instruction in the subset indicates a plurality of positions in the first vector for the first plurality of elements, a plurality of positions in the second vector for the second plurality of elements, and a plurality of positions in the output vector for the plurality of output elements. (Fig. 2 item 201 (instruction), 206 (first source location), 208 (second source location), 212A (first source), 212B (second source), 204 (destination location, 218 (destination vector as output vector); [0045] regarding the first and second source being vectors; [0056] regarding instructions defining locations of bits; As interpreted by the Examiner, [0056] recites the instructions defining locations of bits, and Fig. 2 shows arrows from specific individual elements from the first source (212A), and the second source (212B), to the execution circuit (214), and from the execution circuit to the specific location in the destination vector (218)).
With regards to claim 4, Heinecke teaches the accelerator circuit of claim 1, as referenced above.
Heinecke further teaches:
wherein the vector circuit is further configured to: perform the respective vector operation on a first plurality of elements of the first vector and a second element of the second vector (Fig. 1 117 (execution circuitry); Fig. 2 item 201 (instruction), 202 (opcode), 206 (first source location from reg/mem), 208 (second source location from reg/mem), 212A (first source), 212B (second source), 214 (execution circuitry), as noted by the Examiner, fig. 2 indicates multiple elements from the first and second vectors used in computations in the execution circuitry; [0045] regarding the first and second source being vectors; [0046] regarding the opcode from the instruction set indicating operations for the execution circuitry to perform on the first vector data and second vector data);
to generate a plurality of output elements of the output vector, (Fig. 1 117 (execution circuitry); Fig. 2 item 201 (instruction), 202 (opcode), 206 (first source location from reg/mem), 208 (second source location from reg/mem), 212A (first source), 212B (second source), 214 (execution circuitry), destination vector (218), as noted by the Examiner, fig. 2 indicates multiple elements from the first and second vectors used in computations in the execution circuitry, and output as a destination vector (made up of a plurality of elements); [0046] regarding the opcode from the instruction set indicating operations for the execution circuitry to perform on the first vector data and second vector data);
wherein each instruction in the subset indicates a plurality of positions in the first vector for the first plurality of elements, a position in the second vector for the second element, and a plurality of positions in the output vector for the plurality of output elements. (Fig. 2 item 201 (instruction), 206 (first source location), 208 (second source location), 212A (first source), 212B (second source), 204 (destination location, 218 (destination vector as output vector); [0045] regarding the first and second source being vectors; [0056] regarding instructions defining locations of bits; As interpreted by the Examiner, [0056] recites the instructions defining locations of bits, and Fig. 2 shows arrows from specific individual elements from the first source (212A), and the second source (212B), to the execution circuit (214), and from the execution circuit to the specific location in the destination vector (218)).
With regards to claim 5, Heinecke teaches the accelerator circuit of claim 1, as referenced above.
Heinecke further teaches:
wherein the vector circuit is further configured to: perform the respective vector operation on a first element of the first vector and a second element of the second vector (Fig. 1 117 (execution circuitry); Fig. 2 item 201 (instruction), 202 (opcode), 206 (first source location from reg/mem), 208 (second source location from reg/mem), 212A (first source), 212B (second source), 214 (execution circuitry); [0045] regarding the first and second source being vectors; [0046] regarding the opcode from the instruction set indicating operations for the execution circuitry to perform on the first vector data and second vector data);
to generate an output element of the output vector, (Fig. 2 item 204 (destination location), 214 (execution circuitry), 218 (destination vector as an output vector); [0037] regarding the instruction performing operations on two source inputs and outputting the result to a destination vector);
wherein each instruction in the subset indicates a position in the first vector for the first element, a position in the second vector for the second element, and a position in the output vector for the output element. (Fig. 2 item 201 (instruction), 206 (first source location), 208 (second source location), 212A (first source), 212B (second source), 204 (destination location), 218 (destination vector as output vector); [0045] regarding the first and second source being vectors; [0056] regarding instructions defining locations of bits; As interpreted by the Examiner, [0056] recites the instructions defining locations of bits, and Fig. 2 shows arrows from specific individual elements from the first source (212A), and the second source (212B), to the execution circuit (214), and from the execution circuit to the specific location in the destination vector (218)).
With regards to claim 6, Heinecke teaches the accelerator circuit of claim 1, as referenced above.
wherein the vector circuit is further configured to receive the at least one first element (Fig. 2 item 212A (first source));
and the at least one second element (Fig. 2 item 212B (second source));
from the data memory at a vector register file of the vector circuit in accordance with each instruction in the subset. (Fig. 1 item 115 (register file/memory); Fig. 2 item 201 (instruction), 206 (first source location from reg/mem), 208 (second source location from reg/mem), 212A (first source), 212B (second source)).
With regards to claim 7, Heinecke teaches the accelerator circuit of claim 6, as referenced above.
Heinecke further teaches:
wherein the vector circuit is further configured to store the least one output element in the vector register file in accordance with each instruction in the subset for further use by the vector circuit. (Fig. 1 item 119 (write back circuit), 115 (register file/memory); Fig. 2 item 201 (instruction), 204 (destination location, 218 (destination vector as output vector); [0045] regarding the destination (output) being a vector; [0044] regarding the writeback circuit writing the results of the execution).
With regards to claim 10, Heinecke teaches the accelerator circuit of claim 1, as referenced above.
Heinecke further teaches:
wherein the accelerator circuit is integrated into an image signal processor circuit or a neural processor circuit. ([0161] regarding inclusion of an image processor with the circuit).
With regards to claim 11, Heinecke teaches:
A method of operating an accelerator circuit, (Fig. 1);
comprising: storing a plurality of instructions in an instruction memory of the accelerator circuit; (Fig. 1 item 101 (storage); [0042] regarding instructions fetched from storage (101) (as memory));
receiving, by an align and dispatch circuit and from the instruction memory, an instruction packet comprising multiple instructions stored in a same address in the instruction memory; (Fig. 1 items 109 (Decode circuitry), 113 (register rename/scheduling circuit) and the multiple outputs from the scheduling circuit based on the single instruction; [0042] regarding the decode circuitry taking the instructions and generating it into one or more operations);
dispatching, by the align and dispatch circuit, a first instruction to a sequencer circuit, a second instruction to a scalar circuit, a third instruction to a load and store circuit, or a fourth instruction to a vector circuit; (Fig. 1 items 109 (decode circuitry), 113(scheduling circuit) output to the execution circuitry, as a fourth instruction);
reading at least a subset of the instructions of the instruction packet from the align and dispatch circuit that is to receive the instruction packet from the instruction memory by the vector circuit of the accelerator circuit coupled to the instruction memory, (Fig. 1 items 101 (storage), 105 (fetch), 109 (decode), 113 (scheduling circuit), 117 (Execution circuitry); Fig. 2; [0046] regarding fetch and decode circuitry to read instructions; [0042] regarding the decode circuitry taking the instructions and generating it into one or more operations);
each instruction in the at least the subset of the instructions is to include a first identification of at least a portion of a first vector and a second identification of at least a portion of a second vector; (Fig. 2 item 201 (instruction), 206 (first source location), 208 (second source location), 212A (first source), 212B (second source); [0045] regarding the first and second source being vectors);
receiving, at the vector circuit, at least a portion of the input data from a data memory of the accelerator circuit, (Fig. 1 item 115 (register file/memory), 117 (execution circuitry); Fig. 2 item 201 (instruction), 206 (first source location from reg/mem), 208 (second source location from reg/mem), 212A (first source), 212B (second source); [0045] regarding the first and second source being vectors; [0046] regarding the instruction containing first source data and second source data);
the portion of input data corresponds to the at least the subset of the instructions; (Fig. 1 item 115 (register file/memory), 117 (execution circuitry); Fig. 2 item 201 (instruction), 206 (first source location from reg/mem), 208 (second source location from reg/mem), 212A (first source), 212B (second source); [0045] regarding the first and second source being vectors; [0046] regarding the instruction containing first source data and second source data);
and performing, by the vector circuit, a respective vector operation in accordance with each instruction in the subset (Fig. 1 117 (execution circuitry); Fig. 2 item 201 (instruction), 202 (opcode), 206 (first source location from reg/mem), 208 (second source location from reg/mem), 212A (first source), 212B (second source), 214 (execution circuitry); [0045] regarding the first and second source being vectors; [0046] regarding the opcode from the instruction set indicating operations for the execution circuitry to perform on the first vector data and second vector data);
on at least one first element of the first vector and at least one second element of the second vector from the received portion of input data to generate at least one output element of an output vector, (Fig. 1 117 (execution circuitry); Fig. 2 item 201 (instruction), 202 (opcode), 206 (first source location from reg/mem), 208 (second source location from reg/mem), 212A (first source), 212B (second source), 214 (execution circuitry), item 204 (destination location), 218 (destination vector as an output vector); [0045] regarding the first and second source being vectors; [0046] regarding the opcode from the instruction set indicating operations for the execution circuitry to perform on the first vector data and second vector data; [0037] regarding the instruction performing operations on two source inputs and outputting the result to a destination vector; [0056] regarding instructions defining locations of bits; As interpreted by the Examiner, [0056] recites the instructions defining locations of bits, and Fig. 2 shows arrows from specific individual elements from the first source (212A), and the second source (212B), to the execution circuit (214), and from the execution circuit to the specific location in the destination vector (218));
each instruction in the subset is to indicate positions in respective vectors for (i) the at least one first element, (ii) the at least one second element, and (iii) the at least one output element. (Fig. 2
item 201 (instruction), 206 (first source location), 208 (second source location), 212A (first source), 212B (second source), 204 (destination location), 218 (destination vector as output vector); [0045] regarding the first and second source being vectors; [0056] regarding instructions defining locations of bits; As interpreted by the Examiner, [0056] recites the instructions defining locations of bits, and Fig. 2 shows arrows from specific individual elements from the first source (212A), and the second source (212B), to the execution circuit (214), and from the execution circuit to the specific location in the destination vector (218)).
With regards to claim 12, Heinecke teaches the method of claim 11, as referenced above.
Heinecke further teaches:
wherein each instruction in the subset indicates at least one position in the first vector for the at least one first element, at least one position in the second vector for the at least one second element, and least one position in the output vector for the at least one output element. (Fig. 2 item 201 (instruction), 206 (first source location), 208 (second source location), 212A (first source), 212B (second source), 204 (destination location), 218 (destination vector as output vector); [0045] regarding the first and second source being vectors; [0056] regarding instructions defining locations of bits; As interpreted by the Examiner, [0056] recites the instructions defining locations of bits, and Fig. 2 shows arrows from specific individual elements from the first source (212A), and the second source (212B), to the execution circuit (214), and from the execution circuit to the specific location in the destination vector (218)).
With regards to claim 13, Heinecke teaches the method of claim 11, as referenced above.
Heinecke further teaches:
further comprising: performing, by the vector circuit, (Fig. 2);
the respective vector operation on a first plurality of elements of the first vector and a second plurality of elements of the second vector to generate a plurality of output elements of the output vector, (Fig. 1 117 (execution circuitry); Fig. 2 item 201 (instruction), 202 (opcode), 206 (first source location from reg/mem), 208 (second source location from reg/mem), 212A (first source), 212B (second source), 214 (execution circuitry), as noted by the Examiner, fig. 2 indicates multiple elements from the first and second vectors used in computations in the execution circuitry, and output as a destination vector (made up of a plurality of elements); [0045] regarding the first and second source being vectors; [0046] regarding the opcode from the instruction set indicating operations for the execution circuitry to perform on the first vector data and second vector data);
wherein each instruction in the subset indicates a plurality of positions in the first vector for the first plurality of elements, a plurality of positions in the second vector for the second plurality of elements, and a plurality of positions in the output vector for the plurality of output elements. (Fig. 2 item 201 (instruction), 206 (first source location), 208 (second source location), 212A (first source), 212B (second source), 204 (destination location), 218 (destination vector as output vector); [0045] regarding the first and second source being vectors; [0056] regarding instructions defining locations of bits; As interpreted by the Examiner, [0056] recites the instructions defining locations of bits, and Fig. 2 shows arrows from specific individual elements from the first source (212A), and the second source (212B), to the execution circuit (214), and from the execution circuit to the specific location in the destination vector (218)).
With regards to claim 14, Heinecke teaches the method of claim 11, as referenced above.
Heinecke further teaches:
further comprising: performing, by the vector circuit, the respective vector operation on a first plurality of elements of the first vector and a second element of the second vector (Fig. 1 item 117 (execution circuitry); Fig. 2 item 201 (instruction), 202 (opcode), 206 (first source location from reg/mem), 208 (second source location from reg/mem), 212A (first source), 212B (second source), 214 (execution circuitry); [0045] regarding the first and second source being vectors; [0046] regarding the opcode from the instruction set indicating operations for the execution circuitry to perform on the first vector data and second vector data);
to generate a plurality of output elements of the output vector, (Fig. 2 item 204 (destination location), 214 (execution circuitry), 218 (destination vector as an output vector); [0037] regarding the instruction performing operations on two source inputs and outputting the result to a destination vector);
wherein each instruction in the subset indicates a plurality of positions in the first vector for the first plurality of elements, a position in the second vector for the second element, and a plurality of positions in the output vector for the plurality of output elements. (Fig. 2 item 201 (instruction), 206 (first source location), 208 (second source location), 212A (first source), 212B (second source), 204 (destination location), 218 (destination vector as output vector); [0045] regarding the first and second source being vectors; [0056] regarding instructions defining locations of bits; As interpreted by the Examiner, [0056] recites the instructions defining locations of bits, and Fig. 2 shows arrows from specific individual elements from the first source (212A), and the second source (212B), to the execution circuit (214), and from the execution circuit to the specific location in the destination vector (218)).
With regards to claim 15, Heinecke teaches the method of claim 11, as referenced above.
Heinecke further teaches:
further comprising: performing, by the vector circuit, (Fig. 2);
the respective vector operation on a first element of the first vector and a second element of the second vector to generate an output element of the output vector, (Fig. 1 117 (execution circuitry); Fig. 2 item 201 (instruction), 202 (opcode), 206 (first source location from reg/mem), 208 (second source location from reg/mem), 212A (first source), 212B (second source), 214 (execution circuitry), as noted by the Examiner, fig. 2 indicates multiple elements from the first and second vectors used in computations in the execution circuitry, and output as a destination vector (made up of a plurality of elements); [0045] regarding the first and second source being vectors; [0046] regarding the opcode from the instruction set indicating operations for the execution circuitry to perform on the first vector data and second vector data);
wherein each instruction in the subset indicates a position in the first vector for the first element, a position in the second vector for the second element, and a position in the output vector for the output element. (Fig. 2 item 201 (instruction), 206 (first source location), 208 (second source location), 212A (first source), 212B (second source), 204 (destination location), 218 (destination vector as output vector); [0045] regarding the first and second source being vectors; [0056] regarding instructions defining locations of bits; As interpreted by the Examiner, [0056] recites the instructions defining locations of bits, and Fig. 2 shows arrows from specific individual elements from the first source (212A), and the second source (212B), to the execution circuit (214), and from the execution circuit to the specific location in the destination vector (218)).
With regards to claim 16, Heinecke teaches the method of claim 11, as referenced above.
Heinecke further teaches:
further comprising: receiving the at least one first element and the at least one second element from the data memory at a vector register file of the vector circuit in accordance with each instruction in the subset. (Fig. 1 item 115 (register file/memory); Fig. 2 item 212A (first source), item 212B (second source) item 201 (instruction), 206 (first source location from reg/mem), 208 (second source location from reg/mem)).
With regards to claim 17, Heinecke teaches the method of claim 16, as referenced above.
Heinecke further teaches:
further comprising: storing the least one output element into the vector register file in accordance with each instruction in the subset for further use by the vector circuit. (Fig. 1 item 119 (write back circuit), 115 (register file/memory); Fig. 2 item 201 (instruction), 204 (destination location, 218 (destination vector as output vector); [0045] regarding the destination (output) being a vector; [0044] regarding the writeback circuit writing the results of the execution).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8, 9, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Heinecke.
With regards to claim 8, Heinecke teaches the accelerator circuit of claim 6, as referenced above.
Heinecke further teaches:
further comprising a buffer circuit coupled to the data memory, (Fig. 9 item 972 (Data TLB unit), item 958 (physical register units));
and the vector circuit is further configured to store the least one output element in the circuit in accordance with each instruction in the subset. (Fig. 1 item 119 (write back circuit), 115 (register file/memory); Fig. 2 item 201 (instruction), 204 (destination location, 218 (destination vector as output vector); [0045] regarding the destination (output) being a vector; [0044] regarding the writeback circuit writing the results of the execution).
Heinecke does not explicitly teach:
store the least one output element in the buffer circuit
However, Heinecke does teach the instruction indicating the destination location (as output location) as seen in Fig. 2 item 201 (instruction), 204 (destination location, 218 (destination vector as output vector). Furthermore, [0044] teaches a writeback circuit writing the results of the execution circuit (as an output), with Fig. 1 showing the write back circuit write to the register file/memory (115). Furthermore, Fig. 9B shows a buffer, Data TLB unit, bidirectionally connected to the memory access units (964), which is connected to the execution circuits. [0132] states that the memory access unit includes a load unit, a store address unit, and a store data unit, and that it is coupled to the data TLB unit (972) in the memory unit (970). Furthermore, [0133] states that the physical register files (958), and memory unit (970) perform the register read/memory read stage, as well as the write back/memory write stage. As interpreted by the examiner, in view of the figures and paragraphs mentioned above, the memory access unit (964) which loads, and stores data to/from the execution clusters (960), is connected, bi-directionally, to Data TLB unit (972) (as a buffer), and thus when the write back process of writing the output from the execution stage occurs, it would write the data to the bi-directionally connected Data TLB unit (972) (as a buffer).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the teachings of Heinecke with the suggested teachings of a Data TLB unit (as a buffer) to store input/output data to/from the execution circuit, because there are some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention. [MPEP 2141(III)(G)].
With regards to claim 9, Heinecke teaches the accelerator circuit of claim 7, as referenced above.
Heinecke further teaches:
further comprising the load and store circuit to include the buffer circuit, (Fig. 9 item 972 (Data TLB unit), 964 (memory access units); [0132] regarding the memory access unit coupled to the data TLB unit, and including a load unit, a store address unit, and a store data unit);
the load and store circuit configured to store the least one output element from the circuit in the data memory. (Fig. 1 item 119 (write back circuit), 115 (register file/memory); Fig. 2 item 201 (instruction), 204 (destination location, 218 (destination vector as output vector); [0045] regarding the destination (output) being a vector; [0044] regarding the writeback circuit writing the results of the execution)).
Heinecke does not explicitly teach:
store the least one output element from the buffer circuit in the data memory
However, Heinecke does teach the instruction indicating the destination location (as output location) as seen in Fig. 2 item 201 (instruction), 204 (destination location, 218 (destination vector as output vector). Furthermore, [0044] teaches a writeback circuit writing the results of the execution circuit (as an output), with Fig. 1 showing the write back circuit write to the register file/memory (115). Furthermore, Fig. 9B shows a buffer, Data TLB unit, bidirectionally connected to the memory access units (964), which is connected to the execution circuits. [0132] states that the memory access unit includes a load unit, a store address unit, and a store data unit, and that it is coupled to the data TLB unit (972) in the memory unit (970). Furthermore, [0133] states that the physical register files (958), and memory unit (970) perform the register read/memory read stage, as well as the write back/memory write stage. As interpreted by the examiner, in view of the figures and paragraphs mentioned above, the memory access unit (964) which loads, and stores data to/from the execution clusters (960), is connected, bi-directionally, to Data TLB unit (972) (as a buffer), and thus when the write back process of writing the output from the execution stage occurs, it would write the data to the bi-directionally connected Data TLB unit (972) (as a buffer), before storing on the memory unit (970).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the teachings of Heinecke with the suggested teachings of a Data TLB unit (as a buffer) to store input/output data to/from the execution circuit, because there are some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention. [MPEP 2141(III)(G)].
With regards to claim 18, Heinecke teaches:
An electronic device, (Fig. 1);
comprising: a memory to store input data; ([0040] regarding source vectors located in memory (as data memory); Fig. 1 item 115 (register file/memory); Fig. 2 items 204, 206, 208 regarding location of a first, and second source, and output (destination) in reg/mem);
and an accelerator circuit coupled to the system memory, (Fig. 9B item 950 (execution engine unit), 970 (memory unit), 976 (L2 cache unit); [0132] regarding the memory unit's L2 cache unit coupled to main memory);
the accelerator circuit including: a vector circuit, a data memory configured to receive and store the input data, ([0040] regarding source vectors located in memory (as data memory); Fig. 1 item 115 (register file/memory); Fig. 2 items 204, 206, 208 regarding location of a first, and second source, and output (destination) in reg/mem; Fig. 9B items 970 (memory unit), 964 (memory access units); [0132] regarding memory unit connected to main memory, and memory access units coupled to the memory unit, with the memory access units including a load unit, a store address unit, and a store data unit);
an instruction memory to store a plurality of instructions, (Fig. 1 item 101 (storage); [0042] regarding instructions fetched from storage (101) (as memory));
an align and dispatch circuitry configured to: receive from the instruction memory an instruction packet comprising multiple instructions stored in a same address in the instruction memory; (Fig. 1 items 109 (Decode circuitry), 113 (register rename/scheduling circuit) and the multiple outputs from the scheduling circuit based on the single instruction; [0042] regarding the decode circuitry taking the instructions and generating it into one or more operations);
and dispatch a first instruction to a sequencer circuit, a second instruction to a scalar circuit, a third instruction to a load and store circuit, or a fourth instruction to the vector circuit; (Fig. 1 items 109 (decode circuitry), 113(scheduling circuit) output to the execution circuitry);
wherein the vector circuit is coupled to the instruction memory and the data memory, (Fig. 1 items 101 (storage), 115 (register file/memory), 117 (execution circuitry); Fig. 2 items 204, 206, 208 regarding location of a first, and second source, and output (destination) in reg/mem);
the vector circuit configured to: read at least a subset of the instructions of the instruction packet from the align and dispatch circuit that receives the instruction packet from the instruction memory, (Fig. 1 items 101 (storage), 105 (fetch), 109 (decode), 113 (scheduling circuit), 117 (Execution circuitry); Fig. 2; [0046] regarding fetch and decode circuitry to read instructions; [0042] regarding the decode circuitry taking the instructions and generating it into one or more operations);
each instruction in the at least the subset of the instructions to include a first identification of at least a portion of a first vector and a second identification of at least a portion of a second vector, (Fig. 2 item 201 (instruction), 206 (first source location), 208 (second source location), 212A (first source), 212B (second source); [0045] regarding the first and second source being vectors);
decode each instruction in the at least the subset of the instructions; (Fig. 2; [0045]-[0046] regarding that the apparatus of fig. 2 (which is of the execution circuitry), decodes instructions which have fields to specify opcode, first and second source locations, and destination vectors);
receive at least a portion of the input data from the data memory that corresponds to the at least the subset of the instructions, (Fig. 1 item 115 (register file/memory), 117 (execution circuitry); Fig. 2 item 201 (instruction), 206 (first source location from reg/mem), 208 (second source location from reg/mem), 212A (first source), 212B (second source); [0045] regarding the first and second source being vectors; [0046] regarding the instruction containing first source data and second source data);
and perform a respective vector operation in accordance with each instruction in the subset on at least one first element of the first vector and at least one second element of the second vector from the received portion of input data (Fig. 1 117 (execution circuitry); Fig. 2 item 201 (instruction), 202 (opcode), 206 (first source location from reg/mem), 208 (second source location from reg/mem), 212A (first source), 212B (second source), 214 (execution circuitry); [0045] regarding the first and second source being vectors; [0046] regarding the opcode from the instruction set indicating operations for the execution circuitry to perform on the first vector data and second vector data);
to generate at least one output element of an output vector, (Fig. 2 item 204 (destination location), 214 (execution circuitry), 218 (destination vector as an output vector); [0037] regarding the instruction performing operations on two source inputs and outputting the result to a destination vector);
each instruction in the subset to indicate positions in respective vectors for (i) the at least one first element, (ii) the at least one second element, and (iii) the at least one output element. (Fig. 2 item 201 (instruction), 206 (first source location), 208 (second source location), 212A (first source), 212B (second source), 204 (destination location, 218 (destination vector as output vector); [0045] regarding the first and second source being vectors).
Heinecke does not explicitly teach:
system memory storing input data
input data from the system memory
However, Heinecke teaches, in reference to Figure 9B, [0132] the memory unit's (970) L2 cache unit (976) coupled to main memory (as system memory). Figure 9B further shows L2 cache unit (976) coupled to Data Cache Unit (974), which is part of memory unit (970), and coupled to Data TLB unit (972) which is also stated in [0132] that the data TBL unit (972) and data cache unit (974) are coupled together. Furthermore, Figure 9B shows Data TLB unit (972) bi-directionally coupled to memory access unit (964), which [0132] recites as well. [0132] also states that the memory access unit (964) includes a load unit, a store address unit, and a store data unit. Furthermore, [0133] states that memory unit (970) performs the memory read stage, and memory write stage. As interpreted by the Examiner, the main memory would be what stores and sends the input data to the memory unit (970) that is coupled to the main memory through the L2 Cache unit (976), this is further shown by the memory access unit (964) which is coupled to the memory unit (970) loading, and storing the input data, as well as [0133] reciting that memory unit (970) performs the memory read stage, which indicates that it reads the data from the main memory to which it is coupled through L2 cache unit (976).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the teachings of Heinecke with the suggested teachings of a Data TLB unit (as a buffer) to store input/output data to/from the execution circuit, because there are some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention. [MPEP 2141(III)(G)].
With regards to claim 19, Heinecke teaches the electronic device of claim 18, as referenced above.
Heinecke further teaches:
wherein each instruction in the subset indicates at least one position in the first vector for the at least one first element, at least one position in the second vector for the at least one second element, and least one position in the output vector for the at least one output element. (Fig. 2 item 201 (instruction), 206 (first source location), 208 (second source location), 212A (first source), 212B (second source), 204 (destination location), 218 (destination vector as output vector); [0045] regarding the first and second source being vectors; [0056] regarding instructions defining locations of bits; As interpreted by the Examiner, [0056] recites the instructions defining locations of bits, and Fig. 2 shows arrows from specific individual elements from the first source (212A), and the second source (212B), to the execution circuit (214), and from the execution circuit to the specific location in the destination vector (218)).
With regards to claim 20, Heinecke teaches the electronic device of claim 18, as referenced above.
Heinecke further teaches:
wherein the vector circuit is further configured to: perform the respective vector operation on a first plurality of elements of the first vector and a second element of the second vector to generate a plurality of output elements of the output vector, (Fig. 1 item 117 (execution circuitry); Fig. 2 item 201 (instruction), 202 (opcode), 206 (first source location from reg/mem), 208 (second source location from reg/mem), 212A (first source), 212B (second source), 214 (execution circuitry), 204 (destination location, 218 (destination vector as output vector); [0045] regarding the first and second source being vectors; [0046] regarding the opcode from the instruction set indicating operations for the execution circuitry to perform on the first vector data and second vector data);
wherein each instruction in the subset indicates a plurality of positions in the first vector for the first plurality of elements, a position in the second vector for the second element, and a plurality of positions in the output vector for the plurality of output elements. (Fig. 2 item 201 (instruction), 206 (first source location), 208 (second source location), 212A (first source), 212B (second source), 204 (destination location), 218 (destination vector as output vector); [0045] regarding the first and second source being vectors; [0056] regarding instructions defining locations of bits; As interpreted by the Examiner, [0056] recites the instructions defining locations of bits, and Fig. 2 shows arrows from specific individual elements from the first source (212A), and the second source (212B), to the execution circuit (214), and from the execution circuit to the specific location in the destination vector (218)).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.A.K./ Examiner, Art Unit 2182 /EMILY E LAROCQUE/ Primary Examiner, Art Unit 2182