DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is non-final and is in response to the claims filed December 17th, 2025. Claims 1-20 are pending, of which claims 1-20 are currently rejected.
Response to Arguments
The claims filed December 17th, 2025 have been entered. Claims 1-20 remain pending in the application. Applicant’s amendments to the Claims have overcome each and every 112(b) rejection, previously set forth in the Office Action mailed October 28th, 2025.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on December 17th, 2025 has been entered.
Claim Rejections – 35 USC § 112
Applicant has amended claims and resolved the antecedent basis and lack of clarity issues. Therefore, the previous rejections of claims 1-20 under 35 U.S.C. 112(b) have been withdrawn.
Prior Art Rejections
Applicant’s arguments regarding the previously cited art have been fully considered and are not persuasive.
Applicant alleges that Haddad in view of Breiner does not teach an inverter to provide the output of the first NOR gate as the inverted signal to both and top and lower AND gate. Specifically, Applicant makes reference to the figure of Breiner’s D-Latch and alleges that Breiner does not disclose the inverter to provide the inverted signal from the first NOR gate to both the top and lower AND gate (Applicant Remarks Pgs. 15-16). Examiner respectfully disagrees. With respect to the inverter that provides the inverted signal of the first NOR gate to the top and lower AND gates (first and second AND gates), Haddad is relied upon to teach this limitation. Examiner wishes to clarify the combination of the Haddad in view of Breiner. Below is Fig. 5 of Haddad:
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The entire latch of Breiner as visualized below would replace the latch 52 of Fig. 5 of Haddad (the latch of Breiner would take the place of the latch of Haddad as indicated in the bolded box above).
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Examiner wishes to point out that the inverter 56 of Haddad at output of latch 52 port Q and input of latch 52 port D is the inverter that is mapped to for inputting the inverted signal of the first NOR gate (bottom NOR gate of Breiner’s latch) to both the first and second AND gates. In having Breiner replace the latch 52 of Haddad, the first NOR gate would output at port Q, go through the inverter 56, and be input to the latch once more at port D. As can be seen in the Breiner latch the input would be provided through port D and from there be provided to both the first and second AND gates. Therefore, Haddad in view of Breiner does in fact teach the inverter for providing the output of the first NOR gate to the first and second AND gates.
See Claim Rejections - 35 USC § 103.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-10 and 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Haddad et al. (US 2016/0004510 A1) (hereinafter “Haddad”), in view of A. Breiner (“Penguin celebrates win over professor”, 2019, from: https://slideplayer.com/slide/14404695) (hereinafter “Breiner”), in view of A. Ardakani et al. (“Improving performance of FPGA-based SR-Latch PUF using Transient Effect Ring Oscillator and Programmable Delay Lines”, 2018) (hereinafter “Ardakani”), in view of ”), further in view of Zalivaka et al. (“Design and Implementation of High-Quality Physical Unclonable Functions for Hardware-Oriented Cryptography”, 2016) included in the IDS filed on 02/18/2022 (hereinafter “Zalivaka”).
Regarding claim 1, Haddad teaches:
A latching circuit comprising:
a latch including (Haddad: Fig. 5 Element 52 latch) a first input port (Haddad: first input port being enable input port CLK), a second input port (Haddad: D input as second input port), and an output port (Haddad: Q output port of latch 52), the latch configured to receive an enable signal at the first input port (Haddad: enable CLK at first input port of latch 52); and
an inverter coupled to the latch (Haddad: inverter 56 coupled to latch 52), configured to generate an inverted signal of data output from the latch (Haddad: inverter 56 takes output Q, inverts the data output), and configured to provide the inverted signal back to the second input port (Haddad: inverted data output from inverter 56 taken back to second input port D of latch 52).
While Haddad teaches the inverter coupled to the latch (Haddad: inverter 56 coupled to latch 52, inverter taking output Q to generate an inverted data output) Haddad does not explicitly teach the internal structure of the latch or the various modes of functionalities of the latches based on an enable signal.
However, Breiner teaches:
wherein the latch comprises:
a first NOR gate and a second NOR gate coupled together in series (Breiner: Slide 17 the bottom NOR gate is the first NOR gate, and the top NOR gate is the second NOR gate; the gated D-latch comprising a set-reset latch with 2 NOR gates, each correspondingly receiving a set or reset input, the first NOR gate receiving the set input and the second NOR gate receiving the reset input, and the output of the second NOR gate being output, which is what goes through the inverter of Haddad’s latch; Slide 17 gated D-latch takes as inputs D, Strobe which corresponds to CLK of Haddad’s latch, and has as outputs Q, which corresponds to the output port D of Haddad’s latch; the first NOR gate provides an input to the second NOR gate and therefore is connected in series), wherein the first NOR gate has an output coupled through the inverter to provide an inverted input from the first NOR gate as the inverted signal (Breiner: Slide 17 the bottom NOR gate as the first NOR gate provides an output Q, which is provided at the output of the latch, having this internal D latch structure at the latch 52 of Haddad’s system shown in Fig. 5, there would be the inverter 56 to take the output signal and create the inverted signal, which is then provided back to the latch as an input as shown in Fig. 5 of Haddad);
a first AND gate and a second AND gate in parallel with the first AND gate, each of the first AND gate and the second AND gate receiving both a) the enable signal and b) the inverted signal (Breiner: Slide 17 2 AND gates in parallel, each receiving the inverted signal provided by Haddad’s inverter 56, and an enable signal as indicated by Strobe in Slide 17);
the first AND gate providing an output which is input to the second NOR gate (Breiner: first AND gate is the top gate, providing input to the second NOR gate), and
the second AND gate providing an output which is input to the first NOR gate (Breiner: the second AND gate is the bottom gate, providing input to the first NOR gate as discussed before).
Below is Fig. 5 of Haddad:
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In combining Breiner with Haddad, the entire latch of Breiner as visualized below would replace the latch 52 of Fig. 5 of Haddad (the latch of Breiner would take the place of the latch of Haddad as indicated in the bolded box above).
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Examiner wishes to point out that the inverter 56 of Haddad at output of latch 52 port Q and input of latch 52 port D is the inverter that is mapped to for inputting the inverted signal of the first NOR gate (bottom NOR gate of Breiner’s latch) to both the first and second AND gates. In having Breiner replace the latch 52 of Haddad, the first NOR gate would output at port Q, go through the inverter 56 of Haddad, and be input to the latch once more at port D. As can be seen in the Breiner latch the input would be provided through port D and from there be provided to both the first and second AND gates.
It would be obvious to one with ordinary skill in the art to combine to one of ordinary skill in the art to utilize the internal gating structure as taught by Breiner for the latch-inverter structure as taught in Haddad because Haddad does not teach the internal structure of the D-latch, while Breiner does disclose this internal structure. It is obvious to use a known technique to improve similar devices in the same way. See MPEP 2141(III)(c).
Haddad in view of Breiner does not explicitly teach the various modes of functionalities of the latches based on an enable signal.
However, Ardakani teaches a latch-based PUF that enters a metastable state at rising edge of the enable signal from 0 (second level) to 1 (first level) that outputs a physically unclonable random number (Ardakani: pg. 372 Col. 1 Lines 17-25).
It would be obvious to combine the latch-based PUF of Ardakani with the latch-inverter structure of Haddad in view of Breiner as all teachings are directed towards digital design with latches. Ardakani enhances the random output generation of Haddad in view of Breiner by exploiting the manufacturing variability to extract secret, unique and unpredictable information from an integrated circuit (Ardakani: Pg. 371 Section 1 Col. 1 Lines 11-13) and increasing the quality of random output and therethrough enhancing entropy (Pg. 373 Col. 1 Lines 25-29).
Haddad in view of Breiner in view of Ardakani does not explicitly teach the latches operating as a ring oscillator or a memory depending on the enable signal.
However, Zalivaka teaches the latch-based PUF acting as a ring oscillator when the enable signal is at a first level (Zalivaka: Pg. 66 Section 4.3.1 lines 3-8 first level at EN = ‘1’ triggers ring oscillator functionality RO-PUF) and acting as a memory when the enable signal is at a second level (Zalivaka: Pg. 4.3.1 Lines 6-8 explains SRAM-PUF functionality when second level EN = ‘0’ is triggered).
It would be obvious to combine the enable signal determining the memory or ring oscillator functionality as taught by Zalivaka with the latching circuit functionality as taught by Haddad in view of Breiner in view of Ardakani as all teachings are directed digital design with latching circuitry. The improvement of Zalivaka lies in decreasing hardware overhead by having multiple modes being functionally possible using the same latching structure (Zalivaka: Pg. 68 Section 4.3.2 Lines 1-2).
Therefore, Haddad in view of Breiner in view of Ardakani in view of Zalivaka teaches:
A latching circuit comprising:
a latch including a first input port, a second input port, and an output port, the latch configured to receive an enable signal at the first input port; and
an inverter coupled to the latch, configured to generate an inverted signal of data output from the latch, and configured to provide the inverted signal back to the second input port,
wherein the latch and the inverter operate as a memory when the enable signal has a first level, operate as a ring oscillator when the enable signal has a second level, and have a metastable state when the enable signal changes from the second level to the first level,
wherein the latch and the inverter comprise:
a first NOR gate and a second NOR gate coupled together in series, wherein the first NOR gate has an output coupled through the inverter to provide an inverted input from the first NOR gate as the inverted signal;
a first AND gate and a second AND gate in parallel with the first AND gate, each of the first AND gate and the second AND gate receiving the enable signal and the inverted signal;
the first AND gate providing an output which is input to the second NOR gate, and
the second NAND gate providing an output which is input to the first NOR gate.
Regarding claim 5, while Haddad in view of Breiner in view of Ardakani teach latches having a random output (Haddad: Fig. 5 Element 52; ¶ 0043; Ardakani: Pg. 372 Section 2.1; Pg. 372 Col. 1 Lines 17-25), Haddad in view of Breiner in view of Ardakani does not explicitly teach latches operating a ring oscillator to output a random number that is physically unclonable.
However, Zalivaka teaches:
The circuit of claim 1, wherein the latch operating as the ring oscillator outputs a random number, for the randomized data, that is physically unclonable (Zalivaka: Pg. 66 Section 4.3.1 Lines 3-8 functionality of RO-PUF and output being a random number).
The motivation to combine provided with respect to claim 1 applies equally to claim 5.
Regarding claim 6, Haddad in view of Breiner in view of Ardakani in view of Zalivaka further teaches:
The circuit of claim 1, wherein the latch operating in the metastable state outputs a random number, for the randomized data, that is physically unclonable (Ardakani: Pg. 372 Col. 1 Lines 17-25 a latch-based PUF that enters a metastable state at rising edge of the enable signal from 0 (second level) to 1 (first level) that outputs a physically unclonable random number).
The motivation to combine provided with respect to claim 1 applies equally to claim 6.
Regarding claim 7, while Haddad in view of Breiner in view of Ardakani teach a latch with a random output (Haddad: Fig. 5 Element 52; ¶ 0043; Ardakani: Pg. 372 Section 2.1; Pg. 372 Col. 1 Lines 17-25), Haddad in view of Breiner in view of Ardakani does not explicitly teach the latch operating as a memory device in order to output an identification pattern for a device identifier of the circuit.
However, Zalivaka teaches:
The circuit of claim 1, wherein the latch operating as the memory device at initialization of the circuit outputs an identification pattern serving as a device identifier of the circuit (Zalivaka: Pg. 68 Section 4.3.2 Lines 6-9 further explains in the SRAM-PUF mode of operation how the output is used to provide a chip ID i.e., an identification pattern or device identifier).
It would be obvious to combine the identification pattern generation of the memory device functionality of the latching circuitry as taught by Zalivaka with the latching functionality of Haddad in view of Breiner in view of Ardakani as all teachings are directed towards digital design of latches. The improvement of Zalivaka lies in decreasing hardware resources needed for computation and generation of random outputs (Zalivaka: Pg. 67 Lines 22-26).
Regarding claim 8, while Haddad in view of Breiner in view of Ardakani in view of Zalivaka further teaches:
The circuit of claim 1, wherein the latch comprises a set-reset latch having a first NOR gate, a second NOR gate, a set input for the first NOR gate, a reset input for the second NOR gate, a first data output of the first NOR gate coupled to the second NOR gate, and a second data output of the first NOR gate provided to the inverter (Breiner: Slide 17 the gated D-latch comprising a set-reset latch with 2 NOR gates, each correspondingly receiving a set or reset input, the first NOR gate receiving the set input and the second NOR gate receiving the reset input, and the output of the second NOR gate being output, which is what goes through the inverter of Haddad’s latch; Slide 17 gated D-latch takes as inputs D, Strobe which corresponds to CLK of Haddad’s latch, and has as outputs Q, which corresponds to the output port D of Haddad’s latch).
The motivation with respect to claim 1 applies equally to claim 8.
Regarding claim 9, Haddad in view of Breiner in view of Ardakani in view of Zalivaka further teaches the circuit of claim 8 and additionally a first AND gate and second AND gate coupled to the set input and reset input respectively of the SR-latch (Breiner: Slide 17).
The motivation to combine with respect to claim 1 applies equally to claim 9.
Regarding claim 10, Haddad in view of Breiner in view of Ardakani in view of Zalivaka further teaches the circuit of claim 9 and additionally the inverter of Haddad receiving the second NOR gate’s second data output, inverting the second data output, and providing it to the input of the latch, which shown in Breiner would be input to both AND gates as shown (Breiner: having Breiner’s D latch structure as shown in Slide 17 as the D-latch 52 of Haddad shown in Fig. 5 would result in output Q going through the inverter 56).
The motivation to combine with respect to claim 1 equally applies to claim 10.
Regarding claim 12, while Haddad in view of Breiner teaches the method of claim 11, Haddad in view of Breiner does not explicitly teach the latch and inverter operating as a memory or ring oscillator depending on the enable signal, or entering a metastable state when the enable signal changes.
However, Ardakani teaches a latch-based PUF that enters a metastable state at rising edge of the enable signal from 0 (second level) to 1 (first level) that outputs a physically unclonable random number (Ardakani: pg. 372 Col. 1 Lines 17-25).
The motivation to combine with respect to claim 1 applies equally to claim 12.
Haddad in view of Ardakani does not explicitly teach the latches operating as a ring oscillator or a memory depending on the enable signal.
However, Zalivaka teaches the latch-based PUF acting as a ring oscillator when the enable signal is at a first level (Zalivaka: Pg. 66 Section 4.3.1 lines 3-8 first level at EN = ‘1’ triggers ring oscillator functionality RO-PUF) and acting as a memory when the enable signal is at a second level (Zalivaka: Pg. 4.3.1 Lines 6-8 explains SRAM-PUF functionality when second level EN = ‘0’ is triggered).
The motivation to combine with respect to claim 1 applies equally to claim 12.
Therefore, Haddad in view of Breiner in view of Ardakani in view of Zalivaka teaches:
The method of claim 11, wherein the latch and inverter operate as a memory when the enable signal has a first level, operate as a ring oscillator when the enable signal has a second level, and have a metastable state when the enable signal changes from the second level to the first level.
Regarding claim 13, Haddad in view of Breiner in view of Ardakani in view of Zalivaka teaches the method of claim 12 and additionally teaches the latch providing a random number output while operating as a ring oscillator (Zalivaka: Pg. 66 Section 4.3.1 Lines 3-8 functionality of RO-PUF and output being a random number) or in the metastable state (Ardakani: Pg. 372 Col. 1 Lines 17-25 a latch-based PUF that enters a metastable state at rising edge of the enable signal from 0 (second level) to 1 (first level) that outputs a physically unclonable random number).
The motivations to combine with respect to claim 1 applies equally to claim 13.
Regarding claim 14, Haddad in view of Breiner in view of Ardakani in view of Zalivaka further teaches:
The method of claim 13, wherein the random number output comprises a physically unclonable random number (Zalivaka: Pg. 66 Section 4.3.1 Lines 6-8; Pg. 68 Section 4.3.2 Lines 69 random sequences from IDs are random numbers as further described in Pg. 69 Lines 13-15; Pg. 67 Lines 20-21).
It would be obvious to combine the physically unclonable random number sequences as taught by Zalivaka with the latching functionality of Haddad in view of Breiner in view of Ardakani as all teachings are directed towards digital design of latching circuitry. The improvement of Zalivaka lies in producing non-reproducible results thus increasing the security and entropy of the circuit as a whole (Zalivaka: Pg. 67 Lines 22-26) and having enhanced security against prediction attacks (Zalivaka: Pg.73 Lines 6-7).
Claim 15 is directed to the method practiced by the circuit of claim 7 and is therefore rejected for the same reasons therein.
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Haddad in view of Breiner in view of Ardakani in view of Zalivaka, further in view of How (9385717) (hereinafter “How”).
Regarding claim 2, while Haddad in view of Breiner in view of Ardakani in view Zalivaka teaches the circuit of claim 1, Haddad in view of Breiner in view of Ardakani in view of Zalivaka does not explicitly teach a controller configured to provide the enable signal to the latch.
However, How teaches a controller configured to provide the enable signal to the latch (Fig. 1 shows controllers providing an enable signal to each of the latches). Based on this controller’s enable input to the latch, the mode of latch functionality will be determined to operate as a ring oscillator or memory as taught by Zalivaka.
It would be obvious to combine a controller for providing an enable signal to a latch as taught by How with the latch circuit as taught by Haddad in view of Breiner in view of Ardakani in view of Zalivaka as all teachings are directed towards latching circuitry. The enhancement of How lies in accounting for the states of the latches in order to determine the enable signal to be sent to the latching circuitry (How: Col. 3 Lines 37-39).
Regarding claim 3, Haddad in view of Breiner in view of Ardakani in view Zalivaka in view of How further teaches the controller providing the enable signal at one of the first level and the second level (Col. 3 Lines 24-26 a clocking signal is providing, that only provides 0 or 1 bits).
The motivation to combine with respect to claim 2 equally applies to claim 3.
Regarding claim 4, Haddad in view of Breiner in view of Ardakani in view Zalivaka in view of How further teaches the controller configured to change the enable signal from first level to the second level, and from the second level to the first level (How: Col. 4 Lines 48-53 the clocking signal that provides 0’s and 1’s or the second and first levels as enable signals respectively is changed periodically by the controller).
The motivation to combine with respect to claim 2 equally applies to claim 4.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Haddad in view of Breiner.
Haddad teaches:
A method for providing an unclonable output from a circuit, comprising:
receiving an enable signal at a first port of a latch (Fig. 5 shows a latch 52 with enable signal at first port CLK);
receiving a data input signal at a second port of the latch (Fig. 5 latch 52 has an input signal at second port D);
generating via an inverter coupled to the latch an inversion of the signal of output data from the latch (Fig. 5 element 52 has at output port Q an inverter 56 taking output data from the port producing an inversion signal of the output data);
feeding the inversion of the signal to the second port (Fig. 5 latch 52 has inverted signal from inverter 56 inputted into latch once more via second port D); and
operating the latch and the inverter to provide the unclonable output (Fig. 5 latch 52 output at RNBIT; ¶ 0043 output is based on metastability of oscillations in the circuit and so is physically unclonable).
Haddad does not explicitly teach the internal structure of the latch.
However, Breiner teaches:
wherein the latch comprises:
a first NOR gate and a second NOR gate coupled together in series (Breiner: Slide 17 the bottom NOR gate is the first NOR gate, and the top NOR gate is the second NOR gate; the gated D-latch comprising a set-reset latch with 2 NOR gates, each correspondingly receiving a set or reset input, the first NOR gate receiving the set input and the second NOR gate receiving the reset input, and the output of the second NOR gate being output, which is what goes through the inverter of Haddad’s latch; Slide 17 gated D-latch takes as inputs D, Strobe which corresponds to CLK of Haddad’s latch, and has as outputs Q, which corresponds to the output port D of Haddad’s latch; the first NOR gate provides an input to the second NOR gate and therefore is connected in series), wherein the first NOR gate has an output coupled through the inverter to provide an inverted input from the first NOR gate as the inverted signal (Breiner: Slide 17 the bottom NOR gate as the first NOR gate provides an output Q, which is provided at the output of the latch, having this internal D latch structure at the latch 52 of Haddad’s system shown in Fig. 5, there would be the inverter 56 to take the output signal and create the inverted signal, which is then provided back to the latch as an input as shown in Fig. 5 of Haddad);
a first AND gate and a second AND gate in parallel with the first AND gate, each of the first AND gate and the second AND gate receiving both a) the enable signal and b) the inverted signal from the first NOR gate (Breiner: Slide 17 2 AND gates in parallel, each receiving the inverted signal provided by Haddad’s inverter 56, and an enable signal as indicated by Strobe in Slide 17),
the first AND gate providing an output which is input to the second NOR gate (Breiner: first AND gate is the top gate, providing input to the second NOR gate), and
the second AND gate providing an output which is input to the first NOR gate (Breiner: the second AND gate is the bottom gate, providing input to the first NOR gate as discussed before).
It would be obvious to one with ordinary skill in the art to combine to one of ordinary skill in the art to utilize the internal gating structure as taught by Breiner for the latch-inverter structure as taught in Haddad because while Haddad does not teach internal structure of the latch, Breiner does teach the internal structure of the latch. It is obvious to use a known technique to improve similar devices in the same way. See MPEP 2141(III)(c).
Haddad in view of Breiner therefore teaches:
A method for providing an unclonable output from a circuit, comprising:
receiving an enable signal at a first port of a latch;
receiving a data input signal at a second port of the latch;
generating via an inverter coupled to the latch an inversion of the signal of output data from the latch;
feeding the inversion of the signal to the second port; and
operating the latch and the inverter to provide the unclonable output,
wherein the latch comprises:
a first NOR gate and a second NOR gate coupled together in series, wherein the first NOR gate has an output coupled through the inverter to provide an inverted input from the first NOR gate as the inversion of the signal,
a first AND gate and a second AND gate in parallel with the first AND gate, each of the first AND gate and the second AND gate receiving both a) the enable signal and b) the inversion of the signal from the first NOR gate,
the first AND gate providing an output which is input to the second NOR gate, and
the second AND gate providing an output which is input to the first NOR gate.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Haddad in view of Breiner in view of Zalivaka further in view of Johannesson et al (US 2007/0011600 A1) (hereinafter “Johannesson”).
While Haddad in view of Breiner teaches the method of claim 11 and a plurality of latches and inverters (Haddad: Fig. 6), Haddad does not explicitly teach providing for the unclonable output a set of probabilities at initializing related to the likelihood of an individual latch-inverter combination storing a ‘0’ or ‘1’ at initialization.
However, Zalivaka teaches determining a probability of the various bits storing 1 or 0 of the various latch-inverters (Zalivaka: Pgs. 43-44 Section 2.2.1) and also discusses the probability of randomness being determined for each bit stored or output i.e., for each latch-inverter (Zalivaka: Pg. 44 Section 2.2.2).
It would be obvious to combine the probability determination of Zalivaka with the method and plurality of latches and inverters of Haddad as both teachings are directed towards latches being used for random data outputs. The enhancement of Zalivaka lies in ensuring optimum randomness from the data outputs as indicated by the probability determination (Zalivaka: Pg. 44 Section 2.2.2 Lines 2-3).
Haddad in view of Zalivaka does not explicitly teach this probability determination occurring at initialization.
However, Johannesson teaches this probability determination for each of the bits occurring at initialization (Johannesson: ¶ 0022 single bit probabilities of the output are determined at initialization).
It would be obvious to one with ordinary skill in the art to combine bit probability determination at initialization as taught by Johannesson with the random output method as taught by Haddad in view of Breiner in view of Zalivaka as all teachings are directed towards techniques for outputting random data. Johannesson improves the random output method of Haddad in view of Zalivaka by having the overall joint probabilities determined by finding the probabilities of individual bits, and so this can further aid in the determination of whether there is true randomness in the overall output (Johannesson: ¶ 0022).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Haddad in view of Breiner in view of Zalivaka further in view of Kvatinsky et al (US 2022/0020410 A1) (hereinafter “Kvatinsky”).
While Haddad in view of Breiner teaches the method of claim 11 and a plurality of latches and inverters (Haddad: Fig. 6), Haddad in view of Breiner does not explicitly teach providing for the unclonable output a set of frequencies for the individual latch-inverter when the latch-inverters are operating as ring oscillators.
However, Zalivaka teaches the latch-based PUF acting as a ring oscillator when the enable signal is at a first level (Zalivaka: Pg. 66 Section 4.3.1 lines 3-8 first level at EN = ‘1’ triggers ring oscillator functionality RO-PUF) and acting as a memory when the enable signal is at a second level (Zalivaka: Pg. 4.3.1 Lines 6-8 explains SRAM-PUF functionality when second level EN = ‘0’ is triggered).
The motivation to combine with respect to claim 1 would apply equally to claim 17.
Haddad in view of Breiner in view of Zalivaka does not teach providing for the unclonable output a set of frequencies for the individual latch-inverter.
However, Kvatinsky teaches the use of frequencies for individual latches in a ring oscillator and/or metastable state functionality in order to output a random number (Kvatinsky: ¶ 0072).
One with ordinary skill in the art would be motivated to combine the frequencies being used for random number output as taught by Kvatinsky with the ring oscillator latch structure as taught by Haddad in view of Breiner in view of Zalivaka as all teachings are directed towards digital design with latches. The improvement of Kvatinsky lies in that the variances in frequences allow for a more random output (Kvatinsky: ¶ 0072).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Haddad in view of in view of Breiner in view of Ardakani, further in view of Kvatinsky.
While Haddad in view of Breiner teaches the method of claim 11 and a plurality of latches and inverters (Haddad: Fig. 6), Haddad does not explicitly teach providing for the unclonable output a set of frequencies for the individual latch-inverter when the latch-inverters are operating in metastable states.
However, Ardakani teaches a latch-based PUF that enters a metastable state at rising edge of the enable signal from 0 (second level) to 1 (first level) that outputs a physically unclonable random number (Ardakani: pg. 372 Col. 1 Lines 17-25).
The motivation to combine with respect to claim 1 applies equally to claim 18.
Haddad in view of Breiner in view of Ardakani does not teach providing for the unclonable output a set of frequencies for the individual latch-inverter.
However, Kvatinsky teaches the use of frequencies for individual latches in a ring oscillator and/or metastable state functionality in order to output a random number (Kvatinsky: ¶ 0072).
The motivation to combine with respect to claim 17 applies equally to claim 18.
Claims 19-20 is rejected under 35 U.S.C. 103 as being unpatentable over Musin et al. (US 2021/0248076 A1) (hereinafter “Musin”), in view of Haddad in view of Breiner in view of Zalivaka in view of How.
Musin teaches a memory system comprising a semiconductor memory device (Musin: Fig. 2 200) having a control circuit (Musin: Fig. 2 220) and a decoder (Musin: Fig. 2 element 240). This decoder’s underlying structure (Musin: shown in Fig. 11) contains a read processor (Musin: Fig. 11 Element 1130), which houses a random number generator (Musin: shown in Fig. 12 element 1136).
The underlying structure of this random number generator structure is not shown.
However, Haddad teaches a structure of a random number generator, this random number generator comprising a latching circuitry, the latch (Haddad: Fig. 5 element 52) including a first input port (Haddad: CLK input port of latch 52), a second input port (Haddad: D input port of latch 52) , an output port (Haddad: Q input port of latch 52), and an enable signal received at the first input port (Haddad: enable signal received at CLK input port i.e., the first input port). Furthermore, an inverter is coupled to this latch (Haddad: Fig. 5 inverter 56 coupled to latch 52) and provides an inverted signal of the data output from the output port of the latch (Haddad: inverter takes data output from the output port Q and inverts the signal), the inverted signal being provided back to the second input port of the latch (Haddad: the inverted signal is provided to the second input port D of latch 52).
This structure of a random number generator as taught by Haddad can be implemented as the random number generator of Musin (Musin: Element 1136 within read processor 1130 which in turn resides within the decoder 1100 which correlates to the row decoder in Fig. 2 Element 240 of the semiconductor memory device).
It would be obvious to a person having ordinary skill in the art to combine the random number generator as taught by Haddad with the semiconductor memory device as taught by Music as both teachings are directed to digital design for integrated circuits. The improvement of Haddad lies in being able to adjust the randomness of the generator to compensate for possible manufacturing dispersions thus increasing entropy (Haddad: ¶ 0062).
Therefore, Musin in view of Haddad teaches:
A memory system comprising:
a semiconductor memory device having a controller and a latching circuit, wherein the latching circuit comprises a latch including a first input port, a second input port, and an output port, the latch configured to receive an enable signal at the first input port; and
an inverter coupled to the latch, configured to generate an inverted signal of data output from the latch, and configured to provide the inverted signal back to the second input port.
Musin in view of Haddad does not explicitly teach the internal latch structure or arrangement of gates within the latch or the controller configured to operate the latching and determine whether the functionality would be as a ring oscillator or as a memory for data storage.
However, Breiner teaches:
a first NOR gate and a second NOR gate coupled together in series (Breiner: Slide 17 the bottom NOR gate is the first NOR gate, and the top NOR gate is the second NOR gate; the gated D-latch comprising a set-reset latch with 2 NOR gates, each correspondingly receiving a set or reset input, the first NOR gate receiving the set input and the second NOR gate receiving the reset input, and the output of the second NOR gate being output, which is what goes through the inverter of Haddad’s latch; Slide 17 gated D-latch takes as inputs D, Strobe which corresponds to CLK of Haddad’s latch, and has as outputs Q, which corresponds to the output port D of Haddad’s latch; the first NOR gate provides an input to the second NOR gate and therefore is connected in series), wherein the first NOR gate has an output coupled through the inverter to provide an inverted input from the first NOR gate as the inverted signal (Breiner: Slide 17 the bottom NOR gate as the first NOR gate provides an output Q, which is provided at the output of the latch, having this internal D latch structure at the latch 52 of Haddad’s system shown in Fig. 5, there would be the inverter 56 to take the output signal and create the inverted signal, which is then provided back to the latch as an input as shown in Fig. 5 of Haddad);
a first AND gate and a second AND gate in parallel with the first AND gate, each of the first AND gate and the second AND gate receiving both a) the enable signal and b) the inverted signal from the first NOR gate (Breiner: Slide 17 2 AND gates in parallel, each receiving the inverted signal provided by Haddad’s inverter 56, and an enable signal as indicated by Strobe in Slide 17);
the first AND gate providing an output which is input to the second NOR gate (Breiner: first AND gate is the top gate, providing input to the second NOR gate), and
the second AND gate providing an output which is input to the first NOR gate (Breiner: the second AND gate is the bottom gate, providing input to the first NOR gate as discussed before).
It would be obvious to one with ordinary skill in the art to combine to one of ordinary skill in the art to utilize the internal gating structure as taught by Breiner for the latch-inverter structure as taught in Haddad because while Haddad does not teach internal structure of the latch, Breiner does teach the internal structure of the latch. It is obvious to use a known technique to improve similar devices in the same way. See MPEP 2141(III)(c).
Musin in view of Haddad in view of Breiner does not explicitly teach the controller configured to operate the latching and determine whether the functionality would be as a ring oscillator or as a memory for data storage.
However, Zalivaka teaches the latch-based PUF acting as a ring oscillator when the enable signal is at a first level (Zalivaka: Pg. 66 Section 4.3.1 lines 3-8 first level at EN = ‘1’ triggers ring oscillator functionality RO-PUF) and acting as a memory when the enable signal is at a second level (Zalivaka: Pg. 4.3.1 Lines 6-8 explains SRAM-PUF functionality when second level EN = ‘0’ is triggered).
The motivation to combine with respect to claim 1 equally applies to claim 19.
Musin in view of Haddad in view of Breiner further in view of Zalivaka does not explicitly teach a controller to operate the latching circuit.
However, How teaches a controller configured to provide the enable signal to the latch (Fig. 1 shows controllers providing an enable signal to each of the latches). Based on this controller’s enable input to the latch, the mode of latch functionality will be determined to operate as a ring oscillator or memory as taught by Zalivaka.
The motivation to combine How with respect to claim 2 applies equally to claim 19.
Therefore, Musin in view of Haddad in view of Breiner in view of Zalivaka in view of How teaches:
A memory system comprising:
a semiconductor memory device having a controller and a latching circuit, wherein the latching circuit comprises a latch including a first input port, a second input port, and an output port, the latch configured to receive an enable signal at the first input port; and
an inverter coupled to the latch, configured to generate an inverted signal of data output from the latch, and configured to provide the inverted signal back to the second input port;
wherein the controller is configured to operate the latching circuit as either a ring oscillator for random number generation or a memory for data storage,
a first NOR gate and a second NOR gate coupled together in series, wherein the first NOR gate has an output coupled through the inverter to provide an inverted input from the first NOR gate as the inverted signal;
a first AND gate and a second AND gate in parallel with the first AND gate, each of the first AND gate and the second AND gate receiving the enable signal and the inverted signal;
the first AND gate providing an output which is input to the second NOR gate, and
the second NAND gate providing an output which is input to the first NOR gate.
Regarding claim 20, while Musin in view of Haddad in view of Breiner in view of Zalivaka in view of How further teaches:
The circuit of claim 1, wherein the latch comprises a set-reset latch having a first NOR gate, a second NOR gate, a set input for the first NOR gate, a reset input for the second NOR gate, a first data output of the first NOR gate coupled to the second NOR gate, and a second data output of the second NOR gate provided to the inverter (Breiner: Slide 17 the gated D-latch comprising a set-reset latch with 2 NOR gates, each correspondingly receiving a set or reset input, the first NOR gate receiving the set input and the second NOR gate receiving the reset input, and the output of the second NOR gate being output, which is what goes through the inverter of Haddad’s latch; Slide 17 gated D-latch takes as inputs D which corresponds to Haddad’s D input port, Strobe which corresponds to CLK input port of Haddad’s latch, and has as output Q, which corresponds to the output port D of Haddad’s latch),
a first AND gate coupled to the set input of the first NOR gate, and (Breiner: Slide 17 first AND gate coupled to the set input of the first NOR gate)
a second AND gate coupled to the reset input of the second NOR gate (Breiner: Slide 17 second AND gate coupled to the reset input of the second NOR gate).
The motivation to combine with respect to claim 19 equally applies to claim 20.
Conclusion
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/M.D.R./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151