DETAILED ACTION
This action is responsive to the following: the amended claims and arguments and response made in amendment filed on July 23, 2025.
Claims 1-13 and 15-20 are pending. Claim 14 is cancelled. Claims 21-29 are withdrawn. Claims 1 and 18 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgement is made of the applicant’s claim of foreign priority. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Response to Amendment
The amendment filed on July 23rd, 2025 has been entered. Claims 1-13 and 15-20 remain pending. Claim 14 is cancelled and Claims 21-29 are withdrawn. Applicant’s amendment to claims overcome some of the rejections under 35 U.S.C 112(a) and 35 U.S.C 112(b).
Claim Rejections - 35 USC § 112 – written description requirement
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-13, and 15-17 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventors, at the time the application was filed, had possession of the claimed invention.
Independent claim 1 recites, “Control Logic.” From the Specification the “control Logic” is only described by what it does, as opposed to what it is. Even though the “program operation controller,” “verify voltage controller,” and “bit line voltage controller” are shown as boxes in a block diagram within the control logic, their structure is also unclear from the disclosure and it does not appear these “controllers” are structures or circuits (contra “sensing circuit” or “data input/output circuit,” which are well understood circuitry). In other words, it appears the disclosure relates to unique methods of operation (i.e., tracking of the voltage gap for the two-step verification, the program enable/inhibit voltage applicable to the bit line, and ∆V used for ISPP) yet these claims are drafted in apparatus form, with their functions used as adjectives for the control logic terms. There is insufficient disclosure of hardware and software. MPEP 2161.01(I). See also definiteness requirement rejection infra. The dependent claims do not recite any further details of the structure of the control logic or these controllers, but instead many simply recite the function the control logic performs.
This reject is not applicable to the method of operation claims. The examiner notes that if claims 1-17 would be favorably considered if redrafted in method of operation format, provided they were also amended to distinguish from the applied prior art.
Claim Rejections - 35 USC § 112 – definiteness requirement
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-13 and 15-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
First, independent claim 1 is indefinite because it attempts to limit the configuration of the peripheral circuit of a “memory device” such that it carries out the claimed operations and “control logic” configured to control the peripheral circuit, which renders the claim indefinite because it is unclear what specifically of the control logic is configured to control the peripheral device such that if performs the operations specified or what configuration of peripheral circuit is necessary to perform these operations or what configuration of this memory device must exist for this operation method to be realized. MPEP 2173.02(II) instructs examiners that definiteness of claim language must be analyzed, not in a vacuum, but in light of: (A) The content of the particular application disclosure; (B) The teachings of the prior art; and (C) The claim interpretation that would be given by one possessing the ordinary level of skill in the pertinent art at the time the invention was made. MPEP 2173.05(g) instructs examiners as follows:
Functional language may also be employed to limit the claims without using the means-plus-function format. See, e.g., K-2 Corp. v. Salomon S.A., 191 F.3d 1356, 1363, 52 USPQ2d 1001, 1005 (Fed. Cir. 1999). Unlike means-plus-function claim language that applies only to purely functional limitations, Phillips v. AWH Corp., 415 F.3d 1303, 1311, 75 USPQ2d 1321, 1324 (Fed. Cir. 2005) (en banc) ("Means-plus-function claiming applies only to purely functional limitations that do not provide the structure that performs the recited function."), functional claiming often involves the recitation of some structure followed by its function.
. . .
Notwithstanding the permissible instances, the use of functional language in a claim may fail "to provide a clear-cut indication of the scope of the subject matter embraced by the claim" and thus be indefinite.
. . .
Unlimited functional claim limitations that extend to all means or methods of resolving a problem may not be adequately supported by the written description or may not be commensurate in scope with the enabling disclosure, both of which are required by 35 U.S.C. 112(a) and pre-AIA 35 U.S.C. 112, first paragraph.
. . .
Examiners should consider the following factors when examining claims that contain functional language to determine whether the language is ambiguous: (1) whether there is a clear cut indication of the scope of the subject matter covered by the claim; (2) whether the language sets forth well-defined boundaries of the invention or only states a problem solved or a result obtained; and (3) whether one of ordinary skill in the art would know from the claim terms what structure or steps are encompassed by the claim. These factors are examples of points to be considered when determining whether language is ambiguous and are not intended to be all inclusive or limiting. Other factors may be more relevant for particular arts. The primary inquiry is whether the language leaves room for ambiguity or whether the boundaries are clear and precise.
. . .
When a claim limitation employs functional language, the examiner’s determination of whether the limitation is sufficiently definite will be highly dependent on context (e.g., the disclosure in the specification and the knowledge of a person of ordinary skill in the art).
. . .
During prosecution, applicant may resolve the ambiguities of a functional limitation in a number of ways. For example: (1) "the ambiguity might be resolved by using a quantitative metric (e.g., numeric limitation as to a physical property) rather than a qualitative functional feature" (see Halliburton Energy Servs., 514 F.3d at 1255-56, 85 USPQ2d at 1663); (2) applicant could demonstrate that the "specification provide[s] a formula for calculating a property along with examples that meet the claim limitation and examples that do not" (see id. at 1256, 85 USPQ2d at 1663 (citing Oakley, Inc. v. Sunglass Hut Int’l, 316 F.3d 1331, 1341, 65 USPQ2d 1321, 1326 (Fed. Cir. 2003))); (3) applicant could demonstrate that the specification provides a general guideline and examples sufficient to teach a person skilled in the art when the claim limitation was satisfied (see Marosi, 710 F.2d at 803, 218 USPQ at 292); or (4) applicant could amend the claims to recite the particular structure that accomplishes the function.
MPEP 2173.05(p)(II) also instructs examiners, regarding claims reciting functional or operational limitations that may create confusion as to what constitutes infringement, as follows:
A single claim which claims both an apparatus and the method steps of using the apparatus is indefinite under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
. . .
In contrast, when a claim recites a product and additional limitations which focus on the capabilities of the system, not the specific actions or functions performed by the user, the claim may be definite under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Independent Claim 1 recites a memory device that includes “a plurality of memory cells”, “a peripheral circuit,” which are understood. However, the claim also recites “control logic.” No circuitry is defined in the claim. The claim states that the control logic is “configured to control the peripheral circuit to perform the program operation.” And is further “configured to change a verify voltage interval…’” And finally is “configured to control the peripheral circuit to apply a first bit line voltage…and apply a second bit line voltage…”
However, this language in the clauses of the claim merely define features of what the control logic does rather than what it is. These limitations are functional and not limited to sufficient structure or circuitry. No structures recited in the specification or claims point to how this memory device is “configured” structurally to only be able to operate in the method outlined in final limitations directed to the manner of using the device claimed. When both a product and a method are claimed in the same claim it is unclear whether infringement occurs when the product is constructed or when the product is used.
It is unclear what of the structures of the “memory device” is configured such that this operation happens. From the applicant’s filed disclosure, Figure 5, 7, 10A-B depict voltage vs time graphs that depict the outcomes of some of the operations involved, but they all depict voltages generated by the peripheral circuitry for use programming and verifying the cells of the memory array and not do not themselves define any feature that is “configurable” or programmable to perform the functions shown. The only other relevant figure, regarding a supposed “configuration” that would yield this functionality, is Figure 2.
Figure 2 shows the “memory device,” but does not provide sufficient detail to indicate or inform those skilled in the memory art as to what is configured to perform the functions recited in claim 1. Of the features shown in figure 2, the address decoder, the voltage generator, the page buffers, the sensing circuit, the data input/output circuit, the memory cell array are all well-established circuitry in the memory art. The control logic consisting of program operation controller, verify voltage controller, bit line voltage controller, and program setting information storage do not appear to be, and would need to be supported by a description of their structure or circuitry.
It is not clear from the blocks shown in figured 2 or as described in the specification what about the control logic is configured to perform the operations specified in claim Claims 2-17 present the same issues.
Therefore, the scope of the claims are indefinite. See MPEP 2173.02(II), 2173.05(g), 2173.05(p)(II). The examiner notes, as discussed supra the written description requirement rejection, that if claims 1-17 would be favorably considered if redrafted in method of operation format, provided they were also amended to distinguish from the applied prior art.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9, 17-18, 20 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over Jung et al (US 20210166771) in view of Kim et al (US 20090296486 A1).
Regarding Independent Claim 1, Jung teaches a memory device comprising:
a plurality of memory cells (Fig. 1: 110);
a peripheral circuit (Fig. 1: 120) configured to perform a program operation (Fig. 1: 130; para 59) including a plurality of loops each including a program voltage apply step of applying a program voltage (Fig. 5: Vpgm) to target cells among the plurality of memory cells and a double verify step (Fig. 3: double verify step) of verifying whether the target cells have been programmed by using a first verify voltage (Fig. 3: V_vfy1) and a second verify voltage (Fig. 3: V_vfy2) greater than the first verify voltage, the first verify voltage (Fig. 3: V_vfy1) and the second verify voltage (Fig. 3: V_vfy2) correspond to a target program state of one of the target cells; and
a program operation controller (Fig. 1: 130; para 59) configured to control the peripheral circuit to perform the program operation, wherein the program operation controller includes:
control logic (Fig. 1: 130; para 59) configured to change a verify voltage interval (Fig. 9B: ΔVvfy; para 144) as an interval between the first verify voltage (Fig. 9B: Vvfy_i; para 144) and the second verify (Fig. 9B: Vvfy_i; para 144) voltage from a predetermined target loop among the plurality of loops; and
a bit line voltage controller (Fig. 1: 130; para 6-7) configured to control the peripheral circuit to apply a first bit line voltage (Fig. 9B: VBL_i; para 137) to bit lines connected to first memory cells having a threshold voltage lower than the first verify voltage among the target cells and apply a second bit line voltage higher (Fig. 9B: VBL_k; para 137) than the first bit line voltage to bit lines connected to second memory cells having a threshold voltage which is one of higher than and equal to the first verify voltage and is lower than the second verify voltage among the target cells in the program voltage apply step of an (n+1)th loop, and apply the second bit line voltage to the bit lines connected to the first memory cells in the program voltage apply step of an (n+2)th loop, based on a verify result in the double verify step of an nth loop as the target loop among the plurality of loops (see para. 195 with respect to Fig. 7C with respect to Fig. 9),
wherein n is a natural number that is one of equal to and greater than 2.
Though Jung teaches a multistep verification stage (Fig. 3: V_vfy1-3), Jung is unclear as to if the change between a change in the interval between verification voltage levels.
Kim teaches a change in the interval between verification levels from one program verification loop to the next (Fig. 5: 520, 540).
When programming multiple multilevel memory cells it may take multiple programming cycles to increase the threshold voltage of a cell to the desired state. And it may desirable to increase the programming voltage despite not having reached the programmed state in order to better target certain cells within the distribution of threshold voltages.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Kim to the teachings of Jung to produce a control logic that adjusts the interval between two verify voltages used in the double verify step of a program verify cycle.
Regarding Claim 2, Jung teaches the program controller (Fig. 1: 130; see para. 59) further includes a “program setting information storage” configured to store target loop information as information on the target loop (see para. 29 and 54-59, explaining the control logic 130 as a combination of hardware and software, and because it controls the other circuitry according to commands, it must include “storage” for the parameters required by the control logic to perform the operations according to their disclosed algorithm, which involves monitoring the program loop count as shown in e.g., Fig. 10).
Regarding Claim 3, Jung teaches wherein each of the (n+1)th loop and the (n+2)th loop includes the program voltage apply step (Fig. 3: PGM Step).
Regarding Claim 4, Jung the memory device of claim 1, further comprising a current sensing circuit (Fig. 1: 125) configured to count a fail bit number as a number of cells which have program-failed among the target cells,
wherein the bit line voltage controller (Fig. 1: 130; para 6-7) controls the peripheral circuit to allow the second bit line voltage to be further increased (para 126-128) than a default bit line voltage in a program voltage apply step of the (n+1)th loop and the (n+2)th loop.
Regarding Claim 5, Jung teaches the memory device of claim 4, wherein the bit line voltage controller (Fig. 1: 130; para 6-7) sets the default bit line voltage according to a program and erase count as a number of times a program operation and an erase operation are performed on a memory block including the target cells (para 103).
Regarding Claim 6, Jung teaches the memory device of claim 4, wherein the nth loop is a pass loop as a loop in which the fail bit number is one of equal to and smaller than a reference number among the plurality of loops (para 155).
Regarding Claim 7, Jung teaches the memory device of claim 1, wherein the verify voltage m controller changes the verify voltage interval in the nth loop to be narrower than a default verify voltage interval as a verify voltage interval in a first loop to an (n-1)th loop among the plurality of loops (para 145).
Regarding Claim 8, Jung teaches the memory device of claim 7, wherein the verify voltage controller narrows the verify voltage interval by increasing a level of the first verify voltage in the nth loop (para 145).
Regarding Claim 9, Jung teaches the memory device of claim 2, wherein the program operation controller (Fig. 1: 130; para 59) controls the peripheral circuit to perform the program operation by applying a program voltage increased by a step voltage as a loop increases (Fig 3: PL1-n, ΔVpgm, Vpgm1-n) to a selected word line connected to the target cells.
Regarding Claim 17, Jung teaches the memory device of claim 1, wherein the first bit line voltage includes a ground voltage (Fig. 5: BL, Vgnd).
Regarding Independent Claim 18, Jung teaches a method of operating a memory device for performing a program operation of applying a program voltage (Fig. 3: Vpgm[1-n]) increased by a step voltage (Fig. 3: ΔVpgm) as a loop increases (Fig. 3: P[1-n] ) to a word line connected to target cells among a plurality of memory cells and performing a verify operation on the target cells by using a first verify voltage (Fig. 3: V_vfy1) and a second verify voltage (Fig. 3: V_vfy2), the is method comprising:
changing a verify voltage interval to a target interval from a default verify voltage interval by adiusting the first verify voltage based on information on a predetermined target loop, the verify voltage interval (Fig. 9B: ΔVvfy; para 144) is an interval between the first verify voltage (Fig. 9B: Vvfy_i; para 144) and the second verify voltage (Fig. 9B: Vvfy_k; para 144) in an nth loop among a plurality of loops and the default verify voltage interval is a verify voltage interval in a first loop to an (n-1)th loop among the plurality of loops
performing the double verify operation (Fig. 3: V_vfy1, V_vfy2) based on the target interval in an nth loop;
performing the program operation by applying a first bit line voltage (Fig. 5: Vgnd) to bit lines connected to memory cells having a threshold voltage lower than the first verify voltage and applying a second bit line voltage (Fig 5. Vinh) higher than the first bit line voltage to bit lines connected to second memory cells having a threshold voltage which is one of greater than and equal to the first verify voltage and is lower than the second verify voltage in an (n+1)th loop among the plurality of loops, based on a result obtained by performing the verify operation in the nth loop; and
performing a program operation by applying the second bit line voltage (Fig 5. Vinh) to the bit lines connected to the first memory cells in a (n+2)th loop among the plurality of loops
wherein n is a natural number that is one of equal to and greater than 2.
Though Jung teaches a multistep verification stage (Fig. 3: V_vfy1-3), Jung is unclear as to if the change between a change in the interval between verification voltage levels.
Kim teaches a change in the interval between verification levels from one program verification loop to the next (Fig. 5: 520, 540).
When programming multiple multilevel memory cells it may take multiple programming cycles to increase the threshold voltage of a cell to the desired state. And it may desirable to increase the programming voltage despite not having reached the programmed state in order to better target certain cells within the distribution of threshold voltages.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Kim to the teachings of Jung to produce a control logic that adjusts the interval between two verify voltages used in the double verify step of a program verify cycle.
Regarding Claim 20, Jung and Kim teaches the method of claim 18, further comprising setting a magnitude of the second bit line voltage (Fig. 9A: VBL_k) to be greater than a default bit line voltage as a second bit line voltage up to the nth loop, after the target loop (para 125).
Claims 2, 10, 15, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al (US 20210166771) and Kim et al (US 20090296486) in view of Yang et al (US 20190392909)
Regarding Claim 2, Jung and Kim teaches the memory device of claim 1. Notwithstanding the 102 rejection over Jung above that relies upon an understanding of the algorithm disclosed by Jung that their control logic 130 performs, assuming arguendo Jung fails to teach a program operation controller (Fig. 1: 130; para 59), which further includes a program setting information storage configured to store target loop information as information on the target loop, Yang nevertheless teaches this “storage” for the target loop information.
Yang teaches a volatile memory (Fig. 2B: 158; also see para. 244-250 indicating the program controller 622 has memory hardware, for example, having executable instructions or program code to carry out its functions, and it sets and knows the settings and characteristics of the memory so as to carry out programming) which is configured to store information on the target loop.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Yang to the teachings of Jung to produce the memory with control logic containing an information storage device that stores information on the target loop.
Regarding Claim 9, Jung and Kim, or in combination Yang teaches the memory device of claim 2, and Jung further teaches the program operation controller (Fig. 1: 130; para 59) controls the peripheral circuit to perform the program operation by applying a program voltage increased by a step voltage as a loop increases (Fig 3: PL1-n, ΔVpgm, Vpgm1-n) to a selected word line connected to the target cells.
Regarding Claim 10, Jung, Kim, and Yang teach the memory device of claim 9. However, Jung fails to teach a program setting information storage that stores default verify and bit line voltage information, which correspond to step voltage information.
Yang teaches a volatile memory (Fig. 2B: 158; also see para. 244-250 indicating the program controller 622 has memory hardware, for example, having executable instructions or program code to carry out its functions, and it sets and knows the settings and characteristics of the memory so as to carry out programming) which can be used to store default verify voltage, bit line voltage and step voltage information.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Yang to the teachings of Jung to produce a memory devices with a program controller that has storage for storing default verify voltage, bit line voltage, and step voltage values.
Regarding Claim 15, Jung, Kim and Yang teach the memory device of claim 10.
Yang further teaches control logic (Fig. 6: CTRLBLV, 616, 622) sets the default bit line voltage according to a magnitude of the step voltage (paragraph 0272), based on the default bit line voltage information (also see para. 244-250 indicating the program controller 622 has memory hardware, for example, having executable instructions or program code to carry out its functions, and it sets and knows the settings and characteristics of the memory so as to carry out programming that involve multiple double verify steps and bit line program-enable/program-inhibit voltages).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Yang to the teachings of Jung to produce a memory device wherein the default bit line voltage based on the magnitude of the step voltage.
Regarding Claim 16, Jung, Kim, and Yang teaches the memory device of claim 15. Yang also teaches control logic (Fig. 6: CTRLBLV, 616, 622) that sets the default bit line voltage to become greater as the magnitude of the step voltage increases (para. 0272; but also, see para. 195, with respect to Fig. 7C with respect to Fig. 9, indicating a first program loop programs a target cell by using a program-enable voltage of VPSB, which may be 0 as indicated in para. 288, and it will repeat the program loop with increased program increment, or step, voltages until programmed, at which point the bit line voltage is increased to the “program-inhibit” level VPUB, which is VDD as explained in para. 291).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Yang to the teachings of Jung to produce a memory device which sets the magnitude of the bit line voltage to become greater as the step voltage increases.
Claim 11 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al (US 20210166771), Kim et al (US 20090296486), and Yang et al (US 20190392909) in view of Yoo (US 20170068481)
Regarding Claim 11, Jung, Kim, and Yang teach the memory device of claim 10, However they fail to teach a control logic that sets the default verify voltage interval according to a magnitude of the step voltage, based on the default verify voltage information.
Yoo teaches a verify voltage which has a magnitude, which changes with changing program voltage step size (Fig. 12: ΔVpgm[1-3], Vvfy11, Vvfy2[1-3], Vvfy2[1-3]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Yoo to the teachings of Jung and Yang to produce a memory device which sets the magnitude of its verify voltage according to the step size of the program voltages.
Regarding Claim 12, Jung, Kim, Yang, and Yoo teach the limitations of claim 11.
Jung further teach the verify voltage level may increase in varying increments as the program loop count increases (para. 144). That means the “default verify voltage interval [] become[s] wider as the magnitude of the step voltage increases” because Jung’s increment is the “interval” and its variance from a prior increment can increase, as the program loop increases, and when the program loop increases, the magnitude of the step voltage increases (Jung para. 144).
Regarding Claim 19, this claim recites the same limitation as dependent claim 11. Jung and Kim teach the limitations of claim 18, and claim 19 is rejected over the combination of Jung, Kim, Yang, and Yoo, or simply Jung, Kim, and Yoo combined, for the same reasons as claim 11.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Jung et al (US 20210166771), alone, or in combination with Yang et al (US 20190392909), in further view of Liu et al (US 20200075102).
Regarding Claim 13, Jung, alone (see 102 rejection of claim 9), or in combination with Yang (see 103 rejection of claim 9) teaches the limitations of claim 9. However, Yang fails to teach the control logic setting a magnitude of the step voltage according to a position of the selected word line connected to the target cells among a plurality of word lines connected to the plurality of memory cells.
Liu teaches a method applying different voltages at different cell depths in the architecture of a 3D memory (Fig. 5A-B: Vver). With different expected verify voltages on the different levels, the increment for the program voltage on the levels for the word line will be different, so the cell can achieve the target state (which would be indicated as pass, based on the verification voltage employed).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Liu to the teachings of Yang to produce a memory device with a program operation controller configured to apply different magnitude of voltages to different cells based on their positions with the 3D array.
Response to Arguments
Applicant’s arguments with respect to claims 1-13 and 5-20 have been considered but are moot because the new ground of rejection.
With respect to the rejections under 35 U.S.C. 112(a) and 112(b) to lack of written description and indefiniteness respectively. Applicant merely acknowledged that they were rejected but provided no response as to why they now overcome the previous rejections. The only amendments to the claims that seem relevant are first the change in claims 1-17 where “program operation controller,” “verify voltage controller,” and “bit line voltage controller” were all simply changed to “control logic.” This change alone wasn’t enough to overcome the bases for rejection under 35 U.S.C 112. As the reasons for rejection primarily dealt with functional language in claims 1-17 where devices where structures were claimed but described by what they do and not by their structure.
Finally, Claim 18 was rejected due to indefiniteness because of a lack of an antecedent basis issue. That is was corrected in the amendment.
Applicant’s claim that Jung fails to teach a change in the interval between verification voltages applied one after the other in a two step verification process is persuasive, but now moot with the application of Kim. Though Jung teaches a multi-step verification process where multiple verification voltages are used to evaluate whether or not cells being programmed have reached certain threshold voltages. It is unclear if Jung shows a change in the verification voltage from one step to the next. However, Kim unambiguously shows such a change in voltage interval in Fig. 5. Thus, applying the teachings of Jung in view of Kim under 35 U.S.C 103 the claims are still rejected.
No argument was made by applicant for the rejection of claims under 35 U.S.C. 103 in the previous application were improper. Thus, all previous rejections have under 35 U.S.C. 103 have been modified to include Kim as a reference and are maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH FIDELIS STORMES whose telephone number is (571)272-3443. The examiner can normally be reached M-F: 6:30am-4pm CST.
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/JOSEPH FIDELIS STORMES/ Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/ Supervisory Patent Examiner, Art Unit 2825