Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Amendment to claims 1 and 3 submitted on September 17, 2025 is acknowledged and has since been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Iacopi (US 20100327319 A1).
Regarding Claim 1, an integrated circuit (IC) device (shown Fig. 2B), comprising:
a substrate (not illustrated, see [0013]);
a gate insulator (4a);
a first region (6), comprising a first semiconductor material (see [0114]) with dopants of a first type (n-type, shown Fig. 2B);
a second region (2), comprising a second semiconductor material (see [0117]) with dopants of a second type (p-type, shown Fig. 2B), the second type different from the first type; and
a channel region (5), comprising a third semiconductor material (see [0115]),
wherein:
the channel region is between the first region and the second region (shown Fig. 2B),
the first region is between the channel region and the substrate (see [0013] which describes the vertical nanowire grown on a substrate),
one of the first region and the second region is a source region of a transistor (see [0117] describing the second region as a source), and another one of the first region and the second region is a drain region of the transistor (see [0114] describing the first region as a rain); and
the first region is in contact with (see [0118]) and wholly wrapped around by the gate insulator (see Fig. 2B and [0118] which describes the gate dielectric formed on the source-channel-drain structure and overlapping the first and second regions along a longitudinal direction).
Regarding Claim 2, Iacopi teaches the IC device according to claim 1, further comprising:
a gate (4a + 4b, shown Fig. 2B) wrapping around at least a portion of the channel region (shown Fig. 2B), wherein a longitudinal axis of the gate is orthogonal to the substrate (described in [0013]).
Regarding Claim 3, Iacopi teaches the IC device according to claim 2, wherein the gate comprises:
the gate insulator wrapping around at least a portion of the channel region (shown Fig. 2B); and
a gate electrode (4b) wrapping around at least a portion of the gate insulator (shown Fig. 2B).
Regarding Claim 4, Iacopi teaches the IC device according to claim 1, wherein the dopants of the first type are n-type dopants and the dopants of the second type are p-type dopants (see Fig. 2B).
Regarding Claim 5, Iacopi teaches the IC device according to claim 1, wherein the first semiconductor material (see selection in [0034]) is different from the second semiconductor material (see selection in [0035]) or the third semiconductor material (wherein the third semiconductor material is the same as the first semiconductor material, see also [0026]).
Regarding Claim 6, Iacopi teaches the IC device according to claim 1, wherein the first semiconductor material (Si, see [0034]), the second semiconductor material (Si, see [0035]), and the third semiconductor material (Si, wherein the third semiconductor material is the same as the first semiconductor material, see [0026]) are the same.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.P.B./Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893