DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/21/2026 has been entered.
Response to Amendments
Applicant's response of 04/21/2026 has been acknowledged. Claims 1, 11,
16, and 23 have been amended. Claim 13 is canceled. Claim 24 is added. No new matter has been added.
This office action considers claims 1, 3-4, 6, 8-12, and 14-24 pending for prosecution and are examined on their merits.
Response to Arguments
Applicant's arguments of 04/21/2026 with respect to the rejections of claims have
been fully considered but are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 1, 4, 6, 8, 21, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Okamoto et al. (US 20230337439 A1 - hereinafter Okamoto) in view of Kurokawa (US 9349722 B2 - hereinafter Kurokawa), Yamazaki et al. (US 20160172500 A1 – hereinafter Yamazaki-2500), and Lee et al. (US 9666797 B1 – hereinafter Lee).
Regarding independent claim 1, Okamoto teaches
(Currently amended) A method for fabricating ([0120] - "a method
for manufacturing a semiconductor device with high productivity can be provided") an integrated circuit device (5400 - Fig. 24J - [0509] - "ICD main unit") comprising:
forming a field effect transistor (300 - Fig. 13 - {[0076] - "OS FET ... also ...
referred to as a transistor"}, {[0187] - "transistor 300"}) on a semiconductor substrate (310 - Fig. 13 - [0187] - "a substrate 310");
depositing a first dielectric layer (320 - Fig. 13 - [0189] - "the insulator 320,
aluminum nitride can be used") over the FET (300);
forming a gate contact plug (328 – [0196] – “the conductor 328 and the conductor 330 have a function of a plug or a wiring”) extending through the first dielectric layer (320) top surface of a gate structure (Fig. 14A – [0217] – “560 functions as a first gate (also referred to as a top gate) electrode” – this is part of the gate structure – hereinafter ‘GS’ and shown in Fig. 13 annotated, see below) of the FET (300);
depositing a first metal-containing dielectric layer (322 - Fig. 13 - [0189] -
"For the insulator 322 ... aluminum oxide can be used") over the first dielectric layer (320) and the gate contact plug (328), wherein the top surface of the gate structure of the FET is spaced apart from the first metal-containing dielectric layer by the first dielectric layer and the gate contact plug (328);
forming a lower conductive feature extending through the first metal-containing dielectric layer to the gate contact plug (328), wherein in a cross-sectional view, an interface formed by the lower conductive feature and an entire sidewall of the first metal-containing dielectric layer is aligned with a sidewall of the gate contact plug (328), wherein the lower conductive feature is entirely embedded in the first metal-containing dielectric layer;
forming a first thin film transistor (TFT) (500 - Fig. 13 - [0176] - "The transistor 500 is provided above the transistor 300") over the first metal-containing dielectric layer (322 - Fig. 13 - [0189] - "For the insulator 322 ... aluminum oxide can be used");
depositing a second dielectric layer over the first TFT (574 - Fig. 13 - [0213] - "an insulator 574");
depositing a second metal-containing dielectric layer over (581 - Fig. 13 - [0257] - "aluminum oxide ... is preferably used for ... the insulator 581") the second dielectric layer (574); and
forming an upper conductive feature extending through the second metal-containing dielectric layer, wherein the upper conductive feature is in contact with the second metal-containing dielectric layer.
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Okamoto does not expressly disclose the other limitations of claim 1.
However, in analogous art, Kurokawa teaches
wherein the top surface of the gate structure (Fig. 6C annotated, see below – hereinafter ‘TGS’) of the FET (104 – Fig. 6C – [21 = 4-26] – “amplifier transistor 104”) is spaced apart (313 – [264 = ] – “insulating film 313 may be provided over the transistor 322” – this corresponds to the first dielectric layer – Fig. 6C annotated, see below, shows this) from the first metal-containing dielectric layer (403_1 – Fig. 6C – [286] – “403_1 can also be used as a photomask” – a photomask and contains metal therefore this is the first metal-containing dielectric layer) by the first dielectric layer (401 – Fig. 6C – [273] – “tier 401 including the amplifier transistor 104 … single crystal silicon is used for a channel formation region of the amplifier transistor 104” – this is the first dielectric layer).
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Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate the spacing structure of
Kurokawa into Okamoto.
An ordinary artisan would have been motivated to use the known technique of Kurokawa in the manner set forth above to produce the predictable results of [2:45-
52] - "The parasitic resistance of a wiring which is electrically connected to the transistor can be used as the resistor of the D/A converter. Transistors can be stacked alternately with interlayer films and the parasitic resistance of a conductive material provided in a contact hole formed in the interlayer film can be used as the resistor, for example. Thus, the area of the resistor can be reduced and the area of the memory cell per bit can be reduced."
Okamoto and Kurokawa do not expressly disclose the other limitations of claim 1.
However, in analogous art, Yamazaki-2500 teaches
forming an upper conductive feature (498c – Fig. 40 – [0543] – “The insulator 494 includes an opening reaching … the conductor 496c. In the openings … the conductor 498c are embedded” – this corresponds to the upper conductive feature) extending through the second metal-containing dielectric layer (494 – Fig. 40 – [0544] – “494 may each be formed to have, for example, a single-layer structure or a stacked-layer structure including an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum” – this is a metal containing dielectric), wherein the upper conductive feature (498c) is in contact with the second metal-containing dielectric layer (494 – Fig. 40 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate the upper conductive feature structure of Yamazaki-2500 into Okamoto and Kurokawa.
An ordinary artisan would have been motivated to use the known technique of Yamazaki-2500 in the manner set forth above to produce the predictable results of
[0004] – “A technique for forming a transistor by using a semiconductor over a substrate having an insulating surface has attracted attention. The transistor is applied to a wide range of semiconductor devices such as an integrated circuit and a display device.”
Okamoto, Kurokawa, and Yamazaki-2500 do not expressly disclose the other limitations of claim 1.
However, in analogous art, Lee teaches
forming a lower conductive feature (Fig. 1D annotated, see below – [4:45-48] – “upper electrode 118 may comprise gold (Au), aluminum (Al), copper (Cu), TiN, etc., or other materials having good conductivity” – hereinafter ‘118L’) extending through the first metal-containing dielectric layer (112 – Fig. 1D – [3:46-47] – “material layer 112 is a first transition metal containing dielectric material”) to the gate contact plug, wherein in a cross-sectional view, an interface formed by the lower conductive feature (118L) and an entire sidewall of the first metal-containing dielectric layer (112) is aligned (Fig. 1D shows this) with a sidewall of the gate contact plug, wherein the lower conductive feature (118L) is entirely embedded in the first metal-containing dielectric layer (112 – Fig. 1D shows this).
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Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to substitute the alignment of structure of Lee into Okamoto, Kurokawa, and Yamazaki-2500.
An ordinary artisan would have been motivated to use the known technique of Lee in the manner set forth above to produce the predictable results of [1:17-19] – “a memory structure and a manufacturing method for a memory structure. The memory structure has excellent operating properties.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 4, Okamoto, as modified by Kurokawa, Yamazaki-2500, and Lee, teaches claim 1 from which claim 4 depends. Okamoto and Lee do not expressly disclose the limitations of claim 4.
However, in analogous art, Kurokawa teaches
(Previously presented) The method of claim 1, further comprising:
forming a second TFT (104, 111, 112, 113 - Fig. 5 - {[29:1] - "transistor 104"}, {[29:16-20] - "the transistor 111 ... over ... the transistor 112 ... over ... the transistor 113"}) over the second metal-containing dielectric layer.
Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate the spacing structure of
Kurokawa into Okamoto and Lee.
An ordinary artisan would have been motivated to use the known technique of Kurokawa in the manner set forth above to produce the predictable results of stacking a third transistor over the preceding two transistors to reduce the area of the chip as Kurokawa states [29:21-24] - "In this manner, the plurality of transistors included in the D/A converter are stacked alternately with interlayer films, so that the area of the memory cell can be reduced."
Okamoto, Lee, and Kurokawa do not expressly disclose the other limitations of claim 4.
However, in analogous art, Yamazaki-2500 teaches
the second metal-containing dielectric layer (494 – Fig. 40 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate the second dielectric layer structure of Yamazaki-2500 into Okamoto, Lee, and Kurokawa.
An ordinary artisan would have been motivated to use the known technique of Yamazaki-2500 in the manner set forth above to produce the predictable results of
[0283] – “Aluminum oxide is preferably used as the insulator 118 because it is highly effective in preventing transmission of both oxygen and impurities such as hydrogen and moisture” thus preventing moisture from degrading the transistors.
Regarding claim 6, Okamoto, as modified by Kurokawa, Yamazaki-2500, and Lee, teaches claim 1 from which claim 6 depends. Okamoto further teaches
(Previously presented) The method of claim 1, wherein the gate
structure (GS) of the FET comprises:
a gate dielectric (315 - Fig. 13 - [0177] - "insulator 315") in contact with a top surface of the semiconductor substrate (310 - Fig. 13 - [0177] - "substrate 310") ; and
a gate electrode (316 - Fig. 13 - [0183] - "conductor 316 functioning as a gate electrode") over the gate dielectric (315).
Regarding claim 8, Okamoto, as modified by Kurokawa, Yamazaki-2500, and Lee, teaches claim 1 from which claim 8 depends. Okamoto further teaches
(Original) The method of claim 1, wherein depositing the first metal-
containing dielectric layer (322) is performed using a sputter deposition process or an atomic layer deposition ([0327] - "aluminum oxide deposited by an ALD method may be used as the first insulator" - the first insulator is 322 and is the first base insulating film) process.
Okamoto, Yamazaki-2500, and Lee do not expressly disclose the other limitations of claim 8.
However, in analogous art, Kurokawa teaches
a sputter deposition process ([19:59-60] - "The base insulating film can be formed by ... a sputtering method").
Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate the sputter deposition
process of Kurokawa into the structure Okamoto, Yamazaki-2500, and Lee.
An ordinary artisan would have been motivated to use the know technique of
Kurokawa in the manner set forth above to produce the predictable result to form the
first metal-containing dielectric layer by sputter deposition.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 21, Okamoto, as modified by Kurokawa, Yamazaki-2500, and Lee, teaches claim 1 from which claim 21 depends. Okamoto, Yamazaki-2500, and Lee do not expressly disclose the limitations of claim 21.
However, in analogous art, Kurokawa teaches
(Previously presented) The method of claim 1, wherein the first dielectric
layer (401 – Fig. 6C – [29:1-5] – “tier 401 including the amplifier transistor 104 … single crystal silicon is used for a channel formation region of the amplifier transistor 104” – this is the first dielectric layer) extends between the top surface (313 – [30:18-19] – “insulating film 313 may be provided over the transistor 322” – this corresponds to the first dielectric layer) of the gate structure (Fig. 6C annotated, see below – hereinafter ‘TGS’) of the FET (104 – Fig. 6C – [21 = 4:26] – “amplifier transistor 104”) and the first metal-containing dielectric layer (403_1 – Fig. 6C – [286 = 30:22] – “403_1 can also be used as a photomask” – a photomask contains metal for standard photolithography therefore this is the first metal-containing dielectric layer).
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Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate first dielectric layer structure of Kurokawa into the structure Okamoto, Yamazaki-2500, and Lee.
An ordinary artisan would have been motivated to use the know technique of
Kurokawa in the manner set forth above to produce the predictable result of [29:5} – “enables high-speed reading.”
Regarding claim 23, Okamoto, as modified by Kurokawa, Yamazaki-2500 ,and Lee, teaches claim 1 from which claim 23 depends. Okamoto further teaches
the gate contact plug (328).
Okamoto, Kurokawa, and Yamazaki-2500 do not expressly disclose the limitations of claim 21.
However, in analogous art, Lee teaches
(Currently amended) The method of claim 1,
wherein in the cross-sectional view, the gate contact plug has a width the same as a width (Fig. 1D shows this) of the lower conductive feature (118L).
Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to substitute the width of structure of Lee into Okamoto, Kurokawa, and Yamazaki-2500.
An ordinary artisan would have been motivated to use the known technique of Lee in the manner set forth above to produce the predictable results as stated above in claim 1.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Okamoto in
view of Kurokawa, Yamazaki-2500, Lee, and Jambunathan et al. (US 20200365585 A1 - hereinafter Jambunathan).
Regarding claim 3, Okamoto, as modified by Kurokawa, Yamazaki-2500, and Lee, teaches claim 1 from which claim 3 depends. Okamoto further teaches
(Previously presented) The method of claim 1, wherein forming the
lower conductive feature (328 and 330 - [0196] - "the conductor 328 and the conductor 330 have a function of a plug or a wiring") comprises:
etching an opening (Fig. 13 annotated, see below – hereinafter ‘OP’) in the first metal-containing dielectric layer (322); and
filling the opening (OP) with a conductive material (540a - Fig. 13 - [0320] - "conductor 540a" – 328 is similar to 540a being filled with the conductor).
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Okamoto, Kurokawa, Yamazaki-2500, and Lee, do not expressly disclose the other limitations of claim 3.
However, in an analogous art, Jambunathan teaches
etching an opening ([0023] - "hardmask 310 may then be patterned using any
suitable techniques, such as one or more ... etch processes, for example. Hardmask
310 may include any suitable material, such as ... aluminum oxide").
Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate the forming of the
conductive feature, the opening, by etching as taught by Jambunathan into Okamoto, Kurokawa, Yamazaki-2500, and Lee.
An ordinary artisan would have been motivated to use the known technique of
Jambunathan in the manner set forth above to produce the predictable result to etch the
opening in the first conductive metal.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Okamoto in view of Kurokawa, Yamazaki-2500, Lee, and Keuning et al. ("Cathode encapsulation of organic light emitting diodes by atomic layer deposited A 1203 films
and A203/a-SiNx: H stacks", Journal of Vacuum Science & Technology A, 2012, Vol. 30 – hereinafter Keuning).
Regarding claim 9, Okamoto, as modified by Kurokawa, Yamazaki-2500, and Lee, teaches claim 1 from which claim 9 depends. Okamoto further teaches
(Original) The method of claim 1, further comprising:
dicing ([0461] - "A dicing step is performed") the semiconductor substrate into
at least one chip (4800a - Fig. 23B - [0462] - "With the dicing step, a chip 4800a").
Okamoto, Kurokawa, Yamazaki-2500, and Lee do not expressly disclose the other limitations of claim 9.
However, in an analogous art, Keuning teaches
forming an encapsulation layer (pp.01 A 131 - [0004] - "In this respect, atomic
layer deposition (ALO) is of interest as it is a technique which is known for its conformal
deposition over 30 structures ... for ... encapsulation") encapsulating the chip, wherein
the encapsulation layer comprises a metal-containing dielectric material
(pp.01 A 131 - [0004] - "Several studies have already shown that Al2O3 synthesized by
ALO is a promising candidate for OLEO encapsulation").
Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate the encapsulation layer
process of Keuning into Okamoto, Kurokawa, Yamazaki-2500, and Lee.
An ordinary artisan would have been motivated to use the know technique Keuning in the manner set forth above to produce the predictable results of avoiding/reducing hydrogen and/or moisture diffusion through the encapsulation and into the chip as Keuning teaches in the [Abstract] - "On the basis of Ca test measurements, a very low intrinsic water vapor transmission rate ... were found for 20--40 nm Al2O3."
Regarding claim 10, Okamoto, as modified by Kurokawa, Yamazaki-2500, Lee, and Keuning teaches claim 9 from which claim 10 depends. Okamoto further teaches
a material of the first metal-containing dielectric layer (322 - [0189] –
"For the insulator 322 ... aluminum oxide can be used").
Okamoto, Kurokawa, Yamazaki-2500, and Lee do not expressly disclose the other limitations of claim 10.
However, in an analogous art, Keuning teaches
wherein the metal-containing dielectric material of the encapsulation layer (pp.01 A 131 - [0004] - "Several studies have already shown that Al2O3 synthesized by ALO is a promising candidate for OLEO encapsulation" - Al2O3 is aluminum oxide) is same as a material of the first metal-containing dielectric layer.
Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention to integrate the same material as the metal containing dielectric material, aluminum oxide, for the encapsulation layer of Keuning into Okamoto, Kurokawa, Yamazaki-2500, and Lee.
An ordinary artisan would have been motivated to use the know technique of Keuning in the manner set forth above for to produce the predictable results as stated above in claim 9.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Okamoto in view of Lee.
Regarding independent claim 11, Okamoto teaches
(Currently amended) A method for fabricating ([0120] - "a method for
manufacturing a semiconductor device with high productivity can be provided") an integrated circuit device (5400 - Fig. 24J - [0509] - "ICD main unit"), comprising:
forming a first transistor (300 - Fig. 13 - {[0076] - "OS FET ... also ... referred to
as a transistor"}, {[0187] - "transistor 300"}) on a semiconductor substrate (310 - Fig.
13 - [0177] - "substrate 310");
forming a gate contact plug (328 – [0196] – “the conductor 328 and the conductor 330 have a function of a plug or a wiring”) on a gate of the first transistor (300);
depositing a first aluminum oxide layer (322 - Fig. 13 - [0189] - "For the insulator 322 ... aluminum oxide can be used") over the first transistor (300);
forming first vias (Fig. 13 – [0196] – “A conductor 328, a conductor 330, and the like that are connected to the capacitor 600 or the transistor 500 are embedded in the insulator 320, the insulator 322, the insulator 324, and the insulator 326” – 328 is contained in a via, hereinafter ‘V1’ – Fig. 14C annotated, see below) in the first aluminum oxide layer (322 – Fig. 13 – [0189] – “For the insulator 322 … aluminum oxide … can be used”), wherein one of the first vias (V1) in the first aluminum oxide layer (322) is directly above the gate of the first transistor (300) and spaced apart (Fig. 15 shows the gate of the transistor 300 only contact the via plug 328 as the gate has insulating layers around the sides thus it is spaced apart from 322) from the gate of the first transistor (300 – Fig. 13 shows this) by the gate contact plug (328), wherein in a cross-sectional view, an interface formed by said one of the first vias and an entire sidewall of the first aluminum oxide layer (322) is aligned with a sidewall of the gate contact plug (328) wherein the first vias are entirely embedded in the first aluminum oxide layer (322); and
after forming the first vias (V1) in the first aluminum oxide layer (322),
forming a second transistor (500 - Fig. 13 - [0176] - "The transistor 500 is provided
above the transistor 300") over the first aluminum oxide layer (322).
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Okamoto does not expressly disclose the other limitations of claim 11.
However, in an analogous art, Lee teaches
wherein in a cross-sectional view, an interface formed by said one of the first vias (Fig. 1D annotated, see below – hereinafter ‘V1’) and an entire sidewall of the first aluminum oxide layer is aligned (Fig. 1D alignment of features) with a sidewall of the gate contact plug wherein the first vias (V1) are entirely embedded in the first aluminum oxide layer.
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Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to substitute the alignment of structure of Lee into Okamoto.
An ordinary artisan would have been motivated to use the known technique of Lee in the manner set forth above to produce the predictable results as stated above in claim 1.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Okamoto in
view of Lee, Yamazaki-2500 and Yamazaki et al. (US 20240013829 A1 – hereinafter Yamazaki-3829).
Regarding dependent claim 12, Okamoto, as modified by Lee, teaches claim 11 from which claim 12 depends. Okamoto and Lee do not expressly disclose the limitations of claim 12.
However, in analogous art, Yamazaki-2500 teaches
(Original) The method of claim 11, wherein the first aluminum oxide layer (118-Fig. 19E- [0359] - "The insulator ... an aluminum oxide film" - this is the first aluminum oxide layer over the dielectric layer forming the transistor") is deposited by a radio frequency (RF) sputter process ([0359] - "the insulator 118 ... may be formed by an RD sputtering method").
It would have been obvious to one of ordinary skill in the art before the effective
filing date of the invention to integrate the first aluminum oxide layer to be deposited by a RF sputter of Yamazaki-2500 into Okamoto and Lee.
An ordinary artisan would have been motivated to use the know technique of Yamazaki-2500 in the manner set forth above for to produce the predictable results of [0026 ] – “so that at least part of the third insulator is in contact with the first insulator.”
To do so would have merely been to apply a known technique to a known device
ready for improvement to yield predictable results, KSR lnt'I Co. v. Teleflex Inc., 550
U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Okamoto, Lee, and Yamazaki-2500 do not expressly disclose the other limitations of claim 12.
However, in analogous art, Yamazaki-3829 teaches
without using a hydrogen-containing precursor ([0214] - "the insulator 214
... can be formed by a sputtering method" and "a sputtering method does not need to
use a molecule containing hydrogen").
It would have been obvious to one of ordinary skill in the art before the effective
filing date of the invention for integrate the first aluminum oxide layer to be deposited by a process without using a hydrogen-containing precursor technique of Yamazaki-3829 into Okamoto, Lee, and Yamazaki-2500.
An ordinary artisan would have been motivated to use the know technique of Yamazaki-3829 in the manner set forth above for to produce the predictable results
to reduce the hydrogen concentrations in the insulator (aluminum oxide).
To do so would have merely been to apply a known technique to a known device
ready for improvement to yield predictable results, KSR lnt'I Co. v. Teleflex Inc., 550
U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Okamoto in
view of Lee and Kurokawa.
Regarding claim 14, Okamoto, as modified by Lee, teaches claim 11 from which claim 14 depends. Okamoto further teaches
(Original) The method of claim 11, further comprising:
depositing a second aluminum oxide layer (574 - Fig. 13 - [0257] - "aluminum oxide ... is preferably used for ... the insulator 574") over the second transistor (500);
forming second vias (546 - Fig. 13 - [0340] - "a conductor 546") in the second
aluminum oxide layer (574); and
after forming the second vias (546) in the second aluminum oxide layer (574), forming a third transistor over the second aluminum oxide layer (574).
Okamoto and Lee do not expressly disclose the limitations of claim 14.
However, in an analogous art, Kurokawa teaches
forming a third transistor (104, 111, 112, 113 - Fig. 5 - {[29:1] - "transistor
104"}, {[29:16-20] - "the transistor 111 ... over ... the transistor 112 ... over ... the
transistor 113"}) over the second metal-containing dielectric layer.
Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate the second TFT (transistor) over the second metal-containing dielectric layer structure of Kurokawa into Okamoto and Lee.
An ordinary artisan would have been motivated to use the know technique of Kurokawa in the manner set forth above for to produce the predictable results of stacking a third transistor over the preceding two transistors to reduce the area of the chip [29:21-24] - "In this manner, the plurality of transistors included in the D/A converter are stacked alternately with interlayer films, so that the area of the memory cell can be reduced."
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Okamoto in
view of Lee, Kurokawa, and Keuning.
Regarding claim 15, Okamoto, as modified by Lee, and Kurokawa, teaches claim 14 from which claim 15 depends. Okamoto further teaches
(Original) The method of claim 14, further comprising:
encapsulating the first (300), second (500), and third transistors in a third
aluminum oxide layer.
Okamoto and Lee do not expressly disclose the other limitations of claim 15.
However, in an analogous art, Kurokawa teaches
and third transistors (104, 111, 112, 113 - Fig. 5 - {[29 - 1] - "transistor 104"},
{[29 - 16-20] - "the transistor 111 ... over ... the transistor 112 ... over ... the transistor
113"}).
Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate a third transistor of Kurokawa into Okamoto and Lee.
An ordinary artisan would have been motivated to use the know technique of Kurokawa in the manner set forth above for to produce the predictable results of stacking a third transistor over the preceding two transistors to reduce the area of the chip as Kurokawa states [29:21-24] - "In this manner, the plurality of transistors included in the D/A converter are stacked alternately with interlayer films, so that the area of the memory cell can be reduced".
Okamoto, Lee and Kurokawa do not expressly disclose the other limitations of claim 15.
However, in an analogous art, Keuning teaches
in a third aluminum oxide layer (pp.01 A 131 -[0004] - "In this respect, atomic
layer deposition (ALO) is of interest as it is a technique which is known for its conformal
deposition over 30 structures ... for ... encapsulation") encapsulating the chip, wherein
the encapsulation layer comprises a metal-containing dielectric material (pp.01 A 131 -
[0004] - "Several studies have already shown that Al2O3 synthesized by ALO is a
promising candidate for OLEO encapsulation").
Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate the third aluminum oxide layer of Keuning into Okamoto, Lee and Kurokawa.
An ordinary artisan would have been motivated to use the know technique of Keuning in the manner set forth above for to produce the predictable results as stated above in claim 9.
Claims 16, 17, 20, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Okamoto in view of Kurokawa, Yamazaki-2500, Lee, and Tochibayashi et al. (US 20170263651 A1 – hereinafter Tochibayashi).
Regarding independent claim 16, Okamoto teaches
(Currently amended) An integrated circuit device (5400 - Fig. 24J –
[0509] - "ICD main unit"), comprising:
a semiconductor substrate (310 - Fig. 13 - [0177] - "substrate 310");
a field effect transistor (FET) (300 - Fig. 13 - {[0076] - "OS FET ... also ...
referred to as a transistor"}, {[0187] - "transistor 300"}) on the semiconductor substrate (310);
a gate contact plug (328 – [0196] – “the conductor 328 and the conductor 330
have a function of a plug or a wiring”) disposed on a gate of the FET;
a first metal oxide layer (322 - Fig. 13 - [0189] - "For the insulator 322 ...
aluminum oxide can be used") over the FET (300) and spaced apart from the gate of the FET by the gate contact plug (328);
first metal vias extending through the first metal oxide layer, wherein in a cross-sectional view, an interface formed by an entire sidewall of the first metal oxide layer and on of the first metal vias is aligned with a sidewall of the gate contact plug (328) wherein the first metal vias are entirely embedded in the first metal oxide layer;
a first thin film transistor (TFT) (500 - Fig. 13 - [0176] "The transistor 500 is
provided above the transistor 300" - a TFT is a transistor type) over the first metal oxide layer (322), the first TFT (500) being spaced apart (Fig. 13 shows this) from the FET (300) at least in part by the first metal oxide layer (322);
a second metal oxide layer (581 - Fig. 13 - [0257] - "the insulator 581, for example, aluminum oxide") over the first TFT (500 - Fig. 13 - [0176] "The transistor 500 is provided above the transistor 300" - a TFT is a transistor type); and
second metal vias (546 - Fig. 13 - [0340] - "a conductor") extending through the second metal oxide layer (581), wherein the second metal vias (546) are in contact with the second metal oxide layer.
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Okamoto does not expressly disclose the other limitations of claim 16.
However, in analogous art, Kurokawa teaches
spaced apart (Fig. 6C shows this) from the gate (Fig. 6C annotated, see below – hereinafter ‘G’) of the FET (104 – Fig. 6C – [21 = 4-26] – “amplifier transistor 104”).
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944
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Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate the spacing structure of
Kurokawa into Okamoto.
An ordinary artisan would have been motivated to use the known technique of Kurokawa in the manner set forth above to produce the predictable results of [2:45-
52] - "The parasitic resistance of a wiring which is electrically connected to the transistor can be used as the resistor of the D/A converter. Transistors can be stacked alternately with interlayer films and the parasitic resistance of a conductive material provided in a contact hole formed in the interlayer film can be used as the resistor, for example. Thus, the area of the resistor can be reduced and the area of the memory cell per bit can be reduced."
Okamoto and Kurokawa do not expressly disclose the other limitations of claim 16.
However, in analogous art, Yamazaki-2500 teaches
wherein the second metal vias are in contact (498c – Fig. 35 – [0543] – “The insulator 494 includes an opening reaching the conductor 496a, an opening reaching the conductor 496b and the conductor 496d, and an opening reaching the conductor 496c. In the openings, the conductor 498a, the conductor 498b, and the conductor 498c are embedded”) with the second metal (494 – Fig. 35 – {[0544] – “494 may each be formed to have, for example, a single-layer structure or a stacked-layer structure including an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum”}, {[0545] – “The insulator that has a function of blocking oxygen and impurities such as hydrogen is preferably included in at least one of the insulators 464, 466, 468, 489, 493, and 494”} – the second metal layer, 494, has a function of blocking oxygen) oxide layer.
Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate the second metal via structure of Yamazaki-2500 into Okamoto and Kurokawa.
An ordinary artisan would have been motivated to use the known technique of Yamazaki-2500 in the manner set forth above to produce the predictable results of
[0004] – “A technique for forming a transistor by using a semiconductor over a substrate having an insulating surface has attracted attention. The transistor is applied to a wide range of semiconductor devices such as an integrated circuit and a display device.”
Okamoto, Kurokawa, and Yamazaki-2500 do not expressly disclose the other limitations of claim 16.
However, in analogous art, Lee teaches
first metal vias (lee (Fig. 2B annotated, see below – hereinafter ‘V1-1’) extending through the first metal oxide layer (212 – Fig. 2B – [4:57-59] – “material layer 212 is an oxide material, such as a first transition metal containing dielectric oxide”), wherein in a cross-sectional view, an interface formed by an entire sidewall of the first metal oxide layer (212) and on of the first metal vias (V1-1) is aligned (Fig. 2B shows alignment of features) with a sidewall of the gate contact plug wherein the first metal vias (V1-1) are entirely embedded in the first metal oxide layer (212).
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Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to substitute the alignment structure of Lee into Okamoto, Kurokawa, and Yamazaki-2500.
An ordinary artisan would have been motivated to use the known technique of Lee in the manner set forth above to produce the predictable results as stated above in claim 1.
Okamoto, Kurokawa, Yamazaki-2500, and Lee do not expressly disclose the other limitations of claim 16.
However, in analogous art, Tochibayashi teaches
oxide layer ({282 – Fig. 35 – [0401] – “The insulator 280 covering the transistor 100 may function as a planarization film that covers a roughness thereunder. An insulator 282, an insulator 284, and an insulator 110 are stacked sequentially over the insulator 280”}, {[0402] – “material having a barrier property against oxygen or hydrogen is preferably used for one or all of the insulator 282, the insulator 284, and the insulator 110. Thus, the insulator 282 can be formed using a material similar to that used for forming the insulator 212. The insulator 284 can be formed using an insulator similar to that used for forming the insulator 212. The insulator 110 can be formed using a material similar to that used for forming the insulator 216”}, {[0391] – “insulators 358 and 212 can be formed using a material similar to that used for forming the insulator 324”}, {[0379] – “insulator 324, and the insulator 326 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide” – a material that has a function of blocking oxygen can be made of aluminum oxide, Yamasaki’s element 494 has a function of blocking oxygen, therefore 494 can be formed using aluminum oxide).
Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to substitute oxide layer of the second metal structure of Tochibayashi into Okamoto, Kurokawa, Yamazaki-2500, and Lee.
An ordinary artisan would have been motivated to use the known technique of Tochibayashi in the manner set forth above to produce the predictable results of [0402] – “material having a barrier property against oxygen or hydrogen.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 17, Okamoto, as modified by Kurokawa, Yamazaki-2500, Lee, and Tochibayashi, teaches claim 16 from which claim 17 depends. Okamoto further teaches
(Original) The integrated circuit device of claim 16, further comprising:
an encapsulation layer (4711 - Fig. 23C - [0464] - "The electronic component 4700 illustrated in FIG. 23C includes a chip 4800a in a mold 4711" - 4800a is one chip diced from the wafer, the encapsulation layer is the mold) encapsulating the FET (300) and the first TFT (500).
Regarding claim 20, Okamoto, as modified by Kurokawa, Yamazaki-2500, Lee, and Tochibayashi, teaches claim 16 from which claim 20 depends. Okamoto further teaches
the second metal oxide layer (581),
the first TFT (300) at least in part by the second metal oxide layer (581).
Okamoto, Yamazaki-2500, Lee, and Tochibayashi do not expressly disclose the limitations of claim 20.
However, in an analogous art, Kurokawa teaches
(Previously presented) The integrated circuit device of claim 16, further
comprising:
a second TFT (104 – Fig. 5 - {[29:1] - "transistor 104"}, {[29:16-20] - "the transistor 111 ... over ... the transistor 112 ... over ... the transistor 113"}) over the second metal oxide layer, the second TFT (104) being spaced apart ([29:21-23] - "In this manner, the plurality of transistors included in the D/A converter are stacked alternately with interlayer films") from the first TFT at least in part by the second metal oxide layer.
Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate the second transistor structure of Kurokawa into Okamoto, Yamazaki-2500, Lee, and Tochibayashi.
An ordinary artisan would have been motivated to use the know technique
of Kurokawa in the manner set forth above to produce the predictable result of stacking a third transistor over the preceding two transistors to reduce the area of the chip [29:21-24] - "In this manner, the plurality of transistors included in the D/A converter are stacked alternately with interlayer films, so that the area of the memory cell can be reduced."
Regarding claim 22, Okamoto, as modified by Kurokawa, Yamazaki-2500, Lee, and Tochibayashi, teaches claim 16 from which claim 22 depends. Okamoto, Kurokawa, Lee, and Tochibayashi do not expressly disclose the limitations of claim 22.
However, in an analogous art, Yamazaki-2500 teaches
(Previously presented) The integrated circuit device of claim 16, wherein a
top surface of one of the second metal vias (498c) abuts a top surface of the second metal oxide layer (494 – Fig. 35 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate the second metal via and metal oxide layer structure of Yamazaki-2500 into Okamoto and Kurokawa.
An ordinary artisan would have been motivated to use the known technique of Yamazaki-2500 in the manner set forth above to produce the predictable results of as stated above in claim 16.
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Okamoto in view of Kurokawa, Yamazaki-2500, Tochibayashi, and Keuning.
Regarding claim 18, Okamoto, as modified by Kurokawa, Yamazaki-2500, Lee, and Tochibayashi, teaches claim 17 from which claim 18 depends. Okamoto further teaches
(Original) The integrated circuit device of claim 17, wherein the
encapsulating layer (4711 - Fig. 23C - [0464] - "The electronic component 4700 illustrated in FIG. 23C includes a chip 4800a in a mold 4711" - 4800a is one chip diced from the wafer, the encapsulation layer is the mold) is made of a same material as the first metal oxide layer (322 - Fig. 13 - [0189] - "For the insulator 322 ... aluminum oxide can be used") is made of aluminum oxide.
Okamoto, Kurokawa, Yamazaki-2500, Lee, and Tochibayashi, do not expressly disclose the other limitations of claim 22.
However, in an analogous art, Keuning teaches
the encapsulating layer is made of a same material (pp.01 A 131 - [0004] -
"Several studies have already shown that Al2O3 synthesized by ALD is a promising
candidate for OLEO encapsulation") as the first metal oxide layer.
Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate the same material for the encapsulation layer structure of Keuning into Okamoto, Kurokawa, Yamazaki-2500, Lee, and Tochibayashi.
An ordinary artisan would have been motivated to use the know technique of Keuning in the manner set forth above for to produce the predictable results of avoiding/reducing hydrogen and/or moisture diffusion through the encapsulation and into the chip as Keuning teaches in the [Abstract] - "On the basis of Ca test measurements, a very low intrinsic water vapor transmission rate ... were found for 20--40 nm Al2O3."
Regarding claim 19, Okamoto, as modified by Kurokawa, Yamazaki-2500, Lee, and Tochibayashi, teaches claim 17 from which claim 19 depends. Okamoto further teaches
(Original) The integrated circuit device of claim 17, wherein the
encapsulating layer (4711) is made of aluminum oxide.
Okamoto, Kurokawa, Yamazaki-2500, Lee, and Tochibayashi, do not expressly disclose the other limitations of claim 17.
However, in an analogous art, Keuning teaches
the encapsulating layer is made of aluminum oxide (pp.01 A 131 - [0004] -
"Several studies have already shown that Al2O3 synthesized by ALD is a promising
candidate for OLEO encapsulation").
Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate aluminum oxide for the encapsulation layer structure of Keuning into Okamoto, Kurokawa, Yamazaki-2500, Lee, and Tochibayashi.
An ordinary artisan would have been motivated to use the know technique of Keuning in the manner set forth above for to produce the predictable results as stated above in claim 18.
Pertinent Art
For the benefits of the Applicant, US 20220013412 A1, US 20220102343 A1 are
cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the combination of limitations including "spaced apart".
Conclusion
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/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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