Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Remarks/Present Status of the Application
The Examiner acknowledges and generally agrees with the applicant’s summary of the application’s status of the application.
Amendments
The Examiner acknowledges that the applicant has amended paragraphs of the specification, as well as amended claims 9-16.
Drawing Objection
The Examiner acknowledges and has fully considered the applicant’s arguments regarding the drawing objection. The Examiner withdraws the drawing objection due to the applicant’s arguments.
Specification Objection
The Examiner acknowledges the applicant’s amendments regarding the applicant’s specification to correct informalities. The Examiner withdraws the specification objection due to the amendments to the specification.
35 U.S.C. 112(b) Rejection
The Examiner acknowledges the applicant’s amendments regarding claims 9-16, and withdraws the 112(b) rejections on claims 9-16 due to the amendments. See new grounds of rejection below, necessitated by amendment.
35 U.S.C. 103 Rejection
The Examiner acknowledges and fully acknowledges the applicant’s arguments. The applicant seemingly asserts, in Remarks page 15 paragraph 4, that the combination of the prior art, Chang et al (U.S Patent Application Publication 2021/0125663 A1), hereinafter “Chang”, in view of Jung et al. (U.S Patent Application Publication 2022/0114427 A1), hereinafter “Jung”, and in further view of Maejima et al. (U.S Patent Application Publication 2007/0210853 A1), hereinafter “Maejima”, fails to teach or suggest all of the recited claim limitations of claim 1. The Examiner respectfully disagrees for at least the reasons listed in the Non-Final Rejection Office Action mailed on 09/10/2025.
The Applicant further argues, in Remarks page 15 paragraph 5 and page 16 paragraphs 1-2, in regards to the applicant’s claim 1 limitation of resistors coupled between the first end of input transistors and a common signal line, that the prior art of Chang does not teach or suggest a resistor coupled between input transistors and a common signal line, and furthermore that Chang in view of Jung does not teach or suggest the above mentioned limitations seemingly due to the resistors of Jung being used as part of a memory cell and not a discrete passive resistor added to a computing circuit for being applied to transposable units outside the memory cell, the applicant argues that from this the combination of Jung with Chang is unreasonable. The Examiner respectfully disagrees for at least the reasons mentioned in the Non-Final Rejection Office Action mailed on 09/10/2025, page 7. The applicant’s specification, paragraph [0009] states, “achieves the function of the multiply accumulate computation by cascading the weight transistor, the input transistor, and the resistor, and setting the resistance value of different resistors”, and further states, “cascading the weight transistor and different numbers of input transistors, the function of the multiply accumulate computation is achieved”. Furthermore, in the applicant’s specification, paragraph [0019] states, “use resistors with different impedance values to achieve a total current for different computations”. Furthermore, in the applicant’s specification, paragraph [0024] states: “a resistance value of the resistor R11 is different from a resistance value of the resistor R01. Therefore, a total current flowing through the first readout bit line R RBL<0> reflects a sum of a weight product of the first weight bit WO and bit transmitted by the input bit line INBL_2 (that is, a logic level) and a weight product of the first weight bit WO and the bit transmitted by the input bit line INBL_3”. Furthermore in the applicant’s specification, paragraph [0046] states, “the number of the transistors M22 is different from the number of the transistors M21. Therefore, the total current flowing through the first readout bit line R RBL<0> reflects the sum of the weight product of the first weight bit WO and the bit transmitted by the input bit line INBL_2 (that is, the logic level) and the weight product of the first weight bit WO and the bit transmitted by the input bit line INBL_3”. The applicant’s specification has different embodiments of the invention, one seemingly using resistors as a change way to have different impedance values to achieve a total current for different computations, and one seemingly using different number transistors (interpreted by the Examiner to mean different widths, which would cause different impedances between transistors). The applicant’s specification discussing the different embodiments, one using different number transistors and one using different resistance level resistors, seemingly implies that changing out a different number transistor with a resistor in series with the transistor instead would be a simple substitution of one known element for another to obtain predictable results. The Examiner merely uses the combination of Chang in view of Jung to show that these components may be simple substitutions of one another, which the applicant seemingly acknowledges based on the applicant’s specification’s description of the different embodiments of the invention.
The applicant further argues, in Remarks page 16 paragraph 3, that the combination of Maejima is impractical and lacks reasonable basis. The Examiner respectfully disagrees. As discussed above, the Examiner merely uses the combination of Chang in view of Jung to show that the components of different width transistors may be replaced by a transistor in series with a resistor. As discussed above, the Examiner notes that the applicant seemingly shows this simple substitution of components in the applicant’s specification. Regarding the combination of Chang in view of Jung and in further view of Maejima, the Examiner points to the Non-Final Office Action mailed on 09/10/2025, page 8 paragraph 1 regarding the motivation to combine, where the different resistive values of Maejima allow the current to vary (Maejima: [0062]), which is similar to that of what the applicant states in the applicant’s specification paragraph [0019] states, “use resistors with different impedance values to achieve a total current for different computations”.
The applicant further argues, in reparks page 16 paragraph 4 to page 17 paragraph 2, that Jung’s resistor in combination of Chang is a hybridization of fundamentally distinct architectures, furthermore adding that Maejima’s resistor array in combination compounds incompatibility and that one of ordinary skill in the art would lack any motivation to combine. The Examiner respectfully disagrees. As discussed above, the Examiner merely uses the combination of Chang in view of Jung to show that the components of different width transistors may be replaced by a transistor in series with a resistor. Furthermore, Jung, paragraph [0019] discusses the invention computing multiply accumulate results based on output summation current, [0056] discusses in-memory computing circuitry integrating memory for performing MAC (Multiply Accumulate) operations, [0078]-[0079] discuss Fig. 4A and computations made by the circuitry, including current summation, which as shown in [0019] is used for MAC operations. Furthermore, as discussed above, the Examiner notes that the applicant seemingly shows a simple substitution of components in the applicant’s specification between resistors and different number transistors. As discussed above, regarding the combination of Chang in view of Jung and in further view of Maejima, the Examiner points to the Non-Final Office Action mailed on 09/10/2025, page 8 paragraph 1 regarding the motivation to combine, where the different resistive values of Maejima allow the current to vary (Maejima: [0062]), which is similar to that of what the applicant states in the applicant’s specification paragraph [0019] states, “use resistors with different impedance values to achieve a total current for different computations”.
The applicant continues, in Remarks page 17 paragraph 3, by asserting that for the arguments discussed above, claim 1 is non-obvious and patentable over the cited prior art, and that claims 2-4 would to be considered non-obvious based on dependence to claim 1. For at least the reasons listed above, the Examiner respectfully disagrees.
Allowable Subject Matter
The applicant recites claims which were indicated as allowable subject matter in the Non-final Office Action mailed on 09/10/2025. The Examiner acknowledges the amendments made to claims 9-16 to overcome the 112(b) rejections, and as mentioned above, the Examiner withdraws the 112(b) rejections to claims 9-16 due to these amendments. The applicant asserts that the subject matter of claims 5-16 remains unchanged in the amended claims, thus the indication of allowance should be maintained. The Examiner respectfully disagrees. The specific reason of indication of allowable subject matter in regards to claim 5, as shown in the Non-Final Office Action mailed on 09/10/2025, was due to the claim limitation in claim 5 being “a seventh weight transistor having a first end coupled to the second end of the third input transistor”, whereas the amended claim 5 limitation recites: “a seventh weight transistor having a first end coupled to the second end of the seventh input transistor,” this is a fundamentally different structure of previously claimed invention and thus not the same indicated allowable subject matter, thus the indicated allowable subject matter of claims 5-8 is revoked. See new grounds of rejection below, necessitated by amendment.
Claim Objections
Claim 13 objected to because of the following informalities:
Claim 13, page 10 line 8, appears to have a grammatical error and should be changed to: “[[a]] an eighth input transistor”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 9, claim 9 recites the limitations of: “a first input transistor”, and “a second input transistor”, and “wherein a number of the first input transistor is different from a number of the second input transistor.” Both the first input transistor and the second input transistor are described as being singular objects, but then described as having a number of a first input transistor different than that of the second input transistor. It is unclear if the limitation is meant to be understood as multiple transistors for either the first input transistor or second input transistor with the number of transistors differing, or, since the claim is seemingly indicating a singular first input transistor and a singular second input transistor, if it is meant to be understood as the number, as in size or width, of the two transistors differ. For purposes of examination, the Examiner interprets the claim limitation as, “wherein a width of the first input transistor is different from a width of the second input transistor”.
Claims 10-16 inherit the same deficiency as claim 9 based on dependance.
Regarding claim 10, claim 10 recites the limitation of: “wherein the number of the second input transistor is 2 to the power of n times the number of the first input transistor”. Similarly to claim 9 above, both the first input transistor and the second input transistor are described as being singular objects, but then described as having a number of a first input transistor different than that of the second input transistor. It is unclear if the limitation is meant to be understood as multiple transistors for either the first input transistor or second input transistor with the number of transistors differing, or, since the claim is seemingly indicating a singular first input transistor and a singular second input transistor, if it is meant to be understood as the number, as in size or width, of the two transistors differ. For purposes of examination, the Examiner interprets the claim limitation as, “wherein the width of the second input transistor is 2 to the power of n times the width of the first input transistor”.
Regarding claim 11, claim 11 recites the limitations of: “a third input transistor”, and “a fourth input transistor”, and “wherein a number of the third input transistor is different from a number of the fourth input transistor.” Both the third input transistor and the fourth input transistor are described as being singular objects, but then described as having a number of a third input transistor different than that of the fourth input transistor. It is unclear if the limitation is meant to be understood as multiple transistors for either the third input transistor or fourth input transistor with the number of transistors differing, or, since the claim is seemingly indicating a singular third input transistor and a singular fourth input transistor, if it is meant to be understood as the number, as in size or width, of the two transistors differ. For purposes of examination, the Examiner interprets the claim limitation as, “wherein a width of the third input transistor is different from a width of the fourth input transistor”.
Claims 12-16 inherit the same deficiency as claim 11 based on dependance.
Regarding claim 12, claim 12 recites the limitations of: “wherein the number of the second input transistor is 2 to the power of n times the number of the first input transistor”, and “the number of the fourth input transistor is 2 to the power of n times the number of the third input transistor”. Both the first input transistor and the second input transistor are described as being singular objects, but then described as having a number of a first input transistor different than that of the second input transistor. It is unclear if the limitation is meant to be understood as multiple transistors for either the first input transistor or second input transistor with the number of transistors differing, or, since the claim is seemingly indicating a singular first input transistor and a singular second input transistor, if it is meant to be understood as the number, as in size or width, of the two transistors differ. Also, both the third input transistor and the fourth input transistor are described as being singular objects, but then described as having a number of a third input transistor different than that of the fourth input transistor. It is unclear if the limitation is meant to be understood as multiple transistors for either the third input transistor or fourth input transistor with the number of transistors differing, or, since the claim is seemingly indicating a singular third input transistor and a singular fourth input transistor, if it is meant to be understood as the number, as in size or width, of the two transistors differ. For purposes of examination, the Examiner interprets the limitations as, “wherein the width of the second input transistor is 2 to the power of n times the width of the first input transistor, the width of the fourth input transistor is 2 to the power of n times the width of the third input transistor”.
Regarding claim 13, claim 13 recites the limitations of: “a fifth input transistor”, and “a sixth input transistor”, and “a seventh input transistor”, and “an eighth input transistor”, and “wherein a number of the fifth input transistor is different from a number of the sixth input transistors”, and “a number of the seventh input transistor is different from a number of the eighth input transistor”. Both the fifth input transistor and the sixth input transistor are described as being singular objects, but then described as having a number of a fifth input transistor different than that of the sixth input transistor. It is unclear if the limitation is meant to be understood as multiple transistors for either the fifth input transistor or sixth input transistor with the number of transistors differing, or, since the claim is seemingly indicating a singular fifth input transistor and a singular sixth input transistor, if it is meant to be understood as the number, as in size or width, of the two transistors differ. Also, both the seventh input transistor and the eighth input transistor are described as being singular objects, but then described as having a number of a seventh input transistor different than that of the eighth input transistor. It is unclear if the limitation is meant to be understood as multiple transistors for either the seventh input transistor or eighth input transistor with the number of transistors differing, or, since the claim is seemingly indicating a singular seventh input transistor and a singular eighth input transistor, if it is meant to be understood as the number, as in size or width, of the two transistors differ. For purposes of examination, the Examiner interprets the limitations as, “wherein a width of the fifth input transistor is different from a width of the sixth input transistor, and a width of the seventh input transistor is different from a width of the eighth input transistor.”
Claims 14-16 inherit the same deficiency as claim 13 based on dependence.
Regarding claim 14, claim 14 recites the limitations of: “wherein the number of the second input transistor is 2 to the power of n times the number of the first input transistor”, and “the number of the fourth input transistor is 2 to the power of n times the number of the third input transistor”, and “the number of the sixth input transistor is 2 to the power of n times the number of the fifth input transistor”, and “the number of the eighth input transistor is 2 to the power of n times the number of the seventh input transistor”. Both the first input transistor and the second input transistor are described as being singular objects, but then described as having a number of a first input transistor different than that of the second input transistor. It is unclear if the limitation is meant to be understood as multiple transistors for either the first input transistor or second input transistor with the number of transistors differing, or, since the claim is seemingly indicating a singular first input transistor and a singular second input transistor, if it is meant to be understood as the number, as in size or width, of the two transistors differ. Also, both the third input transistor and the fourth input transistor are described as being singular objects, but then described as having a number of a third input transistor different than that of the fourth input transistor. It is unclear if the limitation is meant to be understood as multiple transistors for either the third input transistor or fourth input transistor with the number of transistors differing, or, since the claim is seemingly indicating a singular third input transistor and a singular fourth input transistor, if it is meant to be understood as the number, as in size or width, of the two transistors differ. Furthermore, both the fifth input transistor and the sixth input transistor are described as being singular objects, but then described as having a number of a fifth input transistor different than that of the sixth input transistor. It is unclear if the limitation is meant to be understood as multiple transistors for either the fifth input transistor or sixth input transistor with the number of transistors differing, or, since the claim is seemingly indicating a singular fifth input transistor and a singular sixth input transistor, if it is meant to be understood as the number, as in size or width, of the two transistors differ. Also, both the seventh input transistor and the eighth input transistor are described as being singular objects, but then described as having a number of a seventh input transistor different than that of the eighth input transistor. It is unclear if the limitation is meant to be understood as multiple transistors for either the seventh input transistor or eighth input transistor with the number of transistors differing, or, since the claim is seemingly indicating a singular seventh input transistor and a singular eighth input transistor, if it is meant to be understood as the number, as in size or width, of the two transistors differ. For purposes of examination, the Examiner interprets the claim limitations as, “wherein the width of the second input transistor is 2 to the power of n times the width of the first input transistor, the width of the fourth input transistor is 2 to the power of n times the width of the third input transistor, the width of the sixth input transistor is 2 to the power of n times the width of the fifth input transistor, the width of the eighth input transistor is 2 to the power of n times the width of the seventh input transistor, and n is a positive integer greater than or equal to 1.”
Regarding claim 15, claim 15 recites the limitations of: “wherein the number of the fifth input transistor is 2 to the power of n times the number of the first input transistor, the number of the sixth input transistor is 2 to the power of n times the number of the second input transistor, the number of the seventh input transistor is 2 to the power of n times the number of the third input transistor, the number of the eighth input transistor is 2 to the power of n times the number of the fourth input transistor”. The fifth input transistor and the first input transistor are described as being singular objects, but then described as having a number of a fifth input transistor different than that of the first input transistor. It is unclear if the limitation is meant to be understood as multiple transistors for either the fifth input transistor or first input transistor with the number of transistors differing, or, since the claim is seemingly indicating a singular fifth input transistor and a singular first input transistor, if it is meant to be understood as the number, as in size or width, of the two transistors differ. Furthermore, the sixth input transistor and the second input transistor are described as being singular objects, but then described as having a number of a sixth input transistor different than that of the second input transistor. It is unclear if the limitation is meant to be understood as multiple transistors for either the sixth input transistor or second input transistor with the number of transistors differing, or, since the claim is seemingly indicating a singular sixth input transistor and a singular second input transistor, if it is meant to be understood as the number, as in size or width, of the two transistors differ. Furthermore, the seventh input transistor and the third input transistor are described as being singular objects, but then described as having a number of a seventh input transistor different than that of the third input transistor. It is unclear if the limitation is meant to be understood as multiple transistors for either the seventh input transistor or third input transistor with the number of transistors differing, or, since the claim is seemingly indicating a singular seventh input transistor and a singular third input transistor, if it is meant to be understood as the number, as in size or width, of the two transistors differ. Furthermore, the eighth input transistor and the fourth input transistor are described as being singular objects, but then described as having a number of an eighth input transistor different than that of the fourth input transistor. It is unclear if the limitation is meant to be understood as multiple transistors for either the eighth input transistor or fourth input transistor with the number of transistors differing, or, since the claim is seemingly indicating a singular eighth input transistor and a singular fourth input transistor, if it is meant to be understood as the number, as in size or width, of the two transistors differ. For purposes of examination, the Examiner interprets the claim limitation as, “wherein the width of the fifth input transistor is 2 to the power of n times the width of the first input transistor, the width of the sixth input transistor is 2 to the power of n times the width of the second input transistor, the width of the seventh input transistor is 2 to the power of n times the width of the third input transistor, the width of the eighth input transistor is 2 to the power of n times the width of the fourth input transistor”.
Regarding claim 16, claim 16 recites the limitations of: “wherein a ratio of the number of the second input transistor to the number of the first input transistor is different from a ratio of the number of the sixth input transistor to the number of the fifth input transistor, and a ratio of the number of the fourth input transistor to the number of the third input transistor is different from a ratio of the number of the eighth input transistor to the number of the seventh input transistor”. The second input transistor, first input transistor, sixth input transistor, fifth input transistor, fourth input transistor, third input transistor, eighth input transistor and seventh input transistor all are described as singular objects respectively, but then each is described as having a number of these respective transistors differing in ratio in relation to other singular transistors. For that reasons it is unclear if it is meant to be understood as there are multiple transistors for any of or all of the respective first through eighth input transistors, or if it is meant to be understood as their respective number, as in size or width, is what is being referred to in the claim limitations instead. For purposes of examination, the Examiner interprets the claim limitations as, “wherein a ratio of the width of the second input transistor to the width of the first input transistor is different from a ratio of the width of the sixth input transistor to the width of the fifth input transistor, and a ratio of the width of the fourth input transistor to the width of the third input transistor is different from a ratio of the width of the eighth input transistor to the width of the seventh input transistor”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Chang (U.S Patent Application Publication 2021/0125663 A1), hereinafter “Chang”, in view of Jung et al. (U.S Patent Application Publication 2022/0114427 A1), hereinafter “Jung”, and in further view of Maejima et al. (U.S Patent Application Publication 2007/0210853 A1), hereinafter “Maejima”.
With regards to claim 1, Chang teaches:
A configurable computing unit within memory, (Fig. 7);
comprising: a first input transistor having a first end, (Fig. 7 item M8 (as a first input transistor));
a control end coupled to a first input bit line, (Fig. 7 item M8 (as a first input transistor, with control end connected to Input<2> as a first input bit line));
and a second end; (Fig. 7 item 8 (as a first input transistor));
a first weight transistor having a first end coupled to the second end of the first input transistor, (Fig. 7 items M7 (as a first weight transistor), M8 (as a first input transistor connected to M7));
a control end receiving a first weight bit, (Fig. 7 items M7 (as a first weight transistor), LBL (as a first weight bit line));
and a second end coupled to a first readout bit line; (Fig. 7 items M7 (as a first weight transistor connected to HGBL), HGBL (as a first readout bit line); [0037] regarding HGLB as an output bit line);
a first input transistor the first end of the first input transistor and a common signal line; (Fig. 7 item M8 (as a first input transistor), Ground (as a common signal line));
a second input transistor having a first end, (Fig. 7 item M4 (as a second input transistor));
a control end coupled to a second input bit line, (Fig. 7 item M4 (as a second input transistor with control end coupled to Input<3> as a second input line));
and a second end; (Fig. 7 item M4 (as a second input transistor));
a second weight transistor having a first end coupled to the second end of the second input transistor, (Fig. 7 items M3 (as a second weight transistor), M4 (as a second input transistor connected to M3));
a control end receiving the first weight bit, (Fig. 7 items M3 (as a second weight transistor), LBL (as a first weight bit line));
and a second end coupled to the first readout bit line; (Fig. 7 items M3 (as a second weight transistor connected to HGBL), HGBL (as a first readout bit line); [0037] regarding HGLB as an output bit line);
and a second input transistor the first end of the second input transistor and the common signal line, (Fig. 7 item M4 (as a second input transistor), Ground (as a common signal line));
wherein width of the second input transistor is different from width of the first input transistor. (Fig. 7 items M4, M8 with M4 having X2 as a times 2 width of M8; [0037] regarding the width of M4 being twice that of M8);
Chang does not explicitly teach:
resistor coupled between
a resistance value of the second resistor is different from a resistance value of the first resistor
However, Jung teaches:
resistor coupled between (Fig. 7A regarding a resistor in series with a transistor coupled between the transistor and a common signal line)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Chang with the resistor of Chang because [Jung: [0044]] Jung teaches that the resistive elements is for corresponding to a data value, using the resistor in series with the transistor instead of the transistors of different widths would then be a simple substitution of one known element for another to obtain predictable results [MPEP 2141 (III)(B)].
Chang in view of Jung does not explicitly teach:
a resistance value of the second resistor is different from a resistance value of the first resistor
However, Maejima teaches:
a resistance value of the second resistor is different from a resistance value of the first resistor (Fig. 1 regarding a second resistor having a different resistance than the first resistor)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Chang in view of Jung with Maejima because the different resistive values “allow the current to gradually vary (step up) at equal distances”. [Maejima: [0062]].
With regards to claim 2, Chang in view of Jung in further view of Maejima teaches the configurable computing unit according to claim 1, as referenced above.
Chang further teaches:
wherein the width value of the second transistor is 2 to the power of n times the width value of the first transistor, and n is a positive integer greater than or equal to 1. (Fig. 7 items M4, M8 with M4 having X2 as a times 2 width of M8; [0037] regarding the width of M4 being twice that of M8);
Chang does not explicitly teach:
wherein the resistance value of the second resistor is 2 to the power of n times the resistance value of the first resistor, and n is a positive integer greater than or equal to 1.
However, Maejima teaches:
wherein the resistance value of the second resistor is 2 to the power of n times the resistance value of the first resistor, and n is a positive integer greater than or equal to 1. (Fig. 1 regarding a second resistor having a different resistance than the first resistor with the first resistor being R and the second resistor being 2R)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Chang in view of Jung with Maejima because the different resistive values “allow the current to gradually vary (step up) at equal distances”. [Maejima: [0062]].
With regards to claim 3, Chang in view of Jung in further view of Maejima teaches the configurable computing unit according to claim 1, as referenced above.
Chang further teaches:
further comprising: a third input transistor having a first end, (Fig. 7 item M9 (as a third input transistor));
a control end coupled to a third input bit line, (Fig. 7 item M9 (as a third input transistor with control end connected to Input <0> as a third input line));
and a second end; (Fig. 7 item M9 (as a third input transistor));
a third weight transistor having a first end coupled to the second end of the third input transistor, (Fig. 7 items M10 (as a third weight transistor), M9 (as a third input transistor connected to M10));
a control end receiving the first weight bit, (Fig. 7 items M10 (as a third weight transistor control end connected to LBL), LBL (as a first weight bit line));
and a second end coupled to a second readout bit line; (Fig. 7 items M10 (as a third weight transistor connected to HGBLB), HGBLB (as a second readout bit line); [0037] regarding HGBLB as an output bit line);
a third input transistor first end of the third input transistor and the common signal line; (Fig. 7 item M9 (as a third input transistor), Ground (as a common signal line));
a fourth input transistor having a first end, (Fig. 7 item M5 (as a fourth input transistor));
control end coupled to a fourth input bit line, (Fig. 7 item M5 (as a fourth input transistor control end connected to Input<1> as a fourth input line));
and a second end; (Fig. 7 item M5 (as a fourth input transistor));
a fourth weight transistor having a first end coupled to the second end of the fourth input transistor, (Fig. 7 items M6 (as a fourth weight transistor), M5 (as a fourth input transistor connected to M6));
a control end receiving the first weight bit, (Fig. 7 items M6 (as a fourth weight transistor control line connected to LBL), LBL (as a first weight bit line));
and a second end coupled to the second readout bit line; (Fig. 7 items M6 (as a fourth weight transistor connected to HGBLB), HGBLB (as a second readout bit line); [0037] regarding HGBLB as an output bit line);
and a fourth input transistor the first end of the fourth input transistor and the common signal line, (Fig. 7 item M5 (as a fourth input transistor), Ground (as a common signal line));
wherein a width value of the fourth input transistor is different from a width value of the third input transistor. (Fig. 7 items M9, M5 with M5 having X2 as a times 2 width of M9; [0037] regarding the width of M5 being twice that of M9);
Chang does not explicitly teach:
resistor coupled between
However, Jung teaches:
resistor coupled between (Fig. 7A regarding a resistor in series with a transistor coupled between the transistor and a common signal line)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Chang with the resistor of Chang because [Jung: [0044]] Jung teaches that the resistive elements is for corresponding to a data value, using the resistor in series with the transistor instead of the transistors of different widths would then be a simple substitution of one known element for another to obtain predictable results [MPEP 2141 (III)(B)].
Chang in view of Jung do not explicitly teach:
wherein a resistance value of the fourth resistor is different from a resistance value of the third resistor
However, Maejima teaches:
wherein a resistance value of the fourth resistor is different from a resistance value of the third resistor (Fig. 1 regarding a fourth resistor having a different resistance than the third resistor)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Chang in view of Jung with Maejima because the different resistive values “allow the current to gradually vary (step up) at equal distances”. [Maejima: [0062]].
With regards to claim 4, Chang in view of Jung in further view of Maejima teaches the configurable computing unit according to claim 3, as referenced above.
Chang further teaches:
wherein the width value of the second input transistor is 2 to the power of n times the width value of the first input transistor, (Fig. 7 items M4, M8 with M4 having X2 as a times 2 width of M8; [0037] regarding the width of M4 being twice that of M8);
the width value of the fourth input transistor is 2 to the power of n times the width value of the third input transistor, and n is a positive integer greater than or equal to 1. (Fig. 7 items M9, M5 with M5 having X2 as a times 2 width of M9; [0037] regarding the width of M5 being twice that of M9);
Chang does not explicitly teach:
wherein the resistance value of the second resistor is 2 to the power of n times the resistance value of the first resistor
the resistance value of the fourth resistor is 2 to the power of n times the resistance value of the third resistor, and n is a positive integer greater than or equal to 1
However, Maejima teaches:
wherein the resistance value of the second resistor is 2 to the power of n times the resistance value of the first resistor (Fig. 1 regarding a second resistor having a different resistance than the first resistor, with the first resistor having a resistance of R, and the second having the resistance of 2R)
the resistance value of the fourth resistor is 2 to the power of n times the resistance value of the third resistor, and n is a positive integer greater than or equal to 1. (Fig. 1 regarding a fourth resistor having a different resistance than the third resistor, with the third resistor having a resistance of 4R and the fourth resistor having the resistance of 8R)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Chang in view of Jung with Maejima because the different resistive values “allow the current to gradually vary (step up) at equal distances”. [Maejima: [0062]].
With regards to claim 5, Chang in view of Jung in further view of Maejima teaches the configurable computing unit according to claim 3, as referenced above.
Chang further teaches:
further comprising: a fifth input transistor having a first end, (Fig. 8 item 200a (memory unit, with memory cell and transpose cell); [0039] regarding Fig 7 able to be incorporated in Fig 8, Fig. 7 as item 214b is a transpose cell, and Input bit lines Input <3:2> and Input <1:0> connected to each memory array unit; Fig. 7 item M8 (as a fifth input transistor));
a control end coupled to the first input bit line, (Fig. 8 item 200a (memory unit, with memory cell and transpose cell); [0039] regarding Fig 7 able to be incorporated in Fig 8, Fig. 7 as item 214b is a transpose cell, and Input bit lines Input <3:2> and Input <1:0> connected to each memory array unit; Fig. 7 item M8 (as a fifth input transistor control end connected to Input<2> as a first input bit line));
and a second end; (Fig. 8 item 200a (memory unit, with memory cell and transpose cell); [0039] regarding Fig 7 able to be incorporated in Fig 8, Fig. 7 as item 214b is a transpose cell, and Input bit lines Input <3:2> and Input <1:0> connected to each memory array unit; Fig. 7 item M8 (as a fifth input transistor));
a fifth weight transistor having a first end coupled to the second end of the fifth input transistor, (Fig. 8 item 200a (memory unit, with memory cell and transpose cell); [0039] regarding Fig 7 able to be incorporated in Fig 8, Fig. 7 as item 214b is a transpose cell, and Input bit lines Input <3:2> and Input <1:0> connected to each memory array unit; Fig. 7 items M7 (as a fifth weight transistor), M8 (as a fifth input transistor connected to M7));
a control end receiving a second weight bit, ([0003] regarding memory cells storing weight bit; [0027] regarding memory cell 212 storing a weight bit; Fig. 8 item 200a (memory unit, with memory cell and transpose cell); [0039] regarding Fig 7 able to be incorporated in Fig 8, Fig. 7 as item 214b is a transpose cell, and Input bit lines Input <3:2> and Input <1:0> connected to each memory array unit; Fig. 7 items M7 (as a fifth weight transistor control end connected to LBL, LBL (as a second weight bit line). As interpreted by the Examiner, each memory cell stores a weight bit (as suggested in [0027]), thus another memory cell would contain a second weight bit);
and a second end coupled to the first readout bit line; (Fig. 8 item 200a (memory unit, with memory cell and transpose cell); [0039] regarding Fig 7 able to be incorporated in Fig 8, Fig. 7 as item 214b is a transpose cell, and Input bit lines Input <3:2> and Input <1:0> connected to each memory array unit; Fig. 7 items M7 (as a fifth weight transistor connected to HGBL), HGBL (as a first readout bit line); [0037] regarding HGLB as an output bit line);
a fifth input transistor the first end of the fifth input transistor and the common signal line; (Fig. 8 item 200a (memory unit, with memory cell and transpose cell); [0039] regarding Fig 7 able to be incorporated in Fig 8, Fig. 7 as item 214b is a transpose cell, and Input bit lines Input <3:2> and Input <1:0> connected to each memory array unit; Fig. 7 item M8 (as a fifth input transistor), Ground (as a common signal line));
a sixth input transistor having a first end, (Fig. 8 item 200a (memory unit, with memory cell and transpose cell); [0039] regarding Fig 7 able to be incorporated in Fig 8, Fig. 7 as item 214b is a transpose cell, and Input bit lines Input <3:2> and Input <1:0> connected to each memory array unit; Fig. 7 item M4 (as a sixth input transistor));
a control end coupled to the second input bit line, (Fig. 8 item 200a (memory unit, with memory cell and transpose cell); [0039] regarding Fig 7 able to be incorporated in Fig 8, Fig. 7 as item 214b is a transpose cell, and Input bit lines Input <3:2> and Input <1:0> connected to each memory array unit; Fig. 7 item M4 (as a sixth input transistor with control end coupled to Input<3> as a second input line));
and a second end; (Fig. 8 item 200a (memory unit, with memory cell and transpose cell); [0039] regarding Fig 7 able to be incorporated in Fig 8, Fig. 7 as item 214b is a transpose cell, and Input bit lines Input <3:2> and Input <1:0> connected to each memory array unit; Fig. 7 item M4 (as a sixth input transistor));
a sixth weight transistor having a first end coupled to the second end of the sixth input transistor, (Fig. 8 item 200a (memory unit, with memory cell and transpose cell); [0039] regarding Fig 7 able to be incorporated in Fig 8, Fig. 7 as item 214b is a transpose cell, and Input bit lines Input <3:2> and Input <1:0> connected to each memory array unit; Fig. 7 items M3 (as a sixth weight transistor), M4 (as a sixth input transistor connected to M3));
a control end receiving the second weight bit, (Fig. 8 item 200a (memory unit, with memory cell and transpose cell); [0039] regarding Fig 7 able to be incorporated in Fig 8, Fig. 7 as item 214b is a transpose cell, and Input bit lines Input <3:2> and Input <1:0> connected to each memory array unit; Fig. 7 items M3 (as a sixth weight transistor), LBL (as a second weight bit line));
and a second end coupled to the first readout bit line; (Fig. 8 item 200a (memory unit, with memory cell and transpose cell); [0039] regarding Fig 7 able to be incorporated in Fig 8, Fig. 7 as item 214b is a transpose cell, and Input bit lines Input <3:2> and Input <1:0> connected to each memory array unit; Fig. 7 items M3 (as a sixth weight transistor connected to HGBL), HGBL (as a first readout bit line); [0037] regarding HGLB as an output bit line);
a sixth input transistor the first end of the sixth input transistor and the common signal line; (Fig. 8 item 200a (memory unit, with memory cell and transpose cell); [0039] regarding Fig 7 able to be incorporated in Fig 8, Fig. 7 as item 214b is a transpose cell, and Input bit lines Input <3:2> and Input <1:0> connected to each memory array unit; Fig. 7 item M4 (as a sixth input transistor), Ground (as a common signal line));
a seventh input transistor having a first end, (Fig. 8 item 200a (memory unit, with memory cell and transpose cell); [0039] regarding Fig 7 able to be incorporated in Fig 8, Fig. 7 as item 214b is a transpose cell, and Input bit lines Input <3:2> and Input <1:0> connected to each memory array unit; Fig. 7 item M9 (as a seventh input transistor));
a control end coupled to the third input bit line, (Fig. 8 item 200a (memory unit, with memory cell and transpose cell); [0039] regarding Fig 7 able to be incorporated in Fig 8, Fig. 7 as item 214b is a transpose cell, and Input bit lines Input <3:2> and Input <1:0> connected to each memory array unit; Fig. 7 item M9 (as a seventh input transistor with control end connected to Input <0> as a third input line));
and a second end; (Fig. 8 item 200a (memory unit, with memory cell and transpose cell); [0039] regarding Fig 7 able to be incorporated in Fig 8, Fig. 7 as item 214b is a transpose cell, and Input bit lines Input <3:2> and Input <1:0> connected to each memory array unit; Fig. 7 item M9 (as a seventh input transistor));
a seventh weight transistor having a first end coupled to the second end of the seventh input transistor, (Fig. 8 item 200a (memory unit, with memory cell and transpose cell); [0039] regarding Fig 7 able to be incorporated in Fig 8, Fig. 7 as item 214b is a transpose cell, and Input bit lines Input <3:2> and Input <1:0> connected to each memory array unit; Fig. 7 items M10 (as a seventh weight transistor), M9 (as a seventh input transistor connected to M10));
a control end receiving the second weight bit, (Fig. 8 item 200a (memory unit, with memory cell and transpose cell); [0039] regarding Fig 7 able to be incorporated in Fig 8, Fig. 7 as item 214b is a transpose cell, and Input bit lines Input <3:2> and Input <1:0> connected to each memory array unit; Fig. 7 items M10 (as a seventh weight transistor control end connected to LBL), LBL (as a second weight bit line));
and a second end coupled to the second readout bit line; (Fig. 8 item 200a (memory unit, with memory cell and transpose cell); [0039] regarding Fig 7 able to be incorporated in Fig 8, Fig. 7 as item 214b is a transpose cell, and Input bit lines Input <3:2> and Input <1:0> connected to each memory array unit; Fig. 7 items M10 (as a seventh weight transistor connected to HGBLB), HGBLB (as a second readout bit line); [0037] regarding HGBLB as an output bit line);
a seventh input transistor the first end of the seventh input transistor and the common signal line; (Fig. 8 item 200a (memory unit, with memory cell and transpose cell); [0039] regarding Fig 7 able to be incorporated in Fig 8, Fig. 7 as item 214b is a transpose cell, and Input bit lines Input <3:2> and Input <1:0> connected to each memory array unit; Fig. 7 item M9 (as a seventh input transistor), Ground (as a common signal line));
an eighth input transistor having a first end, (Fig. 8 item 200a (memory unit, with memory cell and transpose cell); [0039] regarding Fig 7 able to be incorporated in Fig 8, Fig. 7 as item 214b is a transpose cell, and Input bit lines Input <3:2> and Input <1:0> connected to each memory array unit; Fig. 7 item M5 (as an eighth input transistor));
a control end coupled to the fourth input bit line, (Fig. 8 item 200a (memory unit, with memory cell and transpose cell); [0039] regarding Fig 7 able to be incorporated in Fig 8, Fig. 7 as item 214b is a transpose cell, and Input bit lines Input <3:2> and Input <1:0> connected to each memory array unit; Fig. 7 item M5 (as an eighth input transistor control end connected to Input<1> as a fourth input line));
and a second end; (Fig. 8 item 200a (memory unit, with memory cell and transpose cell); [0039] regarding Fig 7 able to be incorporated in Fig 8, Fig. 7 as item 214b is a transpose cell, and Input bit lines Input <3:2> and Input <1:0> connected to each memory array unit; Fig. 7 item M5 (as an eighth input transistor));
an eighth weight transistor having a first end coupled to the second end of the eighth input transistor, (Fig. 8 item 200a (memory unit, with memory cell and transpose cell); [0039] regarding Fig 7 able to be incorporated in Fig 8, Fig. 7 as item 214b is a transpose cell, and Input bit lines Input <3:2> and Input <1:0> connected to each memory array unit; Fig. 7 items M6 (as an eighth weight transistor), M5 (as a eighth input transistor connected to M6));
a control end receiving the second weight bit, (Fig. 8 item 200a (memory unit, with memory cell and transpose cell); [0039] regarding Fig 7 able to be incorporated in Fig 8, Fig. 7 as item 214b is a transpose cell, and Input bit lines Input <3:2> and Input <1:0> connected to each memory array unit; Fig. 7 items M6 (as an eighth weight transistor control line connected to LBL), LBL (as a second weight bit line));
and a second end coupled to the second readout bit line; (Fig. 8 item 200a (memory unit, with memory cell and transpose cell); [0039] regarding Fig 7 able to be incorporated in Fig 8, Fig. 7 as item 214b is a transpose cell, and Input bit lines Input <3:2> and Input <1:0> connected to each memory array unit; Fig. 7 items M6 (as an eighth weight transistor connected to HGBLB), HGBLB (as a second readout bit line); [0037] regarding HGBLB as an output bit line);
and an eighth input transistor the first end of the eighth input transistor and the common signal line, (Fig. 8 item 200a (memory unit, with memory cell and transpose cell); [0039] regarding Fig 7 able to be incorporated in Fig 8, Fig. 7 as item 214b is a transpose cell, and Input bit lines Input <3:2> and Input <1:0> connected to each memory array unit; Fig. 7 item M5 (as a eighth input transistor), Ground (as a common signal line));
wherein a width value of the sixth input transistor is different from a width value of the fifth input transistor, (Fig. 8 item 200a (memory unit, with memory cell and transpose cell); [0039] regarding Fig 7 able to be incorporated in Fig 8, Fig. 7 as item 214b is a transpose cell, and Input bit lines Input <3:2> and Input <1:0> connected to each memory array unit; Fig. 7 items M8, M4 with M4 having X2 as a times 2 width of M8; [0037] regarding the width of M4 being twice that of M8);
and a width value of the eighth input transistor is different from a width value of the seventh input transistor. (Fig. 8 item 200a (memory unit, with memory cell and transpose cell); [0039] regarding Fig 7 able to be incorporated in Fig 8, Fig. 7 as item 214b is a transpose cell, and Input bit lines Input <3:2> and Input <1:0> connected to each memory array unit; Fig. 7 items M9, M5 with M5 having X2 as a times 2 width of M9; [0037] regarding the width of M5 being twice that of M9).
Chang does not explicitly teach:
resistor coupled between
a resistance value of the sixth resistor is different from a resistance value of the fifth resistor
a resistance value of the eighth resistor is different from a resistance value of the seventh resistor
However, Jung teaches:
resistor coupled between (Fig. 7A regarding a resistor in series with a transistor coupled between the transistor and a common signal line)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Chang with the resistor of Chang because [Jung: [0044]] Jung teaches that the resistive elements is for corresponding to a data value, using the resistor in series with the transistor instead of the transistors of different widths would then be a simple substitution of one known element for another to obtain predictable results [MPEP 2141 (III)(B)].
Chang in view of Jung does not explicitly teach:
a resistance value of the sixth resistor is different from a resistance value of the fifth resistor
a resistance value of the eighth resistor is different from a resistance value of the seventh resistor
However, Maejima teaches:
a resistance value of the sixth resistor is different from a resistance value of the fifth resistor (Fig. 1 regarding resistors of different values)
a resistance value of the eighth resistor is different from a resistance value of the seventh resistor (Fig. 1 regarding resistors of different values)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Chang in view of Jung with Maejima because the different resistive values “allow the current to gradually vary (step up) at equal distances”. [Maejima: [0062]].
With regards to claim 6, Chang in view of Jung in further view of Maejima teaches the configurable computing unit according to claim 5, as referenced above.
Chang further teaches:
wherein the width value of the second input transistor is 2 to the power of n times the width value of the first input transistor, (Fig. 8 item 200a (memory unit, with memory cell and transpose cell); [0039] regarding Fig 7 able to be incorporated in Fig 8, Fig. 7 as item 214b is a transpose cell, and Input bit lines Input <3:2> and Input <1:0> connected to each memory array unit; Fig. 7 items M8, M4 with M4 having X2 as a times 2 width of M8; [0037] regarding the width of M4 being twice that of M8);
the width value of the fourth input transistor is 2 to the power of n times the width value of the third input transistor, (Fig. 8 item 200a (memory unit, with memory cell and transpose cell); [0039] regarding Fig 7 able to be incorporated in Fig 8, Fig. 7 as item 214b is a transpose cell, and Input bit lines Input <3:2> and Input <1:0> connected to each memory array unit; Fig. 7 items M9, M5 with M5 having X2 as a times 2 width of M9; [0037] regarding the width of M5 being twice that of M9);
the width value of the sixth input transistor is 2 to the power of n times the width value of the fifth input transistor, (Fig. 8 item 200a (memory unit, with memory cell and transpose cell); [0039] regarding Fig 7 able to be incorporated in Fig 8, Fig. 7 as item 214b is a transpose cell, and Input bit lines Input <3:2> and Input <1:0> connected to each memory array unit; Fig. 7 items M8, M4 with M4 having X2 as a times 2 width of M8; [0037] regarding the width of M4 being twice that of M8);
the width value of the eighth input transistor is 2 to the power of n times the width value of the seventh input transistor, (Fig. 8 item 200a (memory unit, with memory cell and transpose cell); [0039] regarding Fig 7 able to be incorporated in Fig 8, Fig. 7 as item 214b is a transpose cell, and Input bit lines Input <3:2> and Input <1:0> connected to each memory array unit; Fig. 7 items M9, M5 with M5 having X2 as a times 2 width of M9; [0037] regarding the width of M5 being twice that of M9);
and n is a positive integer greater than or equal to 1. (Fig. 8 item 200a (memory unit, with memory cell and transpose cell); [0039] regarding Fig 7 able to be incorporated in Fig 8, Fig. 7 as item 214b is a transpose cell, and Input bit lines Input <3:2> and Input <1:0> connected to each memory array unit; Fig. 7 items M8, M4 with M4 having X2 as a times 2 width of M8; [0037] regarding the width of M4 being twice that of M8, M9, M5 with M5 having X2 as a times 2 width of M9; [0037] regarding the width of M5 being twice that of M9).
Chang does not explicitly teach:
resistance value of the resistor
However, Maejima teaches:
resistance value of the resistor (Fig. 1 regarding resistors of different values)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Chang in view of Jung with Maejima because the different resistive values “allow the current to gradually vary (step up) at equal distances”. [Maejima: [0062]].
Allowable Subject Matter
Claims 7 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter regarding claims 7 and 8.
With regards to claim 7, the applicant claims a computing unit within memory, wherein the computing unit within memory of claim 1 comprises:
a first input transistor having a first end, a control end coupled to a first input bit line, and a second end; a first weight transistor having a first end coupled to the second end of the first input transistor, a control end receiving a first weight bit, and a second end coupled to a first readout bit line; a first resistor coupled between the first end of the first input transistor and a common signal line; a second input transistor having a first end, a control end coupled to a second input bit line, and a second end; a second weight transistor having a first end coupled to the second end of the second input transistor, a control end receiving the first weight bit, and a second end coupled to the first readout bit line; and a second resistor coupled between the first end of the second input transistor and the common signal line, wherein a resistance value of the second resistor is different from a resistance value of the first resistor.
Furthermore, wherein the computing unit of claim 3 comprises:
a third input transistor having a first end, a control end coupled to a third input bit line, and a second end; a third weight transistor having a first end coupled to the second end of the third input transistor, a control end receiving the first weight bit, and a second end coupled to a second readout bit line; a third resistor coupled between the first end of the third input transistor and the common signal line; a fourth input transistor having a first end, a control end coupled to a fourth input bit line, and a second end; a fourth weight transistor having a first end coupled to the second end of the fourth input transistor, a control end receiving the first weight bit, and a second end coupled to the second readout bit line; and a fourth resistor coupled between the first end of the fourth input transistor and the common signal line, wherein a resistance value of the fourth resistor is different from a resistance value of the third resistor.
Furthermore, the computing unit of claim 5 comprises:
a fifth input transistor having a first end, a control end coupled to the first input bit line, and a second end; a fifth weight transistor having a first end coupled to the second end of the fifth input transistor, a control end receiving a second weight bit, and a second end coupled to the first readout bit line; a fifth resistor coupled between the first end of the fifth input transistor and the common signal line; a sixth input transistor having a first end, a control end coupled to the second input bit line, and a second end; a sixth weight transistor having a first end coupled to the second end of the sixth input transistor, a control end receiving the second weight bit, and a second end coupled to the first readout bit line; a sixth resistor coupled between the first end of the sixth input transistor and the common signal line; a seventh input transistor having a first end, a control end coupled to the third input bit line, and a second end; a seventh weight transistor having a first end coupled to the second end of the seventh input transistor, a control end receiving the second weight bit, and a second end coupled to the second readout bit line; a seventh resistor coupled between the first end of the seventh input transistor and the common signal line; an eighth input transistor having a first end, a control end coupled to the fourth input bit line, and a second end; an eighth weight transistor having a first end coupled to the second end of the eighth input transistor, a control end receiving the second weight bit, and a second end coupled to the second readout bit line; and an eighth resistor coupled between the first end of the eighth input transistor and the common signal line, wherein a resistance value of the sixth resistor is different from a resistance value of the fifth resistor, and a resistance value of the eighth resistor is different from a resistance value of the seventh resistor.
With regards to claim 7, the applicant claims a computing unit within memory, wherein the computing unit within memory of claim 7 comprises:
wherein the resistance value of the fifth resistor is 2 to the power of n times the resistance value of the first resistor, the resistance value of the sixth resistor is 2 to the power of n times the resistance value of the second resistor, the resistance value of the seventh resistor is 2 to the power of n times the resistance value of the third resistor, the resistance value of the eighth resistor is 2 to the power of n times the resistance value of the fourth resistor, and n is a positive integer greater than or equal to 1.
With regards to claim 8, the applicant claims a computing unit within memory, wherein the computing unit within memory of claim 8 comprises:
wherein a ratio of the resistance value of the second resistor to the resistance value of the first resistor is different from a ratio of the resistance value of the sixth resistor to the resistance value of the fifth resistor, and a ratio of the resistance value of the fourth resistor to the resistance value of the third resistor is different from a ratio of the resistance value of the eighth resistor to the resistance value of the seventh resistor.
The primary reason for indication of allowable subject matter is the above italicized claim limitations in combination with the remaining claim limitations including intervening claims.
Chang, discloses the claimed invention in accordance with the above claim mappings. Chang in view of Jung, and Chang in view of Jung and in further view of Maejima are all silent with respect to the above highlighted limitations in combination with the remaining limitations including intervening claims.
Claims 9-16 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter regarding claim 9.
With regards to claim 9, the applicant claims a computing unit within memory, wherein the computing unit within memory of claim 9 comprises:
a first weight transistor having a first end coupled to a first readout bit line, a control end receiving a first weight bit, and a second end; a first input transistor having a first end coupled to the second end of the first weight transistor, a control end coupled to a first input bit line, and a second end coupled to a common signal line; and a second input transistor having a first end coupled to the second end of the first weight transistor, a control end coupled to a second input bit line, and a second end coupled to the common signal line, wherein a number of the first input transistor is different from a number of the second input transistor.
The primary reason for indication of allowable subject matter is the above italicized claim limitations in combination with the remaining claim limitations including intervening claims.
Chang has a similar structure to that which is described in the claimed limitations of claim 9 (as shown in figure 7), however, Chang has a first and second weight transistor which the input transistors are coupled to and thus is silent with respect to the above highlighted limitations in combination with the remaining limitations including intervening claims.
Chang et al. (U.S. Patent Application Publication 2021/0216846 A1), hereinafter “Chang_2”, Figures 3, 5, and 7 discloses much of the limitations described in the claims, similarly, Jung Figure 7A teaches much of the limitations described in the claims, as well as Lue et al. (U.S. Patent Application Publication 2022/0246212 A1), hereinafter “Lue” Figures 1 and 2 teaches much of the limitations described in the claims. Chang_2, Jung, and Lue, however, are all silent with respect to the above highlighted limitations in combination with the remaining limitations including intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.A.K./ Examiner, Art Unit 2182 /EMILY E LAROCQUE/ Primary Examiner, Art Unit 2182