Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-24 are presented for examination.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “a partitioning logic module configured to individually configure” in claim 1.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Objections
In claim 17 line 1, the limitation “the method of claim 14” should be changed to “the processor architecture of claim 14” (or “the method of claim 2” if intended to depend from a different independent claim).
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 3-14, 17 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1, and similarly claims 3 and 14, the limitation “a partitioning logic module configured to individually configure” invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. While the written description contains references to partitioning logic (see e.g. para. [0039], fig. 5, “partition logic”), the disclosure is devoid of any structure (e.g. circuitry) that performs the function in the claim. Therefore, the claim lacks adequate support for such a claim limitation under 35 U.S.C. 112(a).
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3-14, 17, 22-24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the scope of the limitation “a partitioning logic module configured to individually configure each of the primary cores” is unclear. It is unclear whether a single partitioning logic module (claimed to be comprised in a primary processing core) configures each of the primary cores, or only the core the module is in. For the purposes of examination, this has been interpreted to only require at least one partitioning logic module in a core.
Claim 7 recites the limitation "the RISC processor". The antecedent basis for this limitation is unclear. There are multiple previous RISC processors claimed, and it is unclear to which RISC processor this limitation refers. For the purposes of examination, this has been interpreted to be “a RISC processor.”
Claim 14 recites the limitation "the control centric mode". The antecedent basis for this limitation is unclear. There are multiple “a control-centric mode” limitations in parent claim 1 (see lines 3-4, line 9, line 22), and it is unclear to which control-centric mode this limitation refers. For the purposes of examination, this has been interpreted to be “a control-centric mode.”
Claims 22-24 recite the limitation "the streaming mode". The antecedent basis for this limitation is unclear. There are multiple previous “a streaming mode” limitations claimed (see claim 2 lines 13-14, lines 17-18), and it is unclear to which streaming mode this limitation refers. For the purposes of examination, this has been interpreted to be “a streaming mode.”
Regarding claim 1, and similarly claims 3 and 14, the limitation “a partitioning logic module configured to individually configure” invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. While the written description contains references to partitioning logic (see e.g. para. [0039], fig. 5, “partition logic”), the disclosure is devoid of any structure (e.g. circuitry) that performs the function in the claim. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claims 3-6, 8-13, 17 are rejected for being dependent, either directly or indirectly, upon a rejected parent claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12, 14-22, 24 are rejected under 35 U.S.C. 103 as being unpatentable over Appu et al., US Patent Application Publication 2018/0308202 (hereinafter Appu) in view of Jacob, US Patent Application Publication 2005/0166033 (hereinafter Jacob).
Regarding claim 1, Appu teaches:
A reduced instruction set computer processor architecture comprising: multiple RISC processors each defining a primary processing core in a control-centric mode (see e.g. fig. 2A-D, 19, para. [0254], multiple RISC processors such as a cluster of processors 214A including a primary core such as processor 1900; the core operating in a control-centric mode when it primarily reads and executes general purpose instructions for processing), each primary processing core comprising: a main memory (see e.g. fig. 19, memory module); a shared memory (see e.g. para. [0075], [0079-80]); at least one cache memory (see e.g. fig. 19, para. [0045], [0065], [0075]); a plurality of arithmetic logic units capable of reading from and writing to the at least one cache memory in a control-centric mode (see e.g. para. [0045], [0082-3], execution units within GPU can perform general purpose operations such as reading from and writing to a cache memory in a general purpose GPU mode); the architecture being operable to receive configuration code, execute the configuration code to thereby define a plurality of secondary cores by configuring hardware network connections in accordance with the configuration code (see e.g. para. [0161], [0181-2], secondary cores as hardware blocks for operations such as add, multiply, accumulate, etc. can be reconfigured as desired based on training logic configuration code information used by a configuration controller) to thereby define at least one pipeline to allow data to stream out of arithmetic logic units into the main memory and other ones of the plurality of arithmetic logic units in a streaming mode (see e.g. fig. 21, para. [0073], execution units as ALUs, [0275-80], at least one connection allows streaming to/from memory and other execution units; *Examiner notes that the claimed “pipeline” has not been limited other than that it allows data to stream out, which can be taught by any connection or series of elements connecting ALUs and memory to allow data transfer), the architecture comprising: access memory associated with each arithmetic logic unit; at least one load/unload matrix, that defines memory load and unload, associated with each arithmetic logic unit (see e.g. fig. 19-21, para. [0134], [0161], [0181-2], [0203], [0221-40], [0277], local memory and buffers that direct load and unload are associated with execution units that perform operations); and a partitioning logic module (see e.g. fig. 19-21, para. [0134], [0161], [0181-2], training and configuration logic along with memory partitioning) configured to individually configure each of the primary cores to operate in the streaming mode or a control-centric mode (see e.g. fig. 19-21, para. [0134], [0161], [0181-2], [0203], [0221-40], [0277], execution units are configured/reconfigured to perform operations on matrices depending on the chosen mode of operation such as a GPU performing more general purpose operations or more graphics/machine learning operations streaming data from one unit to another unit or directly to memory; *Examiner notes that the modes are claimed in the alternative such that the prior art need only teach one mode to meet the claimed limitation).
Appu fails to explicitly teach a plurality of different node wrappers, a respective one of the plurality of different node wrappers respectively being associated with each of the primary cores, the node wrapper being operable to perform configuration.
Jacob teaches a node wrapper associated with each core that is operable to perform data and configuration management (see e.g. fig. 1, para. [0038-9], node wrapper).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Appu and Jacob to include a plurality of different node wrappers, a respective one of the plurality of different node wrappers respectively being associated with each of the primary cores, the node wrapper being operable to perform configuration. This would have provided an advantage of increased programmable flexibility to allow each node to be “adapted on the fly to perform a desired function or to execute a specific algorithm” such as discussed by Jacob (see para. [0050]).
Claim 2 is rejected for reasons corresponding to those given above for claim 1.
Regarding claim 3, Appu in view of Jacob teaches or suggests:
The processor architecture of claim 1, wherein the partitioning logic module is configured to partition the at least one load/unload matrix and meter data from the access memory and to combine load/unload matrix partitions back into a full output matrix (see e.g. Appu para. [0134], [0161], [0181-2], [0203], [0238], matrix data such as for machine learning is loaded from memory for different processing nodes; the shared memory and the matrix data it stores is partitioned as part of the system configuration by training and configuration logic; the data is processed by different nodes and then result data is combined back for output).
Regarding claim 4, Appu in view of Jacob teaches or suggests:
The processor architecture of claim 1, wherein each secondary core comprises: a processor including processing elements arranged in a ring, each processing element computes a rectangular partition of a result matrix, the result matrix being represented by the label Y, using single precision floating point arithmetic, integer arithmetic and vector arithmetic (see e.g. Appu fig. 19-21, para. [0073], [0082], [0203], [0250], [0264], [0270], a ring interconnect couples processing units that perform floating point, integer, and vector arithmetic to compute rectangular portions of matrix data; Jacob para. [0116], ring topology).
Regarding claim 5, Appu in view of Jacob teaches or suggests:
The processor architecture of claim 4 wherein each arithmetic logic unit has an input that is associated with a node input memory, partitioning logic and an input state machine for transferring data from memory to the arithmetic logic unit and wherein each arithmetic logic unit has an output that is associated with an output memory, the output memory being updated throughout processing with the latest sum for the arithmetic logic unit as it is computed (see e.g. Appu fig. 19-21, para. [0073], [0134-5], [0182], [0203], [0221-40], execution units are associated with memory, partitioning logic, and read/write elements for inputting and outputting data such as for an addition operation).
Regarding claim 6, Appu in view of Jacob teaches or suggests:
The processor architecture of claim 1, wherein the architecture is formed on a single chip (see e.g. Appu fig. 17, para. [0045]).
Regarding claim 7, Appu in view of Jacob teaches or suggests:
The processor architecture of claim 1 wherein, in the streaming mode, the arithmetic logic units of each of the multiple RISC processors are used as streaming secondary cores (see e.g. Appu fig. 21, para. [0275-80]).
Regarding claim 8, Appu in view of Jacob teaches or suggests:
The processor architecture of claim 1, wherein each cache memory is a nodal memory comprising multiple memories (see e.g. Appu para. [0075]).
Regarding claim 9, Appu in view of Jacob teaches or suggests:
The processor architecture of claim 1, wherein each primary core has multiple arithmetic logic units (see e.g. Appu para. [0078], [0082]).
Regarding claim 10, Appu in view of Jacob teaches or suggests:
The processor architecture of claim 9, wherein the arithmetic logic units are configured as at least one of integer multipliers, integer multiplier accumulators, integer dividers, floating point multipliers, floating point multiplier accumulators, floating point dividers (see e.g. Appu para. [0082]).
Regarding claim 11, Appu in view of Jacob teaches or suggests:
The processor architecture of claim 10, wherein the arithmetic logic units are Single Instruction Multiple Data (SIMD) units (see e.g. Appu para. [0071], [0290]).
Regarding claim 12, Appu in view of Jacob teaches or suggests:
The processor architecture of claim 9, wherein, in the streaming mode, the respective node wrapper associated with each of the primary cores defines multiple hardware streams to be allocated to specific ones of the secondary cores (see e.g. Appu para. [0291-4]).
Regarding claim 14, Appu in view of Jacob teaches or suggests:
The processor architecture of claim 1, wherein the partitioning logic module is configured to dynamically configure at least some of the primary cores to operate in the streaming mode or the control-centric mode in a dynamic manner during execution (see e.g. Appu fig. 21, para. [0275-80], dynamically scalable; Jacob para. [0037], [0110], dynamic hardware reconfiguration).
Claims 15-22, 24 are rejected for reasons corresponding to those given above for claims 4-5, 7-12, 14.
Claims 13, 23 are rejected under 35 U.S.C. 103 as being unpatentable over Appu in view of Jacob, further in view of Bhunia et al., US Patent Application Publication 2019/0180041 (hereinafter Bhunia).
Regarding claim 13, Appu in view of Jacob teaches or suggests:
The processor architecture of claim 1.
Appu in view of Jacob fails to explicitly teach wherein, in the streaming mode, the respective node wrapper associated with each primary core is fractured into multiple secondary core node wrappers.
Bhunia teaches security or communication wrappers that can include a number of localized wrapper cells (see e.g. fig. 3B, para. [0043-7])
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Appu, Jacob, and Bhunia such that in the streaming mode, the respective node wrapper associated with each primary core is fractured into multiple secondary core node wrappers. This would have provided additional granularity to provide even more programmable flexibility to the system. This would have also allowed for granular security policies to protect on-chip assets such as discussed by Bhunia (see para. [0018-19]).
Claim 23 is rejected for reasons corresponding to those given above for claim 13.
Response to Arguments
Applicant's arguments filed 12/30/25 have been fully considered but they are not persuasive.
Regarding the limitation interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, Applicant has not amended the claim limitation to avoid being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting “circuitry” or sufficient structure to perform the claimed function); or presented a sufficient showing that the claim limitation recites sufficient structure to perform the claimed function so as to avoid it being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The cited paragraphs and figures do not specifically state the corresponding structure, material, or acts to perform the claimed function.
Regarding the rejection under 35 U.S.C. 112(b), Applicant states “However, with respect to claims 14, and 22-24, the examiner is incorrect in stating that '[t]here are multiple previous 'arithmetic logic units' limitations claimed" and "[t]here are multiple previous 'a streaming mode' limitations claimed". Antecedent basis can be found once, and only once, for these limitations in claim 1”
This is incorrect. These claims were not rejected for “arithmetic logic units” limitations. Regarding claim 14, there are multiple “a control-centric mode” limitations in parent claim 1 (see lines 3-4, line 9, line 22). Regarding claims 22-24, the antecedent basis for these claims cannot be given by claim 1 because these claims do not depend from claim 1. They are method claims that depend from independent claim 2. Claim 2 recites multiple “a streaming mode” limitations (see claim 2 lines 13-14, lines 17-18).
Applicant argues: “In particular, Jacobs fails to teach or suggest at least the following claimed elements: to thereby define a plurality of secondary cores by configuring hardware network connections in accordance with the configuration code to thereby define at least one data pipeline to allow data to stream out of arithmetic logic units into the main memory and other ones of the plurality of arithmetic logic units in a streaming mode.”
Jacob was not relied upon to teach these configuration elements of the claim(s). Appu teaches performing these configuration elements of the claim. Appu fails to explicitly teach a respective node wrapper being operable to perform configuration.
Jacob teaches a node wrapper associated with each core that is operable to perform data and configuration management (see e.g. fig. 1, para. [0038-9], node wrapper).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Appu and Jacob to include a respective node wrapper associated with each of the primary cores, the node wrapper being operable to perform configuration. This would have provided an advantage of increased programmable flexibility to allow each node to be “adapted on the fly to perform a desired function or to execute a specific algorithm” such as discussed by Jacob (see para. [0050]).
One cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicant argues: “Further, Appu lacks any disclosure of defining "at least one data pipeline to allow data to stream out of arithmetic logic units into the main memory and other ones of the plurality of arithmetic logic units in a streaming mode" as recited in the claims.”
Examiner respectfully disagrees. Appu teaches that at least one connection allows streaming to/from memory and other execution units (see e.g. fig. 21, para. [0073], execution units as ALUs, [0275-80], *Examiner notes that the claimed “pipeline” has not been limited other than that it allows data to stream out, which can be taught by any connection or series of elements connecting ALUs and memory to allow data transfer).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN M LINDLOF whose telephone number is (571)270-1024. The examiner can normally be reached Mon-Tue 8:30-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at 5712703995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOHN M LINDLOF/Primary Examiner, Art Unit 2183
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