DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-6, 8-10, 12-15, 17 and 21-27 are pending in this application. Claims 2, 9 ,12 and 24 are currently amended; claims 1, 3-6, 8, 10, 13-15, 17, 21-23 and 25-26 are previously presented; claim 27 is new; claims 7, 11, 16 and 18-20 are canceled.
Claim Interpretation
The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. For example, assume a method claim requires step A if a first condition happens and step B if a second condition happens. If the claimed invention may be practiced without either the first or second condition happening, then neither step A or B is required by the broadest reasonable interpretation of the claim. If the claimed invention requires the first condition to occur, then the broadest reasonable interpretation of the claim requires step A. If the claimed invention requires both the first and second conditions to occur, then the broadest reasonable interpretation of the claim requires both steps A and B. See MPEP 2111.04 II for more information.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-6 are 13-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites “wherein the post processing operation further includes at least one of clamping the matrix multiplication results to limit the matrix multiplication results to the clamp range, or a bit shift operation based on the shift value”. This limitation recites a list of alternatives, however, the list is an open list of alternatives which creates confusion as to what other alternatives are intended to be encompassed by the claim. For purposes of examination, this is interpreted as wherein the post processing operation is at least one of clamping the matrix multiplication results to limit the matrix multiplication results to the clamp range, or a bit shift operation based on the shift value. See MPEP 2173.05(h) subsection I and 2117 subsection I for more information. Claim 13 recites substantially the same limitation and is rejected for the same reason. Claims 4-6 inherit the same deficiency as claim 3 by reason of dependence. Claims 14-15 inherit the same deficiency as claim 13 by reason of dependence.
Claim 6 recites “wherein the post processing operation further includes multiplying the matrix multiplication results with the scaling value”. This limitation is unclear because it is adding another alternative post processing operation to the list of alternatives in claim 3 from which the claim depends. However, as discussed above, the list of alternatives in claim 3 must be a closed group of alternative, therefore, no further addition can be included. Perhaps Applicant may want to amend claim 3 to include the features of claim 6.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8 and 21-27 are rejected under 35 U.S.C. 103 as being unpatentable over Mansell et al. (US 20190369989 A1), hereinafter Mansell, in view of Emberling et al. (US 20230097279 A1), hereinafter Emberling and Hennessy et al. (NPL – “Computer Organization and Design: The Hardware/Software Interface”), hereinafter Hennessy.
Regarding claim 1, Mansell teaches a method comprising, by a processing circuit (Mansell Fig. 1 and claim 1; processing circuitry - data processing apparatus 10):
receiving a first instruction including a first parameter identifying a first register, a second parameter identifying a second register, a third parameter identifying at least one output register, and a fourth parameter indicating whether the first instruction is for a matrix multiplication, wherein the first instruction uses an instruction set architecture (ISA) instruction (Mansell Figs. 15A-16 and 18-21; paragraphs [0064-0065] first instruction – 500; first parameter – 504; second parameter – 506; third parameter – 508; fourth parameter – 502);
in response to the fourth parameter indicating that the first instruction is for the matrix multiplication (Examiner notes that this limitation recites a contingent limitation and the subsequent steps are not required to be performed if the fourth parameter has a value different from a value indicating the matrix multiplication. See claim interpretation section above.):
receiving, from the first register, input (Mansell Fig. 15A-16 and paragraphs [0064-0065] input values – contents of the first register);
receiving, from the second register, (Mansell Fig. 15A-16 and paragraphs [0064-0065] values – contents of the second register);
performing the matrix multiplication of the input (Mansell Fig. 15A-16 and paragraphs [0064-0065] matrix multiplication results – result matrix C); and
providing matrix multiplication results to the at least one output register (Mansell Fig. 15A-16 and paragraphs [0064-0065] “The output of the FMA units is applied to a respective register of the set of accumulation registers specified in the instruction (see item 508 in FIG. 15B) … The accumulators for the result matrix C are stored in the registers v4-v7”).
Mansell does not explicitly teach input feature values and weight values; and wherein the first instruction uses an instruction set architecture (ISA) instruction that is also used for an operation different from the matrix multiplication when the fourth parameter has a value different from a value indicating the matrix multiplication.
However, on the same field of endeavor, Emberling discloses receiving input feature values and weight values and performing matrix multiplication of the input feature values and the weight values to obtain matrix multiplication results (Emberling Fig. 4 and paragraphs [0026, 0030]; input feature values – pixel values I1-I34; weight values – weight values w11-w33; matrix multiplication results – convolution result).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Mansell using Emberling and configure the data stored in registers 510/520 (v0/v2) as input feature values and weight values in order to implement a system for processing layers of a neural network (Emberling paragraph [0028]).
Therefore, the combination of Mansell as modified in view of Emberling teaches receiving, from the first register, input feature values; and receiving, from the second register, weight values.
The combination of Mansell as modified in view of Emberling does not explicitly teach wherein the first instruction uses an instruction set architecture (ISA) instruction that is also used for an operation different from the matrix multiplication when the fourth parameter has a value different from a value indicating the matrix multiplication.
However, on the same field of endeavor, Hennessy discloses a first instruction that uses an instruction set architecture (ISA) instruction that is also used for a different operation when a fourth parameter has a value different from a value indicating a first arithmetic operation (Hennessy Figs. 2.5 and 2.6; fourth parameter – function code; the add and subtract instruction have different function codes 32 and 34 respectively).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Mansell in view of Emberling and generalize the teaching of Hennessy by including an additional parameter (i.e., a function field) or modifying the opcode to specify that the first instruction is a matrix multiplication operation when the fourth parameter has a first value and is an operation different from the matrix multiplication when the fourth parameter has a second value different from the first value in order to specify the different operations performed by the instruction based on the value of the fourth parameter (Hennessy Figs. 2.5 and 2.6).
Therefore, the combination of Mansell as modified in view of Emberling and Hennessy teaches wherein the first instruction uses an instruction set architecture (ISA) instruction that is also used for an operation different from the matrix multiplication when the fourth parameter has a value different from a value indicating the matrix multiplication.
Regarding claim 2, Mansell as modified in view of Emberling and Hennessy teaches all the limitations of claim 1 as stated above.
Mansell does not explicitly teach further comprising: receiving a second instruction including at least a first parameter identifying a third register, a second parameter identifying a fourth register, and a third parameter indicating whether the second instruction is to perform a post processing operation on the matrix multiplication results, wherein the at least one output register includes the third register; and in response to the third parameter of the second instruction indicating that the second instruction is for the post processing operation1, performing the post processing operation on matrix multiplication results stored in the third register using at least one of a clamp range, a shift value, or a scaling value indicated by the fourth register.
However, on the same field of endeavor, Emberling discloses receiving an instruction to perform a post processing operation including scaling, shifting and clamping operations along with a clamp range on the matrix multiplication results; and performing the post processed operation on the matrix multiplication results by scaling, shifting and clamping the matrix multiplication results; and providing the post processed result to an output register (Emberling Figs. 3 and 5; paragraphs [0028 and 0031]; claim 10; instruction to perform a post processing operation – instruction to perform at least one of transitional operations 350-370 or 515-530).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Mansell and generalize the teaching of Emberling by configuring the apparatus to receive a second instruction to perform a post processing operation including scaling, shifting and clamping operations on the matrix multiplication results; perform the post processing operation to generate a post processed result; and store the post processed result to the output registers in order to implement a system for processing layers of a neural network (Emberling paragraph [0028]).
Therefore, the combination of the combination of Mansell as modified in view of Emberling and Hennessy teaches further comprising: receiving a second instruction indicating whether the second instruction is to perform a post processing operation on the matrix multiplication results; and in response to the second instruction indicating that the second instruction is for a post processing operation, performing the post processing operation on matrix multiplication results using at least one of a clamp range, a shift value, or a scaling value.
Mansell as modified in view of Emberling and Hennessy does not explicitly teach further comprising: receiving a second instruction including at least a first parameter identifying a third register, a second parameter identifying a fourth register, and a third parameter indicating whether the second instruction is to perform a post processing operation on the matrix multiplication results, wherein the at least one output register includes the third register; and in response to the third parameter of the second instruction indicating that the second instruction is for a post processing operation, performing the post processing operation on matrix multiplication results stored in the third register using at least one of a clamp range, a shift value, or a scaling value indicated by the fourth register.
However, on the same field of endeavor, Mansell discloses an instruction including at least a first parameter identifying a third register, a second parameter identifying a fourth register, and a third parameter indicating an operation to be performed and performing the operation indicated in the instruction (Mansell Figs. 4-21 and corresponding description). Similarly, Hennessy also discloses a second instruction including at least a first parameter identifying a third register, a second parameter identifying a fourth register, and a third parameter indicating an operation to be performed and performing the operation indicated in the instruction (Hennessy Figs. 2.5 and 2.6).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Mansell by modifying the instruction to perform at least one of transitional operations to include a parameter indicating the post-processing operation to be performed; and parameters identifying the location of the inputs to the post-processing operation by including a parameter identifying the location of the scaling value, shift value and/or clamp range and a parameter identifying the location of the matrix multiplication results. As discussed above, the matrix multiplication results are stored in the output registers, therefore, it would be obvious that the output registers corresponds to the third register while the register used to store the scaling, value, shift value and/or clamp range corresponds to the fourth register because a data processing instruction normally specifies the operations and source registers needed to perform the instruction (Mansell paragraphs [0049, 0050, 0064 and claim 1; Hennessy page 83-87).
Therefore, the combination of the combination of Mansell as modified in view of Emberling and Hennessy teaches further comprising: receiving a second instruction including at least a first parameter identifying a third register, a second parameter identifying a fourth register, and a third parameter indicating whether the second instruction is to perform a post processing operation on the matrix multiplication results, wherein the at least one output register includes the third register; and in response to the third parameter of the second instruction indicating that the second instruction is for a post processing operation, performing the post processing operation on matrix multiplication results stored in the third register using at least one of a clamp range, a shift value, or a scaling value indicated by the fourth register.
Regarding claim 3, Mansell as modified in view of Emberling and Hennessy teaches all the limitations of claim 2 as stated above. Further, Mansell as modified in view of Emberling and Hennessy teaches wherein the post processing operation includes at least one of clamping the matrix multiplication results to limit the matrix multiplication results to the clamp range, or a bit shift operation based on the shift value (Emberling Fig. 5 and paragraph [0031] bit shift operation – right shift by 14 bits or shift operation 522. Further, examiner notes that this limitation further limits the contingent limitation and is not required by the claim if the third parameter of the second instruction does not indicate that the second instruction is for a post processing operation. See claim interpretation section above).
Regarding claim 4, Mansell as modified in view of Emberling and Hennessy teaches all the limitations of claim 3 as stated above. Further, Mansell as modified in view of Emberling and Hennessy teaches wherein the fourth register indicates both of the clamp range and the shift value; and the post processing operation includes both the bit shift operation based on the shift value and clamping the matrix multiplication results to limit the matrix multiplication results to the clamp range (Emberling paragraphs [0028-0029 and 0031]; claim 10; clamp range - the -127 to 128 range of an 8-bit signed integer; shift value - 14 bits. Further, examiner notes that the italicized limitation further limits the contingent limitation and is not required by the claim if the third parameter of the second instruction does not indicate that the second instruction is for a post processing operation. See claim interpretation section above).
Regarding claim 5, Mansell as modified in view of Emberling and Hennessy teaches all the limitations of claim 4 as stated above. Further, Mansell as modified in view of Emberling and Hennessy teaches wherein the fourth register further indicates the scaling value (Emberling paragraphs [0028-0029 and 0031]; scaling values – scaling values to scale each convolution result value).
Regarding claim 6, Mansell as modified in view of Emberling and Hennessy teaches all the limitations of claim 5 as stated above. Further, Mansell as modified in view of Emberling and Hennessy teaches wherein the post processing operation further includes multiplying the matrix multiplication results with the scaling value (Emberling paragraphs [0028 and 0031]. Further, examiner notes that this limitation further limits the contingent limitation and is not required by the claim if the third parameter of the second instruction does not indicate that the second instruction is for a post processing operation. See claim interpretation section above).
Regarding claim 8, Mansell as modified in view of Emberling and Hennessy teaches all the limitations of claim 2 as stated above. Further, Mansell as modified in view of Emberling and Hennessy teaches further comprising applying a bias to the matrix multiplication results before the post processing operation (Emberling Fig. 5 and paragraphs [0028 and 0031] bias – bias value 505/535). The motivation to combine is the same as claim 2.
Regarding claim 21, Mansell as modified in view of Emberling and Hennessy teaches all the limitations of claim 2 as stated above. Further, Mansell as modified in view of Emberling and Hennessy teaches further comprising storing results of the post processing operation (Emberling Fig. 5 and paragraph [0028 and 0031]. Further, examiner notes that this limitation is not required to be performed if the third parameter of the second instruction does not indicate that the second instruction is for a post processing operation. See claim interpretation section above).
Mansell does not explicitly teach further comprising storing results of the post processing operation to the third register.
However, on the same field of endeavor, Mansell discloses storing the results of a data processing operation back to a register storing one of the inputs of the operation (Mansell Fig. 4 paragraph [0052] “in some embodiments the result register 128 and register A may be one and the same register”).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Mansell and store the results of the post processing operation back to the third register. One of ordinary skill in the art could have substituted the output register for the post-processing operation for the third register, and the results of the substitution would have been predictable because both register have the same function of storing data. See MPEP 2141 III.B for more information.
Therefore, the combination of Mansell as modified in view of Emberling and Hennessy teaches further comprising storing results of the post processing operation to the third register.
Regarding claim 22, Mansell as modified in view of Emberling and Hennessy teaches all the limitations of claim 2 as stated above.
Mansell does not explicitly teach wherein the fourth register stores at least one of a respective clamp range, a respective shift value, or a respective scaling value for each of the matrix multiplication results stored in the at least one output register.
However, on the same field of endeavor, Emberling discloses storing a respective value used in a post-processing operation for each of matrix multiplication result in an input register (Emberling paragraph [0031] “The bias value can be either a constant value or a value stored in a respective lane's VGPR”).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Mansell and generalize the teaching of Emberling by storing at least one of a respective clamp range, a respective shift value, or a respective scaling value for each of the matrix multiplication results in the fourth register in order to perform the post-processing operation in parallel in accordance with a SIMD paradigm (Emberling paragraphs [0019, 0022]).
Therefore, the combination of Mansell as modified in view of Emberling and Hennessy teaches wherein the fourth register stores at least one of a respective clamp range, a respective shift value, or a respective scaling value for each of the matrix multiplication results stored in the at least one output register.
Regarding claim 23, Mansell as modified in view of Emberling and Hennessy teaches all the limitations of claim 2 as stated above. Further, Mansell as modified in view of Emberling and Hennessy teaches wherein the fourth register stores a high clamp value and a low clamp value that are shared by the matrix multiplication results stored in the third register (Emberling paragraph [0028] high clamp value and a low clamp value – 128 and -127).
Regarding claim 24, Mansell as modified in view of Emberling and Hennessy teaches all the limitations of claim 2 as stated above. Further, Mansell as modified in view of Emberling and Hennessy teaches wherein the second instruction has a same format as for the first instruction, and the third parameter of the second instruction and the fourth parameter of the first instruction are in a parameter field of the ISA instruction (Hennessy Figs. 2.5 and 2.6 parameter field – function field; or Mansell Fig. 15B and paragraph [0064] parameter field - opcode).
Regarding claim 25, Mansell as modified in view of Emberling and Hennessy teaches all the limitations of claim 2 as stated above. Further, Mansell as modified in view of Emberling and Hennessy teaches wherein the second instruction uses an ISA instruction different from the ISA instruction used for the first instruction (Hennessy Figs. 2.5 and 2.6; the first and second are different because they indicate different operations).
Regarding claim 26, Mansell as modified in view of Emberling and Hennessy teaches all the limitations of claim 1 as stated above. Further, Mansell as modified in view of Emberling and Hennessy teaches wherein the processing circuit includes a general purpose processor (Mansell Fig. 1 and paragraph [0049]; claims 1 and 19).
Regarding claim 27, Mansell as modified in view of Emberling and Hennessy teaches all the limitations of claim 1 as stated above. Further, Mansell as modified in view of Emberling and Hennessy teaches wherein the value of the fourth parameter is the sole indicator of whether the first instruction is for the matrix multiplication or the operation different from the matrix multiplication (see claim 1 analysis above of modifying the opcode to specify that the first instruction is a matrix multiplication operation when the fourth parameter has a first value and is an operation different from the matrix multiplication when the fourth parameter has a second value different from the first value, therefore, the opcode field is the sole indicator. See also Mansell paragraph [0050] which discloses that defines the operation associated with the instruction in combination with paragraph [0056] which discloses different types of operations besides multiplication such as any other type of arithmetic operation (addition, subtraction etc.) or also logical operation (ADD, XOR, etc.)).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Mansell in view of Emberling and Hennessy as applied to claim 1 above, and further in view of Andri et al. (NPL – “YodaNN: An Architecture for Ultralow Power Binary-Weight CNN Acceleration”), hereinafter Andri.
Regarding claim 9, Mansell as modified in view of Emberling and Hennessy teaches all the limitations of claim 1 as stated above.
Mansell does not explicitly teach wherein the weight values are binary values or ternary values.
However, on the same field of endeavor, Andri discloses using weights that have binary values (Andri abstract and page 52-53 section B “the weights which are reduced to a binary value”).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Mansell in view of Emberling and Hennessy using Andri and configure the weight values as binary weight values in order to reduce the weight storage requirement of the system (Andri abstract and Introduction page 48 right col last full paragraph).
Therefore, the combination of Mansell as modified in view of Emberling, Hennessy and Andri teaches wherein the weight values are binary values or ternary values.
Claims 10, 12-15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Mansell in view of Emberling, Hennessy and Nair et al. (US 11138292 B1), hereinafter Nair.
Regarding claim 10, Mansell teaches a system, comprising:
a first register configured to receive input (Mansell Fig. 15A-16 and paragraphs [0064-0065] first register – 510/520 or v0/v2; input values – contents of the register);
a second register configured to receive values (Mansell Fig. 15A-16 and paragraphs [0064-0065] second register – other of 510/520 or v0/v2);
output registers (Mansell Fig. 15A-16 and paragraphs [0064-0065] output registers – 522-528 or v4-v7);
a processor including (Mansell Fig. 1 and claim 1; processor - processing circuitry):
a set of multipliers (Mansell Figs. 11-13 set of multipliers – multipliers 400-406), and
(Mansell Figs. 11-13 adders – adders 408-414),
wherein the processor is configurable to:
receive a first instruction including a first parameter identifying the first register, a second parameter identifying the second register, a third parameter identifying the output registers, and a fourth parameter indicating whether the first instruction is for a matrix multiplication, wherein the first instruction uses an instruction set architecture (ISA) instruction (Mansell Figs. 15A-16 and 18-21; paragraphs [0064-0065] first instruction – 500; first parameter – 504; second parameter – 506; third parameter – 508; fourth parameter – 502);
and in response to the fourth parameter indicating that the first instruction is for the matrix multiplication:
receive the input (Mansell Fig. 15A-16 and paragraphs [0064-0065]);
receive the values from the second register (Mansell Fig. 15A-16 and paragraphs [0064-0065]);
process, by the set of multipliers, the input values to obtain intermediate results (Mansell Fig. 15A-16 and paragraphs [0064-0069] intermediate results – result of the multiply operations);
process, by the (Mansell Fig. 15A-16 and paragraphs [0064-0065] matrix multiplication output value – matrix result C); and
output the matrix multiplication output value to the output registers (Mansell Fig. 15A-16 and paragraphs [0064-0065] “The output of the FMA units is applied to a respective register of the set of accumulation registers specified in the instruction (see item 508 in FIG. 15B) … The accumulators for the result matrix C are stored in the registers v4-v7”).
Mansell does not explicitly teach input feature values; weights; a series of adders; and wherein the first instruction uses an instruction set architecture (ISA) instruction that is also used for an operation different from the matrix multiplication when the fourth parameter has a value different from a value indicating the matrix multiplication.
However, on the same field of endeavor, Emberling discloses receiving input feature values and weight values and performing matrix multiplication of the input feature values and the weight values to obtain matrix multiplication results (Emberling Fig.4 and paragraphs [0026, 0030]; input feature values – pixel values I1-I34; weight values – weight values w11-w33; matrix multiplication results – convolution result).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Mansell using Emberling and configure the data stored in registers 510/520 (v0/v2) as input feature values and weight values in order to implement a system for processing layers of a neural network (Emberling paragraph [0028]).
Therefore, the combination of Mansell as modified in view of Emberling teaches receive the input feature values from the first register; and receive the weights from the second register.
Mansell as modified in view of Emberling does not teach a series of adders; and wherein the first instruction uses an instruction set architecture (ISA) instruction that is also used for an operation different from the matrix multiplication when the fourth parameter has a value different from a value indicating the matrix multiplication
However, on the same field of endeavor, Hennessy discloses a first instruction that uses an instruction set architecture (ISA) instruction that is also used for a different operation when a fourth parameter has a value different from a value indicating a first arithmetic operation (Hennessy Figs. 2.5 and 2.6; fourth parameter – function code; the add and subtract instruction have different function codes 32 and 34 respectively).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Mansell in view of Emberling and generalize the teaching of Hennessy by including an additional parameter (i.e., a function field) or modifying the opcode to specify that the first instruction is a matrix multiplication operation when the fourth parameter has a first value and is an operation different from the matrix multiplication when the fourth parameter has a second value different from the first value in order to specify the different operations performed by the instruction based on the value of the fourth parameter (Hennessy Figs. 2.5 and 2.6).
Therefore, the combination of Mansell as modified in view of Emberling and Hennessy teaches wherein the first instruction uses an instruction set architecture (ISA) instruction that is also used for an operation different from the matrix multiplication when the fourth parameter has a value different from a value indicating the matrix multiplication.
Mansell as modified in view of Emberling and Hennessy does not teach a series of adders.
However, on the same field of endeavor, Nair discloses performing matrix multiplication of input feature values and weights and using a series of adders to sum outputs of a plurality of multiplier circuits (Nair Figs. 2A and 3A, col 6 lines 20-57 and col 8 lines 42-44; input feature values – input image/matrix 102; weights – weights; a series of adders – adder tree 322).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Mansell using Nair and configure each of the adders 408-414 as an adder tree for summing outputs of respective plurality multipliers 400-406 in order to implement a system for neural network computations (Nair col 1 line 33-40 and col 5 lines 25-37). Using a adder tree configuration as disclosed by Nair would still correctly add the output of the respective plurality multipliers 400-406.
Therefore, the combination of Mansell as modified in view of Emberling, Hennessy and Nair a series of adders.
Regarding claim 12, Mansell as modified in view of Emberling, Hennessy and Nair teaches all the limitations of claim 10 as stated above.
Mansell does not explicitly teach wherein the processor is further configurable to: receive a second instruction including at least a first parameter identifying the output registers, a second parameter identifying a third register, and a third parameter indicating whether the second instruction is for a post processing operation, the third register configured to store at least one of a clamp range, a shift value, or a scaling value; and in response to the third parameter of the second instruction indicating that the second instruction is for the post processing operation, perform the post processing operation on the matrix multiplication output value stored in the output registers using the at least one of the clamp range, the shift value, or the scaling value in the third register.
However, on the same field of endeavor, Emberling discloses a processing circuitry configured to receive an instruction to perform a post processing operation including scaling, shifting and clamping operations along with a clamp range on the matrix multiplication results; and performing the post processed operation on the matrix multiplication results by scaling, shifting and clamping the matrix multiplication results; and providing the post processed result to an output register (Emberling Figs. 3 and 5; paragraphs [0028 and 0031]; claim 10; instruction to perform a post processing operation – instruction to perform at least one of transitional operations 350-370 or 515-530).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Mansell and generalize the teaching of Emberling by configuring the apparatus to receive a second instruction to perform a post processing operation including scaling, shifting and clamping operations on the matrix multiplication results; perform the post processing operation to generate a post processed result; and store the post processed result to the output registers in order to implement a system for processing layers of a neural network (Emberling paragraph [0028]).
Therefore, the combination of the combination of Mansell as modified in view of Emberling, Hennessy and Nair teaches wherein the processor is further configurable to: receive a second instruction indicating whether the second instruction is for a post processing operation, at least one of a clamp range, a shift value, or a scaling value; and in response to the second instruction indicating that the second instruction is for a post processing operation, perform the post processing operation on the matrix multiplication output value stored in the output registers using the at least one of the clamp range, the shift value, or the scaling value.
Mansell as modified in view of Emberling, Hennessy and Nair does not explicitly teach wherein the processor is further configurable to: receive a second instruction including at least a first parameter identifying the output registers, a second parameter identifying a third register, and a third parameter indicating whether the second instruction is for a post processing operation, the third register configured to store at least one of a clamp range, a shift value, or a scaling value; and in response to the third parameter of the second instruction indicating that the second instruction is for a post processing operation, perform the post processing operation on the matrix multiplication output value stored in the output registers using the at least one of the clamp range, the shift value, or the scaling value in the third register.
However, on the same field of endeavor, Mansell discloses an instruction including parameters identifying input registers and a parameter indicating an operation to be performed and performing the operation indicated in the instruction (Mansell Figs. 4-21 and corresponding description). Similarly, Hennessy also discloses a second instruction including parameters identifying input registers and a parameter indicating an operation to be performed and performing the operation indicated in the instruction (Hennessy Figs. 2.5 and 2.6).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Mansell by modifying the instruction to perform at least one of transitional operations to include a parameter indicating the post-processing operation to be performed; and parameters identifying the location of the inputs to the post-processing operation by including a parameter identifying the location of the matrix multiplication results in the output registers, and including a parameter identifying the location of the scaling value, shift value and/or clamp range and a parameter because a data processing instruction normally specifies the operations and source registers needed to perform the instruction (Mansell paragraphs [0049, 0050, 0064 and claim 1; Hennessy page 83-87).
Therefore, the combination of the combination of Mansell as modified in view of Emberling, Hennessy and Nair teaches wherein the processor is further configurable to: receive a second instruction including at least a first parameter identifying the output registers, a second parameter identifying a third register, and a third parameter indicating whether the second instruction is for a post processing operation, the third register configured to store at least one of a clamp range, a shift value, or a scaling value; and in response to the third parameter of the second instruction indicating that the second instruction is for a post processing operation, perform the post processing operation on the matrix multiplication output value stored in the output registers using the at least one of the clamp range, the shift value, or the scaling value in the third register.
Regarding claim 13, Mansell as modified in view of Emberling, Hennessy and Nair teaches all the limitations of claim 12 as stated above. Further, Mansell as modified in view of Emberling, Hennessy and Nair teaches wherein the post processing operation includes at least one of clamping the matrix multiplication output value to limit the matrix multiplication output value to the clamp range, or a bit shift operation based on the shift value (Emberling Fig. 5 and paragraph [0031] bit shift operation – right shift by 14 bits).
Regarding claim 14, Mansell as modified in view of Emberling, Hennessy and Nair teaches all the limitations of claim 13 as stated above. Further, Mansell as modified in view of Emberling, Hennessy and Nair teaches wherein the processor is configured to: receive both the clamp range and the shift value from the third register, clamp the matrix multiplication output value based on the clamp range and perform the bit shift operation based on the shift value (Emberling paragraphs [0028-0029 and 0031]).
Regarding claim 15, Mansell as modified in view of Emberling, Hennessy and Nair teaches all the limitations of claim 14 as stated above. Further, Mansell as modified in view of Emberling, Hennessy and Nair teaches wherein the processor is configured to: receive the scaling value from the third register; and multiply the matrix multiplication output value with the scaling value (Emberling paragraphs [0028-0029 and 0031]).
Regarding claim 17, Mansell as modified in view of Emberling, Hennessy and Nair teaches all the limitations of claim 12 as stated above. Further, Mansell as modified in view of Emberling, Hennessy and Nair teaches wherein a bias is applied to the matrix multiplication output value before the post processing operation (Emberling Fig. 5 and paragraphs [0028 and 0031] bias – bias value 505/535). The motivation to combine is the same as claim 12.
Response to Arguments
In view of amendments made, the objection to claims 2-6, 8, 12-15, 17 and 21-25 has been withdrawn
In view of amendments made and upon further reconsideration, the 35 U.S.C. 112(b) rejection of the claims 9 and 24 has been withdrawn.
Applicant’s arguments, see remarks page 7-8, filed 09/04/2026, with respect to the 35 U.S.C. 112(b) rejection of claims 3-6 and 13-15 have been fully considered but they are not persuasive.
Applicant argues that it is unclear why a list of alternatives in an open-ended claim necessarily “creates confusion as to what other alternative are intended to be encompassed by the claims”. The cited MPEP § 2173.05 (h) I and § 2117 discuss requirements of Markush groups, which typically recite “selected from the group consist of ... . “ Here, claims 3 and 13 do not recite a Markush group. Markush group is not the only acceptable construction to recite alternatives. As clearly stated in MPEP § 2173.05 (h), “A claim which recites a list of alternatives to define a limitation is an acceptable claim construction which should not necessarily be rejected as confusing under 35 U.S. C 112(b) or as improper.”
Response: Examiner respectfully disagrees. Applicant is merely citing the first paragraph of 2173.05(h) subsection I. The rest of the section explains that “Claims that set forth a list of alternatives from which a selection is to be made are typically referred to as Markush claims” and “A Markush grouping is a closed group of alternatives, i.e., the selection is made from a group "consisting of" (rather than "comprising" or "including") the alternative members. Abbott Labs., 334 F.3d at 1280, 67 USPQ2d at 1196. If a Markush grouping requires a material selected from an open list of alternatives (e.g., selected from the group "comprising" or "consisting essentially of" the recited alternatives), the claim should generally be rejected under 35 U.S.C. 112(b) as indefinite because it is unclear what other alternatives are intended to be encompassed by the claim.” Further, MPEP 2117 subsection I states that “Although the term "Markush claim" is used throughout the MPEP, any claim that recites alternatively usable members, regardless of format, should be treated as a Markush claim”. Therefore, claims 3 and 13 are treated as Markush claims as they recite alternative limitations.
Applicant’s arguments, see remarks page 9-12, filed 09/04/2026, with respect to the rejection(s) of claim(s) 1-6, 8-10, 12-15, 17 and 21-26 under 35 U.S.C. 103 have been fully considered but they are not persuasive.
Applicant argues the following:
1.) the “op” and “funct” field of Hennessey are two arithmetic variants of the same opcode class that are fundamentally different from matrix multiplication. The examiner's generalization of different operations to dispatch between matrix multiplication and a fundamentally different operation is an inferential leap that constitutes impermissible hindsight rather than a teaching, suggestion, or motivation from the references themselves. Nowhere does any of the cited references teach or suggest how to decode and execute instructions having the same instruction format and including a parameter (or field) in the instruction format to indicate matrix multiplication and an operation different from the matrix multiplication. Examiner has not provided how Mansell, Emberling, and Hennessy could be combined to decode and execute instructions having the same instruction format and including a parameter (or field) in the instruction format to indicate matrix multiplication and an operation different from the matrix multiplication.
Response: Applicant is arguing unclaimed features. The claim does not recite any decoding and executing step of the operation different from the matrix multiplication. Furthermore, the claim only requires an operation different from the matrix multiplication and the add/subtract operation of Henessey clearly operations different from a matrix multiplication operation. The claim does not require the operation different from the matrix multiplication is another matrix operation. For the sake of argument that the operation different from the matrix multiplication is another matrix operation, paragraph [0056] of Mansell discloses the opcode defining any other type of arithmetic operation (addition, subtraction etc.) or logical operation (ADD, XOR, etc.) performed on matrix data with respect to Figure 6A. Furthermore, paragraph [0050] of Mansell and page 82 of Hennessy disclosed that the opcode defines the operation of the instruction, and Figure 2.5 of Hennessy discloses different operations having different opcode values. Therefore, it would be obvious to combine Mansell and Hennessy and configure the opcode to have different values for the different operations such as the other type of arithmetic operations (addition, subtraction etc.) or logical operations (ADD, XOR, etc.) to define the different operations that can be performed by the system.
With respect to claims 2-6, 8-10, 12-15, 17 and 21-27, Applicant relied on claim 1 argument, and the grounds for rejection has been modified for the same reasons as claim 1.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlo Waje whose telephone number is (571)272-5767. The examiner can normally be reached 9:00-6:00 M-F.
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/Carlo Waje/Examiner, Art Unit 2182 (571)272-5767
1 Examiner notes that the italicized limitation recites a contingent limitation and that the subsequent steps are not required to be performed if the third parameter of the second instruction does not indicate that the second instruction is for a post processing operation. See claim interpretation section above.
Prosecution Insights